HD404318 Series

Rev. 6.0 Sept. 1998 Description

The HD404318 Series is 4-bit HMCS400-series microcomputer with large-capacity memory designed to increase program productivity. Each microcomputer has an A/D converter and input capture timer built in. They also come with high-voltage I/O pins that can directly drive a fluorescent display. The HD404318 Series includes four chips: the HD404318 with 8-kword ROM; the HD404316 with 6kword ROM; the HD404314 with 4-kword ROM; the HD4074318 with 8-kword PROM. The HD4074318 is a PROM version ZTAT microcomputer. Programs can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features
34 I/O pins One input-only pin 33 input/output pins: 21 pins are high-voltage pins (40 V, max.) On-chip A/D converter (8-bit 8-channel) Three timers One event counter input One timer output One input capture timer 8-bit clock-synchronous serial interface (1 channel) Alarm output Built-in oscillators Ceramic or crystal oscillator External clock drive is also possible

HD404318 Series
Seven interrupt sources Two by external sources Three by timers One each by the A/D converter and serial interface Two low-power dissipation modes Standby mode Stop mode Instruction cycle time 1 s (fosc = 4 MHz)

Ordering Information
Type Mask ROM Model Name HD404314S HD404314H HD404316S HD404316H HD404318S HD404318H ZTAT HD4074318S HD4074318H 8,192 8,192 6,144 ROM (words) 4,096 RAM (digit) 384 Package DP-42S FP-44A DP-42S FP-44A DP-42S FP-44A DP-42S FP-44A

Recommended PROM Programmers and Socket Adapters

PROM Programmer Manufacture DATA I/O Corp. Model Name 121B Socket Adapter Package DP-42S FP-44A AVAL Corp. PKW-1000 DP-42S FP-44A Hitachi Manufacturer Hitachi Model Name HS4318ESS01H HS4318ESH01H HS4318ESS01H HS4318ESH01H

HD404318 Series
Pin Arrangement

RA1/Vdisp R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 R42/AN6 R43/AN7 AV CC V CC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

DP-42S

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

R23 R22 R21 R20 R13 R12 R11 R10 R83 R82 R81 R80 D8 D7 D6 D5 D4/STOPC D3/BUZZ D2/EVNB D1/INT1 D0/INT0

44 43 42 41 40 39 38 37 36 35 34

NC R03 /TOC R02 /SO R01 /SI R00 /SCK RA1/Vdisp R23 R22 R21 R20 R13

TEST RESET OSC1 OSC2 GND AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4

1 2 3 4 5 6 7 8 9 10 11

FP-44A

33 32 31 30 29 28 27 26 25 24 23

R12 R11 R10 R83 R82 R81 R80 D8 D7 D6 D5

R41/AN5 R42/AN6 R43/AN7 AVCC VCC D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC NC

12 13 14 15 16 17 18 19 20 21 22

HD404318 Series
PinDescription
Pin Number Item Symbol DP-42S FP-44A I/O Function 21 10 16 5 39 1 2 3 I I I Applies power voltage Connected to ground Used as a high-voltage output power supply pin when selected by the mask option Cannot be used in user applications. Connect this pin to GND. Resets the MCU Input/output pin for the internal oscillator. Connect these pins to the ceramic or crystal oscillator, or OSC 1 to an external oscillator circuit.

Power supply VCC GND

Vdisp (shared 1 with RA1) Test Reset Oscillator TEST RESET OSC 1 6 7 8

OSC 2 Port D0D 8

9 2230

1721, I/O Input/output pins addressed individually by bits; D0D 8 are all high-voltage I/O pins. Each pin can be 2326 individually configured as selected by the mask option. 39 I One-bit high-voltage input port pin

RA 1 R0 0R0 3, R3 0R4 3 R1 0R2 3, R8 0R8 3 Interrupt Stop clear Serial interface INT0, INT1 STOPC SCK SI SO Timer TOC EVNB Alarm A/D converter BUZZ AVCC

1 25, 1219 3142

4043, I/O Four-bit input/output pins consisting of standard voltage pins 714 2738 I/O Four-bit input/output pins consisting of high voltage pins

22, 23 26 2 3 4 5 24 25 20

17, 18 21 40 41 42 43 19 20 15

I I

Input pins for external interrupts Input pin for transition from stop mode to active mode

I/O Serial interface clock input/output pin I O O I O Serial interface receive data input pin Serial interface transmit data output pin Timer output pin Event count input pin Square waveform output pin Power supply for the A/D converter. Connect this pin as close as possible to the VCC pin and at the same voltage as VCC. If the power supply voltage to be used for the A/D converter is not equal to VCC, connect a 0.1-F bypass capacitor between the AV CC and AV SS pins. (However, this is not necessary when the AV CC pin is directly connected to the VCC pin.) Ground for the A/D converter. Connect this pin as close as possible to GND at the same voltage as GND. I Analog input pins for the A/D converter

AVSS AN 0AN 7

11 1219

6 714

HD404318 Series
Pin Description in PROM Mode
The HD4074318 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM.
Pin Number DP-42S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 FP-44A 39 40 41 42 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 MCU Mode Pin RA 1/V disp R0 0/SCK R0 1/SI R0 2/SO R0 3/TOC TEST RESET OSC 1 OSC 2 GND AVSS R3 0/AN0 R3 1/AN1 R3 2/AN2 R3 3/AN3 R4 0/AN4 R4 1/AN5 R4 2/AN6 R4 3/AN7 AVCC VCC D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC D5 D6 D7 D8 I/O I/O I/O I/O I/O I/O I/O I/O I/O A3 A4 A9 VCC I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I I I O GND GND O0 O1 O2 O3 O4 O5 O6 O7 VCC VCC M0 M1 A1 A2 I I I I I/O I/O I/O I/O I/O I/O I/O I/O VPP RESET VCC I VCC VCC PROM Mode Pin I/O

HD404318 Series
Pin Number DP-42S 31 32 33 34 35 36 37 38 39 40 41 42 FP-44A 27 28 29 30 31 32 33 34 35 36 37 38 MCU Mode Pin R8 0 R8 1 R8 2 R8 3 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PROM Mode Pin CE OE A13 A14 A5 A6 A7 A8 A0 A10 A11 A12 I/O I I I I I I I I I I I I

I/O: Input/output pin; I: Input pin; O: Output pin

HD404318 Series
Block Diagram
STOPC RESET OSC1 OSC2 TEST GND

INT0 Interrupt control INT1

System control D0 RAM (384 4 bits) D port D1 D2 D3 D4 D5 D6 D7 D8 R00 R01 R02 R03 Y (4 bits) Internal address bus R1 port R10 R11 R12 R13

Timer A

W (2 bits) X (4 bits)

VCC

EVNB

Timer B

SPX (4 bits)

TOC

Timer C Internal data bus

SPY (4 bits)

SI SO SCK Serial interface

Internal data bus

R0 port

R2 port

R20 R21 R22 R23

ALU
AVSS

R30 R3 port

AN0

A/D converter

ST (1 bit)

CA (1 bit)

R31 R32 R33

AN7 AVCC A (4 bits) R4 port B (4 bits) BUZZ Buzzer SP (10 bits) Instruction decoder PC (14 bits) R8 port Data bus

R40 R41 R42 R43

R80 R81 R82 R83

High voltage pin

RA port

ROM (4,096 10 bits) (6,144 10 bits) (8,192 10 bits)

Directional signal line

RA1

HD404318 Series
Memory Map
ROM Memory Map Vector Address Area ($0000$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. Zero-Page Subroutine Area ($0000$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000$0FFF (HD404314), $0000$17FF (HD404316), $0000$1FFF (HD404318, HD4074318)): The entire ROM area can be used for program coding.
$0000 Vector address (16 words)

$000F $0010

Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) HD404314 Program (4,096 words) $0FFF $1000 HD404316 Program (6,144 words) $17FF $1800 HD404318, HD4074318 Program (8,192 words) $1FFF

$0000 JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction $0002 (jump to INT 0 routine) $0003 JMPL instruction $0004 (jump to INT 1 routine) $0005 JMPL instruction $0006 (jump to timer A routine) $0007 $0008 JMPL instruction (jump to timer B routine) $0009 $000A JMPL instruction (jump to timer C routine) $000B $000C JMPL instruction $000D (jump to A/D converter routine) $000E JMPL instruction (jump to serial routine) $000F

Note: Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas are to be used.

Figure 1 ROM Memory Map

HD404318 Series
RAM MemoryMap
Initial values after reset $000 RAM-mapped registers $040 $050 Memory registers (MR) $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) W W R/W R/W W W R/W R/W W W R/W R/W 0000 0000
Undefined Undefined

Data (304 digits)

-000 0000 *2/0000

Undefined

*1

$180

00-0000 *2/0000
Undefined

Not used

Not used $3C0 Stack (64 digits) $3FF $016 $017 $018 $019 $01A A/D channel register A/D data register lower A/D data register upper A/D mode register 1 A/D mode register 2 (ACR) (ADRL) (ADRU) (AMR1) (AMR2) W R R W W -000 0000 1000 0000 --00

Not used

$020 Register flag area $023 $024 Port mode register B (PMRB) $025 Port mode register C (PMRC) (TMB2) $026 Timer mode register B2

W W W

0000 00-0 -000

Not used Notes: 1. Two registers are mapped on the same area ($00A, $00B, $00E, $00F). $030 2. Undefined. Not used R: Read only W: Write only R/W: Read/write $033 $034 Port R3 DCR Port R4 DCR (DCR3) (DCR4) W W 0000 0000 Port R0 DCR (DCR0) W 0000

Not used

$03F $00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W

Figure 2 RAM Memory Map and Initial Values

HD404318 Series
Table 1
Item Interrupt flags/mask Interrupt enable flag (IE) Interrupt request flag (IF) Interrupt mask (IM) Bit registers Watchdog timer on flag (WDON) A/D start flag (ADSF) Input capture status flag (ICSF) Input capture error flag (ICEF) I AD off flag (IAOF) RAM enable flag (RAME)

Initial Values of Flags after MCU Reset

Initial Value 0 0 1 0 0 0 0 0 0

RAM Address
$0000

Bit 3
IM0 (IM of INT0)

Bit 2 IF0 (IF of INT0)

Bit 1 RSP (Reset SP bit)

Bit 0
IE (Interrupt enable flag)

$0001

IMTA (IM of timer A)

IMTC (IM of timer C) IMS (IM of serial)

IFTA (IF of timer A) IFTC (IF of timer C)

IM1 (IM of INT1)

IMTB (IM of timer B) IMAD (IM of A/D)

IF1 (IF of INT1)

IFTB (IF of timer B)
IFAD (IF of A/D)

$0002

$0003

IFS (IF of serial)

Interrupt control bits area Bit 3

$020

Bit 2
ADSF (A/D start flag)

Bit 1
WDON (Watchdog on flag)

Bit 0
Not used ICSF (Input capture status flag)

Not used
RAME (RAM enable flag)

$021

IF: Interrupt request flag $022 IM: Interrupt mask IE: Interrupt $023 enable flag SP: Stack pointer

IAOF (IAD off flag)

ICEF (Input capture error flag)

Not used

Register flag area

Figure 3 Interrupt Control Bits and Register Flag Areas Configuration

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HD404318 Series
SEM/SEMD IE IM IAOF IF ICSF ICEF RAME RSP WDON ADSF Not used Note: Not executed Allowed Allowed Not executed Allowed Not executed Inhibited Not executed Inhibited Inhibited Allowed Inhibited Not executed Allowed Allowed Allowed Allowed Allowed REM/REMD TM/TMD

WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instruction must not be executed for ADSF during A/D conversion. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 $3FF Level 1

$3C0

Bit 3 $3FC $3FD $3FE $3FF ST PC 10 CA PC 3

Bit 2 PC13 PC9 PC6 PC2

Bit 1 PC 12 PC 8 PC 5 PC 1

Bit 0 PC11 PC7 PC4 PC0

PC13 PC0 : Program counter ST: Status flag CA: Carry flag

Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position

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HD404318 Series
Registers and Flags

3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) (SPX) (Y) (X) (A)

0 (W) 0

0 Carry Initial value: Undefined, R/W (CA) 0 Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: 1, no R/W 13 (PC) 9 1 1 1 1 5 (SP) 0 (ST) 0

Figure 6 Registers and Flags

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HD404318 Series
Addressing Modes
RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
1 0 3 0 3 0 3 0

Instruction

Opcode

RAM address Register Indirect Addressing

RAM address 0 0 0 1 0 0 Memory Register Addressing

1st instruction word Opcode

0 9

2nd instruction word

Instruction

RAM address Direct Addressing

Figure 7 RAM Addressing Modes

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HD404318 Series
ROM Addressing Modes Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. Current Page Addressing Mode: A program can branch to any address in the current page (256 words per page) by executing the BR instruction. Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page subroutine area ($0000$003F) by executing the CAL instruction. Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the B register by executing the TBR instruction.
1st instruction word
9 3 09

2nd instruction word

0

Opcode

Opcode

Operand

Operand

13

13

Program counter Direct Addressing

Program counter 0 0 0 0 0 0 0 0 Zero-Page Addressing

Operand Opcode
9 7 0 9 3 0 7 3 0

Operand
13 0

Opcode
13

A
0

Program counter * * * * * * Current Page Addressing

Program counter 0 0 Table Data Addressing

Figure 8 ROM Addressing Modes

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HD404318 Series
Table 2 Instruction Set Classification
Function Transferring constants to the accumulator, B register, and RAM. Transferring contents of the B, Y, SPX, SPY, or memory registers to the accumulator Available when accessing RAM in register indirect addressing mode Transferring data between the accumulator and memory. Number of Instructions 4 8 13 10

Instruction Type Immediate Register-to-register RAM addressing RAM register Arithmetic Compare

Performing arithmetic operations with the contents of the accumulator, 25 B register, or memory. Comparing contents of the accumulator or memory with a constant 12 6 8

RAM bit manipulation Bit set, bit reset, and bit test. ROM addressing Input/output Control Branching and jump instructions based on the status condition.

Controlling the input/output of the R and D ports; ROM data reference 11 with the P instruction Controlling the serial communication interface and low-power dissipation modes. 4 Total: 101 instructions

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HD404318 Series
Interrupts

$000,0 IE (RESET, STOPC) $000,2 INT0 interrupt IF0 $000,3 IM0 $001,0 INT1 interrupt IF1 $001,1 IM1 $001,2 Timer A interrupt IFTA $001,3 IMTA $002,0 Timer B interrupt IFTB $002,1 IMTB $002,2 Timer C interrupt IFTC $002,3 IMTC $003,0 A/D interrupt IFAD $003,1 IMAD $003,2 Serial interrupt IFS $003,3 IMS Priority Controller Priority Order Vector Address $0000 1 $0002 2 $0004 3 $0006 4 $0008 5 $000A 6 $000C 7 $000E Interrupt request

Figure 9 Interrupt Control Circuit

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HD404318 Series
Instruction cycles 1 2 3 4 5 6

Instruction execution*

Interrupt acceptance

Stacking IE reset Vector address generation

Execution of JMPL instruction at vector address

Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction.

Execution of instruction at start address of interrupt routine

Figure 10 Interrupt Processing Sequence

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HD404318 Series
Operating Modes
The MCU has three operating modes as shown in table 3. Transitions between operating modes are shown in figure 11. Table 3
Function System oscillator CPU RAM Timer A Timers B, C Serial interface A/D I/O

Operations in Each Operating Mode

Active Mode OP OP OP OP OP OP OP OP Standby Mode OP Retained Retained OP OP OP OP Retained Stop Mode Stopped Reset Retained Reset Reset Reset Reset Reset

Note: OP implies in operation

18

,
    
  , 

HD404318 Series
Reset by RESET input or by watchdog timer RAME = 0 RAME = 1 RESET 2 RESET 1 Standby mode Active mode

STOPC

Stop mode

fOSC: Oscillate CPU: Stop

SBY instruction Interrupt

fOSC: Oscillate CPU: fcyc PER: fcyc

STOP instruction

fOSC: Stop

CPU: Stop

PER: fcyc

PER: Stop

fOSC: Main oscillation frequency fOSC/4 CPU: System clock

fcyc:

PER: Clock for other peripheral functions

Figure 11 MCU Status Transitions

In stop mode, the system oscillator is stopped. To ensure a proper oscillation stabilization period of at least tRC when clearing stop mode, execute the cancellation according to the timing chart in figure12.
Stop mode

Oscillator Internal clock

RESET or STOPC

tres

STOP instruction execution

tres tRC (stabilization period)

Figure 12 Timing of Stop Mode Cancellation

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HD404318 Series
MCU Operation Sequence: The MCU operates in the sequence shown in figure 13 and figure 14. The low-power mode operation sequence is shown in figure 14. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.

Power ON

RESET = 0?

No

Yes
MCU operation cycle

RAME = 0

Yes Reset MCU

IF = 1?

No No
IM = 0 IE = 1

Yes
Instruction RAME = 1 execution

Reset input
SBY/STOP instruction

IE 0 Stack (PC), (CA), (ST)

No

Low-power mode operation cycle (figure 15)

PC (PC)+1

PC vector address

Figure 13 MCU Operating Sequence (Power ON)

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HD404318 Series
Low-power mode operation cycle

IF = 1 and IM = 0?

No

Yes
Standby mode

Stop mode

No

IF = 1 and IM = 0?

No

STOPC = 0?

Yes Hardware NOP execution Hardware NOP execution

Yes

RAME = 1

PC Next Iocation

PC Next Iocation

Reset MCU

Instruction execution

MCU operation cycle

Figure 14 MCU Operating Sequence (Low-Power Mode Operation)

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HD404318 Series
Oscillator Circuit
Figure 15 shows a block diagram of the clock generation circuit.

OSC2 OSC1

1/4 System fOSC division oscillator circuit

fcyc tcyc

Timing generator circuit

CPU

CPU with ROM, RAM, registers, flags, and I/O

PER

Peripheral function interrupt

Figure 15 Clock Generation Circuit

TEST RESET OSC1 OSC2 GND AVSS

Figure 16 Typical Layout of Crystal and Ceramic Oscillator

22

HD404318 Series
Table 4 Oscillator Circuit Examples
Circuit Configuration External clock operation
External oscillator

Circuit Constants

OSC 1

Open

OSC 2

Ceramic oscillator (OSC1, OSC 2)

C1 OSC1 Ceramic Rf OSC2 C2 GND

Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20%

Crystal oscillator (OSC1, OSC 2)

C1 OSC1 Crystal Rf OSC2 C2 GND L OSC1 CO CS RS OSC2

Rf = 1 M 20% C1 = C2 = 10 to 22 pF 20% Crystal: Equivalent to circuit shown below C0 = 7 pF max. RS = 100 max.

Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC 2, and elements should be as short as possible, and must not cross other wiring (see figure 16).

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HD404318 Series
I/O Ports
The MCU has 33 input/output pins (D0D 8, R0R4, R8) and one input-only pin (RA1). The following describes the features of the I/O ports. The 21 pins consisting of D0D8, R1, R2, and R8 are all high-voltage I/O pins. RA1 is a high-voltage input-only pin. These high-voltage pins can be equipped with or without pull-down resistance, as selected by the mask option. All standard output pins are CMOS output pins. However, the R02/SO pin can be programmed for NMOS open-drain output. In stop mode, input/output pins go to the high-impedance state All standard input/output pins have pull-up MOS built in, which can be individually turned on or off by software Table 5 Control of Standard I/O Pins by Program
0 0 0 PMOS NMOS Pull-up MOS Note: indicates off. 1 1 0 On 1 On 1 0 0 1 On 1 0 On 1 On On

MIS3 (bit 3 of MIS) DCR PDR CMOS buffer

Data control register DCR0, DCR3, DCR4 Bit Initial value Read/Write Bit name 3 0 W DCR03, DCR33, DCR43,

(DCR0: $030, DCR3: $033, DCR4: $034)

2 0 W

1 0 W

0 0 W Bits 0 to 3 CMOS Buffer Control 0 1 CMOS buffer off (high impedance) CMOS buffer on

DCR02, DCR01, DCR00, DCR32, DCR31, DCR30, DCR42, DCR41, DCR40

Correspondence between ports and DCR bits Register DCR0 DCR3 DCR4 Bit 3 R03 R33 R43 Bit 2 R02 R32 R42 Bit 1 R01 R31 R41 Bit 0 R00 R30 R40

Figure 17 Data Control Register (DCR)

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HD404318 Series
Table 6
I/O Pin Type Input/output pins

Circuit Configurations of Standard I/O Pins

Circuit
VCC HLT VCC Pull-up control signal Buffer control signal Output data Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal MIS3 DCR MIS2 PDR MIS3 DCR PDR

Pins R0 0, R0 1, R0 3 R3 0R3 3, R4 0R4 3

R0 2

Output data Input data Input control signal

Peripheral function pins

Input/ output pins

VCC

HLT VCC Pull-up control signal MIS3

SCK

Output data Input data SCK

SCK

Output pins

VCC

HLT VCC Pull-up control signal MIS3

SO

PMOS control signal Output data

MIS2 SO HLT

VCC

TOC

VCC

Pull-up control signal

MIS3

Output data

TOC

Notes on next page.

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HD404318 Series
I/O Pin Type Peripheral function pins Input/ pins Circuit
VCC HLT MIS3 PDR SI

Pins SI

Input data VCC

AN 0AN 7
HLT MIS3 PDR A/D input

Input control

Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins the enter high-impedance state. 2. The HLT signal is 1 in active and standby modes.

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HD404318 Series
Table 7
I/O Pin Type Input/output pins

Circuit Configurations for High-Voltage Input/Output Pins

With Pull-Down Resistance
VCC HLT Output data Pull-down resistance Vdisp Input data Input control signal Input control signal

Without Pull-Down Resistance

VCC HLT Output data Input data

Pins D0D 8, R1 0R1 3, R2 0R2 3, R8 0R8 3

Input pins
Input control signal

Input data

RA 1

Peripheral function pins

Output pins

VCC

HLT Output data

VCC

BUZZ
HLT Output data

Pull-down resistance Vdisp

Input pins
Pull-down resistance Vdisp

Input data

Input data

INT0, INT1, EVNB, STOPC

Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins the enter high-impedance state. 2. The HLT signal is 1 in active and standby modes. 3. The circuits of HD4074318 are without pull-down resistance.

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HD404318 Series
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 0 W PMRA3 2 0 W 1 0 W 0 0 W

PMRA2 PMRA1 PMRA0 PMRA0 R02/SO Mode Selection R02 SO R01/SI Mode Selection R01 SI

PMRA2 0 1 PMRA3 0 1

R03/TOC Mode Selection R03 TOC D3/BUZZ Mode Selection D3 BUZZ

0 1 PMRA1 0 1

Figure 18 Port Mode Register A (PMRA)

Port mode register B (PMRB: $024) Bit Initial value Read/Write Bit name 3 0 W 2 0 1 0 0 0

W W W * PMRB2 PMRB1 PMRB0 PMRB3 PMRB0 D0/INT0 Mode Selection D0 INT0 D1/INT1 Mode Selection D1 INT1

PMRB2 D2/EVNB Mode Selection 0 1 D2 EVNB

0 1 PMRB1 0 1

PMRB3 D4/STOPC Mode Selection 0 1 D4 STOPC

Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not reset but retains its value.

Figure 19 Port Mode Register B (PMRB)

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HD404318 Series
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0

Not used Not used

MIS3 0 1

Pull-Up MOS On/Off Selection Pull-up MOS off Pull-up MOS on (refer to table 5)

MIS2 0 1

CMOS Buffer On/Off Selection for Pin R02/SO CMOS on CMOS off

Note: The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

Figure 20 Miscellaneous Register (MIS)

29

HD404318 Series
Prescaler
The MCU has a built-in prescaler labeled as prescaler S (PSS), which divides the system clock and then outputs divided clock signals to the peripheral function modules, as shown in figure21.

Timer A Timer B Prescaler S Timer C Serial

System clock

Clock selector

Figure 21 Prescaler Output Supply

30

HD404318 Series
Timers
The MCU has three built-in timers: A, B, and C. The functions of each timer are listed in table 7. Timer A Timer A is an 8-bit free-running timer that has the following features: One of eight internal clocks can be selected from prescaler S according to the setting of timer mode register A (TMA: $008) An interrupt request can be generated when timer counter A (TCA) overflows Input clock frequency must not be modified during timer A operation Table 7
Functions Clock source Prescaler S External event Timer functions Free-running Event counter Reload Watchdog Input capture Timer output PWM

Timer Functions
Timer A Available Available Timer B Available Available Available Available Available Available Timer C Available Available Available Available Available

31

HD404318 Series
Timer A interrupt request flag (IFTA)

Timer counter A (TCA) Overflow Selector

2 4 8 32 128 512 1024 2048

System clock

PER

Prescaler S (PSS)

3 Timer mode register A (TMA)

Figure 22 Timer A Block Diagram

Timer mode register A (TMA: $008) Bit Initial value Read/Write Bit name 3 Not used 2 0 W TMA2 1 0 W TMA1 0 0 W TMA0

Source Input clock TMA2 TMA1 TMA0 Prescaler frequency 0 0 0 1 1 0 1 1 0 0 1 1 0 1 PSS PSS PSS PSS PSS PSS PSS PSS 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc

Figure 23 Timer Mode Register A (TMA)

32

Internal data bus

HD404318 Series
Timer B Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features. These are described as follows. By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler S can be selected, or timer B can be used as an external event counter By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected By setting timer write register BL, BU (TWBL, BU: $00A, $00B), timer counter B (TCB) can be written to during reload timer operation By setting timer read register BL, BU (TRBL, BU: $00A, $00B), the contents of timer counter B can be read out Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as an external event An interrupt can be requested when timer counter B overflows or when a trigger input edge is received during input capture operation

33

HD404318 Series
Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU)

Timer read register B lower (TRBL)

Clock Internal data bus Free-running timer control signal Timer counter B (TCB) Overflow

Timer write register B upper (TWBU) Timer write register B lower (TWBL)

EVNB Edge detector PER

Selector 2 4 8 32 128 512 2048

3 Timer mode register B1 (TMB1)

System clock

Prescaler S (PSS) Edge detection control signal

Timer mode register B2 (TMB2)

Figure 24 Timer B Free-Running and Reload Operation Block Diagram

34

HD404318 Series
Input capture status flag (ICSF) Error controller Input capture error flag (ICEF) Interrupt request flag of timer B (IFTB)

Timer read register BU (TRBU) Timer read register B lower (TRBL) EVNB Edge detector Read signal Clock Overflow Internal data bus 35 Timer counter B (TCB) Input capture timer control signal

Selector 2 4 8 32 128 512 2048

3 Timer mode register B1 (TMB1)

System clock

PER

Prescaler S (PSS)

Edge detection control signal Timer mode register B2 (TMB2)

Figure 25 Timer B Input Capture Operation Block Diagram

HD404318 Series
Timer mode register B1 (TMB1: $009) Bit Initial value Read/Write Bit name 3 0 W TMB13 2 0 W TMB12 1 0 W TMB11 0 0 W TMB10

TMB13 0 1

Free-Running/Reload Timer Selection Free-running timer Reload timer

TMB12 0

TMB11 0

TMB10 0 1

Input Clock Period and Input Clock Source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc D2/EVNB (external event input)

0 1

0 1

0 1

Figure 26 Timer Mode Register B1 (TMB1)

Timer mode register B2 (TMB2: $026) Bit Initial value Read/Write Bit name 3 2 0 W 1 0 W TMB21 TMB21 0 0 0 W TMB20 TMB20 0 1 1 0 1 TMB22 0 1 EVNB Edge Detection Selection No detection Falling edge detection Rising edge detection Rising and falling edge detection

Not used TMB22

Free-Running/Reload and Input Capture Selection Free-Running/Reload Input capture

Figure 27 Timer Mode Register B2 (TMB2)

36

HD404318 Series
Timer C Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are described as follows. By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S can be selected By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output (PWM output) is enabled By setting timer write register CL, CU (TWCL, CU: $00E, $00F), timer counter C (TCC) can be written to By setting timer read register CL, CU (TRCL, CU: $00E, $00F), the contents of timer counter C can be read out An interrupt can be requested when timer counter C overflows Timer counter C can be used as a watchdog timer for detecting runaway program

37

HD404318 Series
System reset signal Watchdog on flag (WDON) Watchdog timer controller Interrupt request flag of timer C (IFTC)

Timer read register CU (TRCU) TOC Timer output control logic Timer read register C lower (TRCL)

Clock

Timer counter C (TCC) Timer output control signal

Overflow Internal data bus

Timer write register C upper (TWCU) Timer write register C lower (TWCL)

Selector 2 4 8 32 128 512 1024 2048

Free-running timer control signal 3

System PER clock

Prescaler S (PSS)

Timer mode register C (TMC)

Port mode register A (PMRA)

Figure 28 Timer C Block Diagram

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HD404318 Series
Timer mode register C (TMC: $00D) Bit Initial value Read/Write Bit name 3 0 W TMC3 2 0 W TMC2 1 0 W TMC1 0 0 W TMC0

TMC3 0 1

Free-Running/Reload Timer Selection Free-running timer Reload timer

TMC2 0

TMC1 0

TMC0 0 1

Input Clock Period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc

0 1

0 1

0 1

Figure 29 Timer Mode Register C (TMC)

T (N + 1) TMC3 = 0 (Free-running timer) T TMC3 = 1 (Reload timer) T (256 N) Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are determined by timer mode register C.) N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.) T 256

Figure 30 PWM Output Waveform

39

HD404318 Series
$FF + 1 Overflow Timer C count value

$00

Time

CPU operation

Normal operation

Timer C clear

Normal operation

Timer C clear

Program runaway

Reset

Normal operation

Figure 31 Watchdog Timer Operation Flowchart Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 8. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 8 PWM Output Following Update of Timer Write Register
PWM Output Mode Free running Timer Write Register is Updated during High PWM Output
Timer write register updated to value N

Timer Write Register is Updated during Low PWM Output

Timer write register updated to value N

Interrupt request

Interrupt request

T (255 N) T (N + 1)

T (N' + 1) T (255 N) T (N + 1)

Reload

Timer write register updated to value N

Interrupt request

Timer write register updated to value N

Interrupt request

T (255 N)

T T (255 N) T

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HD404318 Series
Alarm Output Function
The MCU has an alarm output function built in. By setting port mode register C (PMRC: $025), one of four alarm frequencies supplied from the PSS can be selected. Table 9
PMRC Bit 3 0 Bit 2 0 1 1 0 1 System Clock Divisor 2048 1024 512 256

Port Mode Register C

BUZZ Alarm output controller

Alarm output control signal

Selector 1024 2048

2 Port mode register C (PMRC)

256

System PER clock

Prescaler S (PSS)

Figure 32 Alarm Output Function Block Diagram

512

Internal data bus 41

Port mode register A (PMRA)

HD404318 Series
Serial Interface
The MCU has a one-channel serial interface built in with the following features. One of 13 different internal clocks or an external clock can be selected as the transmit clock. The internal clocks include the six prescaler outputs divided by two and by four, and the system clock. During idle states, the serial output pin can be controlled to be high or low output Transmit clock errors can be detected An interrupt request can be generated after transfer has completed when an error occurs Table 10
SMR Bit 3 1

Serial Interface Operating Modes

PMRA Bit 1 0 Bit 0 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode

42

HD404318 Series
Octal counter (OC) Idle controller SCK I/O controller SI Clock Transfer control signal Serial data register (SR) Internal data bus 43 Serial interrupt request flag (IFS)

SO

Selector 3 2 8 32 128 512 2048 Serial mode register (SMR)

System clock

PER

Prescaler S (PSS)

Selector

1/2

1/2

Port mode register C (PMRC)

Figure 33 Serial Interface Block Diagram

HD404318 Series
STS wait state (Octal counter = 000, transmit clock disabled)

MCU reset

SMR write STS instruction

Transmit clock Transmit clock wait state (Octal counter = 000)

SMR write (IFS 1)

Transfer state (Octal counter = 000)

8 transmit clocks or STS instruction (IFS 1)

External clock mode

SMR write

STS wait state (Octal counter = 000, transmit clock disabled)

MCU reset

Continuous clock output state (PMRA 0, 1 = 0, 0)

SMR write STS instruction

8 transmit clocks or SMR write (IFS 1)

Transmit clock
Transmit clock Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000)

STS instruction (IFS 1)

Internal clock mode

Figure 34 Serial Interface State Transitions

Transmit clock 1 Serial output data Serial input data latch timing LSB 2 3 4 5 6 7 8 MSB

Figure 35 Serial Interface Timing

44


,  " !  

Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SMR write External clock selection Output level control in idle states PMRC write SRL, SRU write STS instruction Data write for transmission SCK pin (input) SO pin Undefined LSB IFS External clock mode Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SMR write Internal clock selection Output level control in idle states PMRC write SRL, SRU write STS instruction SCK pin (output) SO pin Data write for transmission Undefined LSB IFS Internal clock mode

HD404318 Series
Transmit clock wait state STS wait state

Dummy write for state transition

Output level control in idle states

MSB

Flag reset at transfer completion

STS wait state

Output level control in idle states

MSB

Flag reset at transfer completion

Figure 36 Example of Serial Interface Operation Sequence

45

HD404318 Series
Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write IFS = 1 Yes No Normal termination Transmit clock wait state State SCK pin (input) Noise 1 2 3 4 SMR write IFS

Transmit clock erors are detected as illustrated in figure 37.

Transmit clock error processing

Transmit clock error detection flowchart Transmit clock wait state Transfer state

Transfer state

7 8 Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set.

Flag set because octal counter reaches 000. Transmit clock error detection procedure

Flag reset at transfer completion.

Figure 37 Transmit Clock Error Detection

46

HD404318 Series
Table 11
PMRC Bit 0 0

Transmit Clock Selection

SMR Bit 2 0 Bit 1 0 Bit 0 0 1 1 0 1 1 0 0 1 System Clock Divisor 2048 512 128 32 8 2 4096 1024 256 64 16 4 Transmit Clock Frequency 4096t cyc 1024t cyc 256t cyc 64t cyc 16t cyc 4t cyc 8192t cyc 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc

0 1

0 1

0 1

Serial mode register (SMR: $005) Bit Initial value Read/Write Bit name 3 0 W SMR3 2 0 W SMR2 1 0 W SMR1 0 0 W SMR0

SMR3 0 1

R00/SCK Mode Selection R00 SCK

SMR2 0

SMR1 0

SMR0 0 1

SCK Output

Clock Source Prescaler

Prescaler Division Ratio Refer to table 11

0 1

0 1

0 1

Output Input

System clock External clock

Figure 38 Serial Mode Register (SMR)

47

HD404318 Series
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 0 W PMRC3 2 0 W PMRC2 1
Undefined

0 0 W PMRC0

W PMRC1

PMRC0 Alarm output function. Refer to table 9. 0 1 PMRC1 0 1

Serial Clock Division Ratio Prescaler output divided by 2 Prescaler output divided by 4 Output Level Control in Idle States Low level High level

Figure 39 Port Mode Register C (PMRC)

48

HD404318 Series
A/D Converter
The MCU also contains a built-in A/D converter that uses a sequential comparison method with a resistance ladder. It can perform digital conversion of eight analog inputs with 8-bit resolution. The following describes the A/D converter. A/D mode register 1 (AMR1: $019) is used to select digital or analog ports A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or analog ports The A/D channel register (ACR: $016) is used to select an analog input channel A/D conversion is started by setting the A/D start flag (ADSF: $020, 2) to 1. After the conversion is completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is cleared to 0 By setting the IAD off flag (IAOF: $021, 2) to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode

4 A/D interrupt request flag (IFAD) A/D mode register 1 (AMR1)

3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

A/D mode register 2 (AMR2) A/D data register (ADRU, L) Internal data bus 49

Selector + Comp

Encoder

A/D controller

AVCC

Control signal for conversion time

A/D channel register (ACR)

A/D start flag (ADSF) AVSS D/A

IAD off flag (IAOF)

Operating mode signal (1 in stop mode)

Figure 40 A/D Converter Block Diagram

HD404318 Series
Notes on Usage Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF) Do not write to the A/D start flag during A/D conversion Data in the A/D data register during A/D conversion is undefined Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop mode. In addition, to save power while in stop mode, all current flowing through the converters resistance ladder is cut off. If the power supply for the A/D converter is to be different from VCC, connect a 0.1-F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain pulled up.
A/D mode register 1 (AMR1: $019) Bit Initial value Read/Write Bit name 3 0 W AMR13 2 0 W AMR12 1 0 W AMR11 0 0 W AMR10 AMR10 AMR12 0 1 AMR13 0 1 R32/AN2 Mode Selection R32 AN2 R33/AN3 Mode Selection R33 AN3 0 1 AMR11 0 1 R30/AN0 Mode Selection R30 AN0 R31/AN1 Mode Selection R31 AN1

Figure 41 A/D Mode Register 1 (AMR1)

50

HD404318 Series
A/D mode register 2 (AMR2: $01A) Bit Initial value Read/Write Bit name 3 2 1 0 W 0 0 W AMR20

Not used Not used AMR21

AMR20 0 1 AMR21 0 1

Conversion Time 34tcyc 67tcyc R4/AN4AN7 Pin Selection R4 AN4AN7

Figure 42 A/D Mode Register (AMR2)

A/D channel register (ACR: $016) Bit Initial value Read/Write Bit name 3 Not used 2 0 W ACR2 1 0 W ACR1 0 0 W ACR0

ACR2 ACR1 ACR0 0 0 0 1 1 0 1 1 0 0 1 1 0 1

Analog Input Selection AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

Figure 43 A/D Channel Register (ACR)

51

HD404318 Series
A/D start flag (ADSF: $020, bit 2) Bit Initial value Read/Write Bit name 3 Not used 2 0 R/W ADSF 1 0 W 0

WDON Not used

A/D Start Flag (ADSF) 0 1 A/D conversion completed A/D conversion started

WDON Refer to the description of timers

Figure 44 A/D Start Flag (ADSF)

IAD off flag (IAOF: $021, bit 2) Bit Initial value Read/Write Bit name 3 0 R/W RAME 2 0 R/W IAOF 1 0 R/W ICEF 0 0 R/W ICSF

IAD Off Flag (IAOF) 0 1 IAD current flows IAD current is cut off

ICSF Refer to the description of timers

ICEF RAME Refer to the description of timers Refer to the description of operating modes

Figure 45 IAD Off Flag (IAOF)

52

HD404318 Series
ADRU: $018 3 2 1 0 3 ADRL: $017 2 1 0

MSB bit 7

LSB bit 0

RESULT

Figure 46 A/D Data Registers

A/D data register (lower digit) (ADRL: $017) Bit Initial value Read/Write Bit name 3 0 R ADRL3 2 0 R ADRL2 1 0 R ADRL1 0 0 R ADRL0

Figure 47 A/D Data Register Lower Digit (ADRL)

A/D data register (upper digit) (ADRU: $018) Bit Initial value Read/Write Bit name 3 1 R ADRU3 2 0 R ADRU2 1 0 R ADRU1 0 0 R ADRU0

Figure 48 A/D Data Register Upper Digit (ADRU)

53

HD404318 Series
Notes on Mounting
Assemble all parts including the HD404318 Series on a board, noting the points described below. 1. Connect layered ceramic type capacitors (about 0.1 F) between AVCC and AVSS , between VCC and GND, and between used analog pins and AVSS . 2. Connect unused analog pins to AVSS .
1. When not using an A/D converter.

VCC

AVCC AN 0 0.1 F AN 1 to AN 7

GND

AVSS

2. When using pins AN 0 and AN 1 but not using AN 2 to AN 7 . AVCC AN 0 AN 1 AN 2 to AN 7 GND 0.1 F 3 AVSS

VCC

3. When using all analog pins. AVCC AN 0 AN 1 AN 2 to AN 7 AVSS 0.1 F 9

VCC

GND

Figure 49 Example of Connections (1)

54

HD404318 Series
Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 50. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2.

VCC C1 C2

VCC

GND

GND

Figure 50 Example of Connections (2)

55

HD404318 Series
Absolute Maximum Ratings
Item Supply voltage Programming voltage Pin voltage Symbol VCC VPP VT Value 0.3 to +7.0 0.3 to +14.0 Unit V V 1 2 3 4 5 6, 7 6, 8 9, 10 10, 11 Notes

0.3 to VCC + 0.3 V VCC 45 to VCC + 0.3 V mA mA mA mA mA mA C C

Total permissible input current Total permissible output current Maximum input current

IO IO IO

70 150 4 20

Maximum output current

I O

4 30

Operating temperature Storage temperature

Topr Tstg

20 to +75 55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP ) of HD4074318. 2. Applies to all standard voltage pins. 3. Applies to high-voltage pins. 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to ports R3 and R4. 8. Applies to port R0. 9. Applies to ports R0, R3, and R4. 10. The maximum output current is the maximum current flowing from V CC to each I/O pin. 11. Applies to ports D0D 8, R1, R2, and R8.

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HD404318 Series
Electrical Characteristics
DC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC 40 V to VC C, T a = 20 to +75C, unless otherwise specified)
Item Input high voltage Symbol Pins VIH RESET, SCK, SI, INT0, INT1, STOPC, EVNB OSC 1 Input low voltage VIL RESET, SCK, SI INT0, INT1, STOPC, EVNB OSC 1 Output high voltage Output low voltage I/O leakage current VOH VOL |IIL| 0.3 0.5 0.4 1 V V V A I OH = 0.5 mA I OL = 0.4 mA Vin = 0 V to VCC 1 SCK, SO, TOC VCC 0.5 SCK, SO, TOC RESET, SCK, SI, SO, TOC, OSC 1 INT0, INT1, STOPC, EVNB Current dissipation in active mode I CC VCC 5.0 mA VCC = 5 V, f OSC = 4 MHz Current dissipation in standby mode Current dissipation in stop mode I SBY VCC 8.0 2.0 mA mA VCC = 5 V, f OSC = 4 MHz I STOP VCC 10 A VCC = 5 V 4, 5 2, 6 3 2, 5 20 A Vin = VCC 40 to VCC 1 VCC 40 0.2V CC V VCC 0.5 0.3 VCC + 0.3 0.2V CC V V Min 0.8V CC Typ Max VCC + 0.3 Unit Test Condition V Notes

Stop mode VSTOP retaining voltage VCC 2

20

A V

4, 6

Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. I CC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST at GND R0, R3, R4 at VCC D0D 8, R1, R2, R8, RA1 at V disp

57

HD404318 Series
3. I SBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Standby mode Pins: RESET at V CC TEST at GND R0, R3, R4 at VCC D0D 8, R1, R2, R8, RA1 at V disp 4. This is the source current when no I/O current is flowing. Test conditions: Pins: R0, R3, R4 at VCC D0D 8, R1, R2, R8, RA1 at GND 5. Applies to the HD404314, HD404316 and HD404318. 6. Applies to the HD4074318.

I/O Characteristics for Standard Pins (V CC = 4.0 to 5.5 V, GND = 0 V, V disp = V CC 40 V to VCC, Ta = 20 to +75C, unless otherwise specified)
Item Input high voltage Symbol Pins VIH R0, R3, R4 R0, R3, R4 R0, R3, R4 R3, R4 R0 Input leakage current Pull-up MOS |IIL| I PU R0, R3, R4 R0, R3, R4 Min 0.7V CC 0.3 Typ Max Unit Test Condition Note

VCC + 0.3 V 0.3V CC 0.4 2.0 1 300 180 V V V V A A A I OH = 0.5 mA I OL = 1.6 mA I OL = 10 mA Vin = 0 V to VCC VCC = 5 V, Vin = 0 V 1 2 3

Input low voltage VIL Output high voltage Output low voltage VOH VOL

VCC 0.5 30 30 150 80

Notes: 1. Output buffer current is excluded. 2. Applies to the HD404314, HD404316, and HD404318. 3. Applies to the HD4074318.

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HD404318 Series
I/O Characteristics for High-Voltage Pins (V CC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC 40 V to VCC, T a = 20 to +75C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Symbol VIH VIL VOH Pins D0D 8, R1, R2, R8, RA 1 D0D 8, R1, R2, R8, RA 1 D0D 8, R1, R2, R8, BUZZ VCC 2.0 VCC 1.0 Output low voltage VOL D0D 8, R1, R2, R8, BUZZ I/O leakage current |IIL| D0D 8, R1, R2, R8, RA1, BUZZ D0D 8, R1, R2, R8, BUZZ 200 600 1000 A Vdisp = VCC 35 V, Vin = VCC 1 VCC 37 V 20 A 150 k at VCC 40 V 2 Vin = VCC 40 V to VCC 3 V V I OH = 10 mA I OH = 4 mA Vdisp = VCC 40 V 1 VCC 3.0 V I OH = 15 mA VCC 40 0.3V CC V Min 0.7V CC Typ Max Unit Test Condition Note

VCC + 0.3 V

VCC 37 V

Pull-down I PD MOS current

Notes: 1. Applies to pins with pull-down MOS as selected by the mask option . 2. Applies to pins without pull-down MOS as selected by the mask option. 3. Excludes output buffer current.

A/D Converter Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC 40 V to VCC, Ta = 20 to +75C, unless otherwise specified)
Item Analog supply voltage Analog input voltage Symbol Pins AVCC AVin AVCC Min Typ Max Unit Test Condition Note 1

VCC 0.3 VCC 8

VCC + 0.3 V AVCC 200 30 8 8 2.0 67 V A pF Bit Chan nel LSB t cyc M VCC = AVCC = 5.0 V

AN 0AN 7 AVSS AN 0AN 7 8 0 34 AN 0AN 7 1

Current flowing I AD between AV CC and AVSS Analog input capacitance Resolution Number of input channels Absolute accuracy Conversion time Input impedance Note: CA in

1. Connect this to V CC if the A/D converter is not used.

59

HD404318 Series
AC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC 40 V to VCC, T a = 20 to +75C)
Item Clock oscillation frequency Instruction cycle time Oscillation stabilization time (ceramic oscillator) Oscillation stabilization time (crystal oscillator) Symbol Pins f OSC t cyc t RC t RC OSC 1, OSC 2 OSC 1, OSC 2 OSC 1 OSC 1 OSC 1 OSC 1 INT0, INT1, EVNB t IL t RSTL t STPL t RSTr t STPr Cin INT0, INT1, EVNB RESET STOPC RESET STOPC 2 1 20 20 30 30 180 t cyc t RC ms ms pF pF pF f = 1 MHz, Vin = 0 V 6 7 4 5 4 5 2 t cyc 3 OSC 1, OSC 2 Min 0.4 0.89 92 92 2 Typ 4 1 Max 4.5 10 7.5 40 20 20 Unit MHz s ms ms ns ns ns ns t cyc 1 1 2 2 2 2 3 Test Condition System clock divided by 4 Note

External clock high width t CPH External clock low width External clock rise time External clock fall time INT0, INT1, EVNB high widths INT0, INT1, EVNB low widths RESET low width STOPC low width RESET rise time STOPC rise time Input capacitance t CPL t CPr t CPf t IH

All input pins except TEST TEST

Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After V CC reaches 4.0 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of t RC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. Refer to figure 51. 3. Refer to figure 52. 4. Refer to figure 53. 5. Refer to figure 54. 6. Applies to the HD404314, HD404316, and HD404318. 7. Applies to the HD4074318.

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HD404318 Series
Serial Interface Timing Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC 40 V to VCC, T a = 20 to +75C, unless otherwise specified) During Transmit Clock Output
Item Symbol Pins SCK SCK SCK SCK SCK SO SI SI Min 1 0.4 0.4 100 200 Typ Max 80 80 300 Unit t cyc t Scyc t Scyc ns ns ns ns ns Test Condition Load shown in figure 56 Load shown in figure 56 Load shown in figure 56 Load shown in figure 56 Load shown in figure 56 Load shown in figure 56 Note 1 1 1 1 1 1 1 1

Transmit clock cycle time t Scyc Transmit clock high width t SCKH Transmit clock low width Transmit clock rise time Transmit clock fall time Serial output data delay time Serial input data setup time t SCKL t SCKr t SCKf t DSO t SSI

Serial input data hold time t HSI

During Transmit Clock Input

Item Symbol Pins SCK SCK SCK SCK SCK SO SI SI Min 1 0.4 0.4 100 200 Typ Max 80 80 300 Unit t cyc t Scyc t Scyc ns ns ns ns ns Load shown in figure 56 Test Condition Note 1 1 1 1 1 1 1 1

Transmit clock cycle time t Scyc Transmit clock high width t SCKH Transmit clock low width Transmit clock rise time Transmit clock fall time Serial output data delay time Serial input data setup time t SCKL t SCKr t SCKf t DSO t SSI

Serial input data hold time t HSI Note: 1. Refer to figure 55.

OSC1 1/fCP VCC 0.5 V 0.5 V tCPr tCPH tCPL tCPf

Figure 51 External Clock Timing

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HD404318 Series
INT0, INT1, EVNB

0.8VCC 0.2VCC

tIH

tIL

Figure 52 Interrupt Timing

RESET 0.8VCC tRSTL 0.2VCC tRSTr

Figure 53 RESET Timing

STOPC 0.8VCC tSTPL 0.2VCC tSTPr

Figure 54 STOPC Timing

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HD404318 Series
t Scyc t SCKf SCK VCC 2.0 V (0.8VCC )* 0.8 V (0.2VCC)* t DSO SO VCC 2.0 V 0.8 V t SSI SI 0.8V CC 0.2VCC t HSI t SCKL t SCKH t SCKr

Note:

*VCC-2.0V and 0.8V are the threshold voltages for transmit clock output. 0.8V CC and 0.2VCC are the threshold voltages for transmit clock input.

Figure 55 Serial Interface Timing

VCC RL = 2.6 k Test point C= 30 pF R= 12 k Hitachi 1S2074 or equivalent

Figure 56 Timing Load Circuit

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HD404318 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404314 and HD404316 as an 8-kword version (HD404318). An 8-kword data size is required to change ROM data to mask manufacturing data since the program used is for an 8-kword version. This limitation applies when using an EPROM or a data base.
ROM 4-kword version: HD404314 Address $1000$1FFF ROM 6-kword version: HD404316 Address $1800$1FFF

$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (4,096 words) $0FFF $1000 Not used $1FFF

$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (6,144 words) $17FF $1800 Not used $1FFF

Fill this area with 1s

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HD404318 Series
HD404314/HD404316/HD404318 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order Customer 1. ROM Size HD404314 HD404316 HD404318 4-kword 6-kword 8-kword Department Name ROM code name LSI number E: With pull-down resistance E Pin name R1 R10 R11 R12 R13 R20 R21 R22 R23 R80 R81 R82 R83 RA1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O option D E

2. I/O Options D: Without pull-down resistance Pin name D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC D5 D6 D7 D8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O option D

R2

R8

3. RA1/Vdisp RA1 without pull-down resistance Vdisp Note: If even only one pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp.

RA

Selected in option (3)

4. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 5. System Oscillator for OSC1 and OSC2 Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz 6. Stop mode Used Not used 7. Package DP-42S FP-44A

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HD404318 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachis sales office for any questions regarding this document or Hitachi semiconductor products.

Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL

NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX

Copyright Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

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