INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl.

2011; 39:783790 Published online 29 April 2010 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.659

A fully-integrated CMOS UWB transceiver for ultra-low-power short-range application

Mengmeng Liu, , Sheng Zhang, Shuo Wang and Runde Zhou
Institute of Microelectronics, Tsinghua University, Beijing 100084, Peoples Republic of China

SUMMARY In short-range UWB communication systems, the low-power design is the most important issue to make UWB technology attractive. A novel trigger receiving algorithm for UWB signals is proposed, which can reduce the system power signicantly at the cost of slight performance degrade. A UWB transceiver based on the trigger receiving algorithm is designed and fabricated in HJTC 0.18 m CMOS process with a total size of 0.45 mm2 . The experimental results show that the total power consumption of the transceiver is only 12 mW at 100 Mb/s data rate from a 1.8 V supply, making it suitable for low-power short-range communication. Copyright 2010 John Wiley & Sons, Ltd.
Received 6 July 2009; Revised 24 September 2009; Accepted 10 October 2009 KEY WORDS:

UWB transceiver; low power; short range

1. INTRODUCTION UWB is recognized as a high-speed, low-power communication technology that can coexist with other wireless systems, which attracts much interest of researchers [1, 2]. Owing to its strictly limited transmitted power, UWB has no advantages in long-range communication, while in the short range, UWB becomes an attractive choice. However, even if in short range, some nonideal factors, such as multipath and narrow band interference, make UWB costly to realize high-speed data transmission, resulting in high-power dissipation and large chip area [35]. Whereas, in shortrange systems especially portable systems, low-power and little chip area are more important than the ultra-high data speed, UWB technology seems competent in these systems: rst, since UWB has huge capacity margin in short range due to its wide bandwidth, the performance degrade brought by structures with low power, low complexity is negligible and can be easily compensated; second, in short-range moderate speed application, multipath is not a thorny problem any more; third, the characteristic of UWB pulses makes some low-complexity processing method and architecture practicable, bringing low power and low cost. Thus, UWB technology is very attractive in low-power short-range application; moreover, the IEEE 802.15.4a has greatly encouraged the development of UWB applications in such eld [6]. This paper aims at low-power short-range UWB systems, proposes a transceiver based on a novel trigger receiving algorithm, which can be implemented and integrated much easily with ultra-low power. The trigger receiving algorithm is discussed in Section 2, its characteristic of ultra-low power is analyzed and demonstrated by simulation. Based on the algorithm, a UWB transceiver
Correspondence

to: Mengmeng Liu, Institute of Microelectronics, Tsinghua University, Beijing 100084, Peoples Republic of China. E-mail: liumm06@mails.tsinghua.edu.cn Copyright 2010 John Wiley & Sons, Ltd.

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is designed and fabricated in 0.18 m CMOS technology. The design and the measurement of the transceiver are presented in Sections 3 and 4.

2. TRIGGER RECEIVING ALGORITHM In most UWB systems, the conventional correlation receiving algorithm is widely used for receiving UWB signals [35], which can be expressed as v=
0 Tb

T (t)s(t) dt
0 n<Nb

T (n)s(n)

(1)

where Tb is the period of receiving data, Ts is the sampling period, Nb = Tb /Ts denotes the number of samples in each data period, T () and s() are local template and received signal, respectively. From Equation (1), it is observed that the sample rate or working frequency of the digital correlation receiver is f s = 1/Ts even if there are no signals at that moment, resulting a power consumption proportional to Ts . However, in short-range moderate speed UWB systems, the data rate, e.g. 20 Mbps, is much lower than the signal bandwidth, e.g. 1 GHz. As a consequence, the receiver sample rate f s is much higher than the data rate Rb , where Rb = 1/Tb , which means in most of the time, the receiver has no input but is still operating, wasting much power with little signicance. Since short-range moderate speed UWB systems have low Spectrum utilization and wide bandwidth, the trigger receiving algorithm, as depicted below in Equation (2), is very suitable for such systems, especially for ultra-low-power case: v max {s(t)} max {s(n)}
0 t<Tb 0 n<Nb

(2)

Equation (2) corresponds to the receiver depicted in Figure 1. As long as the received signal s(t) surpasses the threshold of the comparator (CMP) at any moment during the data period Tb , the high level, i.e. value 1, can be triggered to output Y . This receiving method is called trigger receiving algorithm. From Figure 1, it is obvious that the trigger receiving algorithm is much simpler to implement than the correlation receiving algorithm. The trigger receiver works at the frequency of the data rate Rb , which is much lower than the sample rate of the correlation receiver f s mentioned above. Hence, the trigger receiver has a power consumption proportional to Tb , which is reduced Nb times compared with the correlation receiver. Luckily, in UWB systems, Nb 1 is always satised. Suppose Rb = 20 Mbps, signal bandwidth BW = 1 GHz, or Tb = 50 ns, f s = 2 GHz, we can get Nb = 100; thus, compared with the correlation receiver, the trigger one has a 20 dB lower power consumption. Figure 2 shows the performance of pulse UWB system under the binary symmetric AWGN channel and OOK modulation, using trigger receiver and correlation receiver, respectively. The simulation results indicate that when Nb = 1, the performance of trigger receiver and correlation receiver are the same; however, when the bit-error-rate Pb is below 102 , E b increases about 1 dB if the number of samples Nb increases 10 times by trigger receiver, whereas E b is not relevant to Nb by the traditional correlation receiver. In other words, with the Nb increased by 10 dB, the power consumption of the trigger receiver is reduced by 10 dB, whereas the performance is only decreased by only 1 dB. Whats more, in UWB systems, the transmitted power is quite low, 1 dB of which is negligible considering 10 dB of power consumption of the receiver. As a result, the whole systems can achieve same performance but much lower power dissipation using trigger receiver in short-range moderate speed UWB systems.

s(t) CMP trigger

Figure 1. Block diagram of trigger receiver.

Copyright 2010 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2011; 39:783790 DOI: 10.1002/cta

A FULLY-INTEGRATED CMOS UWB TRANSCEIVER

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Figure 2. Performance of trigger receiver and correlation receiver.

3. TRANSCEIVER ARCHITECTURE AND CIRCUIT DESIGN Based on the trigger receiving algorithm discussed before, a pulse UWB transceiver is designed, aiming at ultra-low-power short-range moderate speed communication, the block diagram of which is described in Figure 3. The transceiver integrated the whole circuits from digital baseband blocks to UWB antenna. The transmitter is mainly comprised of pulse generator, whereas the core of the receiver is trigger receiver and the rest include auto-gain-control (AGC) loop and demodulator. Phase-lock-loop (PLL) generates the multiple frequency clock from the baseband clock clk for receiver digital baseband process. Compared with correlation receivers, the proposed trigger receiver does not need high-speed, high-resolution ADC and the complicated synchronization process in the baseband, what is more, the baseband working frequency is quite lower, leading to low power and low cost. 3.1. Pulse generator UWB pulse generator is shown in Figure 4. Considering baseband data TXD lags the rising edge of the baseband clock clk, the output of the nor-gate is not inuenced by the transition of baseband data, preventing unexpected glitches generated by the gate-controlled clock. A narrow pulse is created at every rising edge of gate-controlled clock. The controllable delay unit is implemented by current-starved inverters, whose delay is verse-proportional to the transistor current from the relationship t p = C L VDD /2I D . The regulated controlling voltage can set the transistor current I D , consequently, the pulse width. 3.2. Trigger receiver Figure 5 depicts the schematic of the VGA and the trigger receiver. VGA uses gate-controlled MOS channel resistance to obtain variable gain, whose dynamic range is designed as 40 dB, and the gain control signals (U , D in Figure 5) are set by a charge pump regulated by the digital back-end, which will be discussed later. CMP utilizes hysteresis structure to suppress the noise, avoiding frequent unwanted overturn, as described on the top of Figure 5. The frequency of receiver clock clk3 is triple the baseband clock clk only to make the digital baseband algorithm, such as phase-offset correct, mulipath remove etc. efcient, which is not indispensable to the analog parts of the transceiver. When a negative-phase pulse arrives at node opl or oph in Figure 5, the rst register will be set to high level asynchronously. When the rising
Copyright 2010 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2011; 39:783790 DOI: 10.1002/cta

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RFI

VGA

Trigger receiver Gain control

Demodulator

RXD

PLL Receiver

CLK

RFO

Pulse generator Transmitter

TXD

Figure 3. Block diagram of UWB transceiver.

TXD clk RFOn CL Vctrl gated clk RFOp

Figure 4. Schematic of pulse generator.

U Vbm D Vbl + CMP + Vbh CMP

CP vga +

opl in Vbn

out ip

rfip

oph

rfin

VGA

CMP
Vbh Vbm vga Vbl D Vbcn Vbn Vbn in ip vga

Vbcp

out

CP
oph opl

bias
psyn
Q

VGA

0 L

SET

SET

CLR Q

CLR Q

clk3

clk3

pulse-detector

Figure 5. Schematic of the VGA and trigger receiver.

edge of clk3 arrives, this register will be synchronously reset, and at the same time data propagate to the second register, realizing the synchronous receiving of asynchronous data, enabling the operation of the following digital process parts.
Copyright 2010 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2011; 39:783790 DOI: 10.1002/cta

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clk
0

Vbcp
D
Q

vco
0

Vbcn
Q

Vbcn

PFD CP

VC O

clk1

clk3

3-divider

Figure 6. Schematic of PLL.

3.3. Phase-lock-loop PLL uses baseband clock clk to generate triple frequency clock clk3 as the main working clock for the receiver. PLL is comprised of 3-divider, phase frequency detector (PFD), current pump (CP), and voltage-controlled ring oscillator comprised of current-starved inverter chain [7]. The low-pass lter comprised of resistor and capacitance in series is put outside the chip, as shown in Figure 6. 3.4. Digital back-end of receiver In order to achieve ultra-low-power consumption of the transceiver, digital back-end of the system is also full-custom designed with low-complexity baseband algorithm, including gain control module and demodulator. The gain control module and the demodulator are pure digital circuit designed for baseband process. As shown in Figure 7, the gain control module generates the control signals U , D according to the occurrence probability of data Y = 1; targeting at the occurrence probability of 1 and 0 are both 50%. The demodulator corrects the phase-offset between the clock of transmitter and the receiver, and then obtains the nal data rxd.

4. EXPERIMENTAL RESULTS The UWB transceiver aiming at ultra-low-power short-range moderate speed communication is implemented in HJTC 0.18 m CMOS process. All the circuits are designed only by CMOS active devices, the absence of inductor and capacitor makes chip area as small as only 0.45 mm2 , including 20 pads. The die photograph is shown in Figure 8. The core block is mainly comprised of transmitter and receiver, whereas receiver can be divided into two parts: RF front-end and digital back-end (here we consider PLL as a part of the digital back-end). The experimental results show that the whole transceiver consumes 4 mW from 1.8 V supply at the data rate of 40 Mb/s whereas 12 mW at the data rate of 100 Mb/s. The measured PN sequence of UWB pulse at the load of 50 and the pulse details are shown in Figures 9 and 10, respectively. More tests show that the width of the pulse can be adjusted between 0.5 and 10 ns, the bandwidth is about 200 MHz4 GHz. With an off-chip lter or band-pass antenna, the spectrum can be compliant with the mask allowed for UWB communication, leading to additional cost. The receiver was tested with UWB pulses of peak voltage of 10 mV. The measured output of receiver corresponding to input data pattern is shown in Figure 11. The tested dynamic range of
Copyright 2010 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2011; 39:783790 DOI: 10.1002/cta

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Figure 7. Schematic of gain control module and demodulator.

Figure 8. Die photograph for pulse UWB transceiver.

the receiver is 30 dB. In Figure 12, the BER at 40 Mbps data rate is depicted, where the signal power is regulated by controllable attenuator. The measurement also shows that when BER is about 0.1%, the communication distance can be extended to 1 m at the data rate of 40 Mbps, which accords with Figure 12 generally. When the data rate declines, the communication distance can be even further. The comparison between the proposed transceiver and other works in [35, 8] are listed in Table I. It is obvious that the proposed UWB transceiver has lower bit-power dissipation per
Copyright 2010 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2011; 39:783790 DOI: 10.1002/cta

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Figure 9. Measured PN sequence of UWB pulses.

Figure 10. Transmitted pulse details.

Figure 11. Measured output at the receiver (data out is delayed).

unit voltage and smaller size, whereas the data speed is moderate, which makes it suitable for short-distance low-power wireless applications.

5. CONCLUSION In this paper a novel low-power UWB transceiver for short-range communication based on the trigger receiving algorithm are presented. The proposed transceiver with a size of only 0.45 mm2 is full-custom designed in 0.18 m CMOS process, and implemented only by CMOS active devices.
Copyright 2010 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2011; 39:783790 DOI: 10.1002/cta

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0.1

BER

0.01

1E-3 0 5 10 15 20 25

Eb/n0

Figure 12. Average BER at 40 Mbps. Table I. Comparison among UWB transceivers.
UWB transceiver This work [3] [4] [5] [8]

Process ( m) 0.18 0.18 0.09 0.18 0.18 1.8 1.8 0.65 1.8 1.5 Power supply (V D D ) (V) Data rate (Rb ) 100 Mb/s 1 Gb/s 16.7 Mb/s 62.4 Mb/s 8 Mb/s Power consumption (P) (mW) 12 385 38 728 2.6 2 144 pJ/V2 Bit-power dissipation per unit voltage (E d /VDD ) 37 pJ/V2 120 pJ/V2 5.4 nJ/V2 3.6 nJ/V2 Chip area (mm2 ) 0.45 5 2.2 4.5 3.1 (active area)

The overall power consumption of the transceiver is 12 mW from a 1.8 V supply at the data rate of 100 Mb/s, making it a good choice for short-range low-power communication.
REFERENCES 1. Fontana RJ. Recent system applications of short-pulse ultra-wideband (UWB) technology. IEEE Transactions on Microwave Theory and Techniques 2004; 52(9):20872104. 2. Kaukovuori J, Kaltiokallio M, Ryynanen J. Analysis and design of common-gate low-noise amplier for wideband applications. International Journal of Circuit Theory and Applications 2009; 37(2):257281. 3. Iida S, Tanaka K, Suzuki H, Yoshikawa N, Shoji N, Grifths B et al. A 3.1 to 5 GHz CMOS DSSS UWB transceiver for WPANs. IEEE ISSCC, 2005; 214216. 4. Lee FS, Chandrakasan AP. A 2.5nJ/b 0.65V 3-to-5 GHz subbanded UWB receiver in 90 nm CMOS. IEEE ISSCC, San Francisco, CA, 2007; 116118. 5. Zheng Y, Annamalai Arasu M, Wong K-W. A 0.18 m CMOS 802.15.4a UWB transceiver for communication and localization. IEEE ISSCC, San Francisco, CA, 2008; 118120. 6. IEEE 802.15.4a Task Group, 2007. Available from: http://www. ieee802.org/15/pub/TG4a.html. 7. Lynch MW, Demirdag C, Belabbes N, Carnevali S, Lacy C, Yu M et al. 3.14.7 GHz WiMedia UWB RF/analog front-end in 130 nm CMOS. IEEE RFIC, Honolulu, Hawaii, 2007; 207210. 8. Anis M, Tielert R. Low power UWB pulse radio transceiver frontend. ESSCIRC, Munich, 2007; 131134.

Copyright

2010 John Wiley & Sons, Ltd.

Int. J. Circ. Theor. Appl. 2011; 39:783790 DOI: 10.1002/cta