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Presented By M.BHUVANESWARI
CMOS Technology depends on using both N-Type and P-Type devices on the same chip. The two main technologies to do this task are: P-Well (Will discuss the process steps involved with this technology)
The substrate is N-Type. The N-Channel device is built into a P-Type well within the parent N-Type substrate. The P-channel device is built directly on the substrate.
N-Well
The substrate is P-Type. The N-channel device is built directly on the substrate, while the Pchannel device is built into a N-type well within the parent P-Type substrate.
Twin Tub
Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate.
P-well on N-substrate
Steps : N-type substrate Oxidation, and mask (MASK 1) to create P-well (4-5m deep) P-well doping
P-well acts as substrate for nMOS devices. The two areas are electrically isolated using thick field oxide (and often isolation implants [not shown here])
SiO2
P-well
N-type substrate
P+ implant/diffusion
P+ mask
N+ implant/diffusion N+ mask
P+ N-type substrate
N+
Vout
Vss
P
P+
P channel Device
N+
N channel Device
N-type substrate
Vin
Vout
Vss
N+
N channel Device
P+
N-well
P channel Device
P-type substrate
MOS Transistor
0 Volts S (Source) 0 Volts G (Gate)
Channel length
Substrate
MOS Transistor
0 Volts S (Source) n-Channel Transistor: ON - D -to-S Current V D D Volts G (Gate) V D D Volts D (D rain)
Channel length
Substrate
X:
S Symbol
X:X
Simplifed Switch M odel
Switch M odel:
D Symbol
X:
X:X
Simplified Switch M odel
Switch M odel
X A ND Y
Y: Y
Series
Parallel
X: X Y: Y X OR Y
Parallel
X1 X2
Xn
X : X Y: Y Z: Z
The function for this circuit is:
CMOS Inverter
A 0 1 Y
VDD A Y
GND
CMOS Inverter
A 0 1 Y
VDD OFF
A=1 Y=0
ON
A Y
GND
CMOS Inverter
A 0 1 Y 1 0
A=0
VDD ON
Y=1
OFF
A Y
GND
Y A B
ON A=0 B=0
ON Y=1 OFF ON
ON A=1 B=0
OFF Y=0 ON ON
A B Y
Inverter Cross-section
Typically use p-type substrate for nMOS transistor
Requires n-well for body of pMOS transistors A GNDSeveral alternatives: SOI, twin-tub, etc. V Y
DD
SiO2 n+ diffusion
n+
n+ p substrate
p+ n well
p+
nMOS transistor
pMOS transistor
VDD
Polysilicon
n+ Diffusion
p+ Diffusion
Contact
Metal
Start with blank wafer Build inverter from the bottom up First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2
p substrate
Fabrication Steps
Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer Softens where exposed to light
Photoresist SiO2
p substrate
Lithography
Expose photoresist through n-well mask Strip off exposed photoresist
Photoresist SiO2
p substrate
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Photoresist SiO2
p substrate
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
SiO2
p substrate
n-well
n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions n well Ions blocked by SiO2, only enter exposed Si
SiO2
Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps
n well p substrate
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and nwell contact
n well p substrate
N-diffusion
Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing
n+ Diffusion
n well p substrate
N-diffusion
Historically dopants were diffused Usually ion implantation today But regions are still called diffusion
n+
n+ n well p substrate
n+
N-diffusion
Strip off oxide to complete patterning step
n+
n+ n well p substrate
n+
P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+ p substrate
p+ n well
p+
n+
Contacts
Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed
Contact
Metallization
Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
Metal
Processing Steps:
Substrate Selection
Anisotropic etch:
Etch polysilicon:
P-Implantation:
Grow phosphorus glass Etch glass to form contact cut Evaporating Alumini
SILICON ON INSULATOR
What is SOI? Characteristics of SOI Fabrication methods Basic categorization Electrical anomalies Advantages and Disadvantages
7/12/2011
What is SOI?
-SOI Silicon-onInsulator
-Si layer on top of an insulator layer to build active devices and circuits. -The insulator layer is usually made of SiO2
7/12/2011
Characteristics
Include: - High speed - Low power - High device density - Easier device isolation structure
7/12/2011 UNIVERSITY OF CALIFORNIA, IRVINE
7/12/2011
Categorization
-Categorization based on the thickness of the silicon film. -The first is a partially-depleted device and the latter is a fullydepleted device.
-Each has its own advantages and disadvantages.
Electrical anomalies
Floating-body effect: -Usually seen in PartiallyDepleted devices. - As shown in figure, the MOS structure is accompanied by a parasitic bipolar device in parallel.
-The base of this device is floating.
7/12/2011
Electrical anomalies
Kink Effect: -Sudden discontinuity in drain current. -Seen when the device is biased in the saturation region. -The bipolar device is turned on. Solution: -Provide a body contact for the device. - Use FD devices.
7/12/2011
Electrical anomalies
Self-heating effect: Thermal insulation is provided by the oxide surface. Heat dissipation is not efficient. This happens only when there is logic switching in the device.
In fully-depleted devices, the threshold voltage is sensitive to the thickness of the silicon film. Manufacturing process is comparatively difficult.
7/12/2011
Advantages of SOI
Suitable for high-energy radiation environments.
Parasitic capacitances of SOI devices are much smaller.
No latch-up.
7/12/2011
Advantages
Easier device isolation
-
7/12/2011
Disadvantages
Major bottleneck is high manufacturing costs of the wafer. Floating-body effects impede extensive usage of SOI. Device integration dopant reaction with the oxide surface. Electrical differences between and SOI nad bulk devices.
7/12/2011 UNIVERSITY OF CALIFORNIA, IRVINE
Conclusion
Due to its characteristics, SOI is fast becoming a standard in IC fabrication.
Several companies have taken up SOI manufacturing.
Interconnect
(i).Metal Interconnect Polysilicon & diffusion (N+,P+)
(ii).Poly Interconnect:
(iii).Local Interconnect:
Circuit Elements:
Latchup problem:
Latchup : Shorting of VDD and Vss lines Chip breakdown Latchup Equivalent Circuit: Vertical : pnp p = source/drain of p device (Emitter) n = n-well (Base) p = p-substrate (Collector)
Lateral : npn n = source/drain of n device (Emitter) p= p-substrate (Base) n= n-well (Collector) Rsubstrate, Rwell Parasitic devices and resistors
Latch up Problem:
Equivalent Circuits:
Characteristics curve:
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