3D IC-Si Integrations (ECTC2010)

State-of-the-art and Trends in 3D Integration
John H. Lau Electronics & Optoelectronics Laboratory (EOL) Industrial Technology Research Institute (ITRI) johnlau@itri.org.tw 886-3591-3390
Lau
Objective of This Lecture

TSV for 3D integration is a more than 26-year-old technology. Even the coplanar GaAs RF MMIC (monolithic microwave integrated circuit) used via hole grounding technology in 1975 (35 years ago), but it was not for 3D integration. In this lecture, the focus is on:
TSV (with a new concept that every chip could have two active surfaces)
Memory CPU Organic Substrate Solder micro bumps TSV Ordinary solder bumps Memory UBM pad CPU
GaAs
Via hole for grounding Vertical Interconnect (TSV) (1975) YOlCHl AKASAKA, Three-Dimensional IC Trends ,
PROCEEDINGS OF THE IEEE, VOL. 74, NO. 12, DECEMBER 1986, page 1703.
Organic Substrate
Lau, IEEE/ECTC09 PDC
Lau
Contents
(1) Introduction to 3D IC/Si Integrations (2) Through Silicon Via (TSV) with RDL Technology (3) Low-Cost Microbumps for 3D IC Integration (4) Thin-Wafer Handling for 3D IC Integration (5) CMOS Image Sensor with TSV (6) 3D MEMS and IC Integration (7) 3D LED and IC Integration (8) Hybrid (Opto-Electronic) 3D IC Integration (9) Summary and Q&A
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Lau Lau, 3D IC Integration PDC
Electronics Industry
1.The Electronics Industry has been the largest industry since 1996. 2.It would be a 1.5 trillion dollars (i.e., $1012) by 2010. 3.It is the most dynamic, fascinating, and important areas of research, design, material, process, manufacturing, assembly, tests and inspections, quality, reliability, workmanship, etc.
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Key Inventions and Driver for the Electronic Industry

The invention of the bipolar junction transistor and the junction field-effect transistor by Bardeen, Brattain, and Shockley in 1956 foreshadowed the development of generations of smart phones and computers yet to come. The invention of the silicon integrated circuit (IC) by Jack Kilby of Texas Instruments in 1958 and 6 months later by Robert Noyce of Fairchild Semiconductor excited the development of generations of integrations. The proposal of doubling the number of transistors on an IC every 24 months by Gordon Moore in 1965 (also called Moore law) has been s the most powerful driver for the development of the microelectronic industry in the past 44 years.
Lau
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Lau, 3D IC Integration PDC
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Lau
2D vs. 3D Examples
MEMS ASIC
Seal Ring
Analog DevicesMEMS (accelerometer) integrated into an ASIC (SoC) 2D
MEMS chip attached to an ASIC chip (3D IC integration) [Prem and Lau, ECTC2008]
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Lau Lau, Lee, Prem, Yu, 3D MEMS Packaging, McGraw-Hill
IC Electronics Products Food Chains

IC Design/Layout and Analysis IC FAB and Test
Substrate Layout Substrate FAB & Test
IC Packaging Design and Analysis IC Packaging Assembly and Test PCB Assembly NG
PCB Layout PCB FAB & Test
Rework Very Unlikely
PCB Test System Test of PCBs in Chassis Ship
Unlikely NG Rework
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Lau
Conventional Packaging Technologies

Plastic Quad Flat Pack (PQFP)
DIE
Plastic Ball Grid Array (PBGA)
Flip Chip Plastic Ball Grid Array (FC-PBGA)
Wire Bonding Chips on Board
Printed Circuit Board

Chip Scale Package (CSP) Wafer Level Chip Scale Package (WLCSP) Direct Chip Attach (DCA) and PoP Package-onPackage (PoP)
Printed Circuit Board
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Advanced Packaging
Given wafers from Semiconductor FAB Packaging People: (1) Make through-silicon vias (TSV) on the chips with redistribution layers (RDL) in wafers (2) Thin wafer handling (3) Make under bump metallurgy (UBM) on the chips in wafers (4) Make low-cost solder microbumps (Wafer Bumping) on the chips in wafers
Lau
All these need to be done on wafers in a FAB the backend of a Semiconductor FAB 10
Lau, Lee, Prem, Yu, 3D MEMS Packaging, McGraw-Hill
Vias in a Chip
There are at least two different vias on a chip. One is very tiny ( 0.1m today) and the other is very large ( 5m today). The tiny ones are connected to devices such as transistors (4 tiny vias for each transistor) to build the first metal layer. Today, the number of these tiny vias, for many chips, already exceeds the world population of over 7 billion. On the other hand, for the large vias that we call TSV for 3D IC integration, the number is much less ( 100,000 today) and the size is larger (a 5m TSV is shown in the figure to show their contrast).
Many tiny vias filled with Cu or W right on top of the devices, e.g., transistor
TSV (5m)
This is a toscale schematic of a 3D IC integration TSV (~5m).
65nm Cu/low-k Chip by GlobalFoundries (2006) to show the tiny vias. A 3D IC integration TSV is drawn to show their contrast
Lau
TSV Via-middle approach Lau, CSR, Apr, 2010.
Some Terminologies (Packaging view) s

FEOL (Front End of Line) is usually performed in Wafer FABs and the process is from a Bare Wafer to Passivation. BEOL (Back End of Line) is usually performed in Packaging & Test Houses and it involves everything after Passivation, e.g., wirebonding, metallization, UBM, wafer bumping, backgranding, and dicing. MEOL (Mid-End of Line) is usually performed by integrating the FEOL and BEOL technologies into a 3D IC/Si integration which involves, e.g., TSV, microbumps, thin-wafer handling, wirebonding, metallization, UBM, wafer bumping, backgranding, and dicing.
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Some Terminologies (Semiconductor)

FEOL (Front End of Line) FEOL is defined as the first portion of IC fabrication where the individual devices such as the transistors and resistors are patterned. This process is from a bare wafer to (but not including) the deposition of metal layers. BEOL (Back End of Line) BEOL is defined as fabrication which the active devices are interconnected with wiring on the wafer. This process starts from the first layer of metal to bonding pads with passivation. It also includes contacts, insulator, and dicing the wafer into individual IC chips.
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3D Integration Technologies
3D IC Packaging 3D IC Integration 3D Si Integration
Full swing production for memories.
Mass Production
Commercialization
Die Stacking with wire bonds
Testing and yield challenges give way for package stacking
Maturity
Applied R&D Basic R&D
Package on Package Stacking (PoP)
Active applied R&D is undertaken by Research Institutes. System level challenges are key. In the phase of industrialization.
Still in upstream research, technological challenges such as yield & device architecture are key issues.
C2C, C2W, W2W Stacking W2W Stacking
Technology
Lau Lau, Lee, Prem, Yu, 3D MEMS Packaging, McGraw-Hill, 2009
Conventional 3D IC Stacking
Akita Elpida 20 Stacked chips s
Flesh memory in volume production!
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Conventional Package-on-Package (PoP)

100s 100s
2 chips with wire bonds
100s
1000s
100s
100s
1 wirebond chip and 1 flip chip face-to-face (F2F)
2 chips with wire bonds and with 1 flip chip on top

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3D Integration Roadmap
3D Packaging (No TSV)
3D Stacking (wirebonds) CMOS image sensor with TSV (PCB Technology) PoP Passive TSV interposer to support highperformance chips
3D IC Integration
C2C/C2W/W2W; microbump bonding; 5 TSV 30m; 20 memory stack 50m; 100 interposers 200m
3D Si Integration
W2W pad-pad bonding (1m TSV 2m)
Cu-Cu bonding
Memory (50m) with TSV and microbump
Mass Production
32 memory (20m) stacked CMOS image sensor with DSP and TSV Active TSV Interposer (e.g., Memory on Logic with TSVs)
Bumpless
SiO2 bonding
Low Volume Production Mass Production

Lau
3D MEMS; 3D LED
Bumpless
2012 2015-17 Don care t to guess!
2008 2011-13
2010 2013-15
Low volume production = only a handful of companies are SHIPPING it; Mass production = many companies17 SHIPPING it. are
Moore Law vs. More-Than-Moore s

Moore Law s
2D SoC
A PROCESSOR, ASIC, MCU, etc. DSP B DISPLAY TSV
More than Moore

3D IC Integration
Thin Chip
3D Si Integration
Thin Chips
MEMORY DISPLAY OPTO B DSP

MEMS
Long Wiring (from A to B) in 2D SoC MEMORY OPTO
For both cases, Thermal Management is a big issue!
TSV
MEMS
Micro Bumps
Wafer-to-wafer bonding Very short wiring in 3D Si integration with very tiny TSVs, thin wafers/chips, and bumpless (no bumps!) Thermal management is a huge problem 18
PROCESSOR. A ASIC, MCU, etc.
Short Wiring (from A to B) in 3D IC Integration with TSVs, thin chips, and microbumps,
Lau
Samsung 3D Stacking with s TSV (Through Silicon Via)

50m thick Chip TSV 16Gb memory (8 x 2Gb) 560m Laser drilled via
Micro bump
Wafer before back-grinding
8-stack chips (50m each) connected with TSV and microbumps
720m
560m
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Samsung 8 Gb DDR3 DRAM is Stacking with s TSV Chips and Microbumps

Chip TSV Micro Bump TSV Area
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Samsung 32-Memory Stacking s
32 memory chips each with 20m thick

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Intel Copper Via Plating in 3D s Interconnects
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Lau
Hitachi 3D Stacked with TSV s
Key features: smaller via diameter (30m); on-wall plated via; and thinner package structure; and room temperature bonding.
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Lau
3D IC Integration
3D Si Integration
Cu-Cu bonding
Mass Production
Bumpless
SiO2 bonding

Lau
3D MEMS; 3D LED
Bumpless
2008 2011-13
2010 2013-15
Low volume production = only a handful of companies are SHIPPING it; Mass production = many companies24 SHIPPING it. are
IBM Generic 3D Technology Roadmap s for High-Performance Computing Systems
TSV for Interposer
TSV for 3D chip stacking
Andry, et.al, Fabrication and Characterization of Robust Through-Silicon Vias for Silicon-Carrier Applications , 25 IBM J. RES. & DEV., Vol. 52, No. 6, November 2008. Lau
Intel Proposed Roadmap of Package Architecture s Transitions to Address the Memory Bandwidth Challenge
Si chip Solder micro bumps Ordinary solder bumps TSV UBM pad Si carrier
3D Stacked Die MCP
Organic Substrate
Substrate Embedded Die MCP

2D Planar MCP
Off-Pkg
Lau
Polka, et.al., Package Technology to Address the Memory Bandwidth Challenge for Tera-scale 26 Computing Intel Technology Journal, Vol. 1, Issue 3, August 2007 ,
3D IC Integration Memory on Active Interposer (CPU)

Memory Organic Substrate CPU
Memory Solder micro bumps TSV Ordinary solder bumps

Lau
UBM pad CPU
Organic Substrate
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TSV: The Smaller the Better

In real applications, the space on the chip to make TSVs is very limited!
Si chip, e.g., Memory Solder micro bumps TSV
25m
UBM pad Active Interposer, e.g., Logic
Not to scale!
Ordinary solder bumps
Memory
The area for > 2500 TSVs
Logic
Lau
Don expect the TSVs are evenly distributed on t 28 the chip!

TSV Applications in 3D Packaging

Solder Microbump Ordinary Solder Bumps High performance chip Underfills TSV interposer Underfills Not to Scale Solder Microbump TSV Memories Underfill
BT Substrate
BT substrate
PCB
Solder Joints
IME US 6846752B2 s Wafer-Level Package for Micro-Electro-Mechanical System (MEMS)
DuPont TSV Image Sensor s
Cap/ASIC
TSV
MEMS
PCB
Lau
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TSV Applications in 3D IC Integrations
Renesas use a TSV interposer to redistribute interconnects in stacked chips

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TSV Interposers (Carriers)
Lau
Ranganathan, et.al, Integration of High Aspect Ratio Tapered Silicon Via for Through-Silicon 31 Interconnection IEEE/ECTC 2008 Proceedings, pp. 859-865. , Lau, 3D IC Integration PDC
3D Packaging vs. 3D IC Integration

The biggest difference between the 3D IC integration and 3D packaging is that 3D IC integration utilizes the TSV to connect chips in the vertical direction while the 3D packaging doesn t. The advantages of the 3D IC integration over the 3D packaging are: (1) less footprint, (2) smaller form-factor, (3) less weight, (4) higher performance, (5) less power, and (6) potentially lower cost The challenges (opportunities) facing the 3D IC integration, among others are: (1) high-yield TSV with RDL fabrication, (2) thin chip and wafer strengthening and handling, (3) microbumps, (4) thermal management, (5) inspection and testing, (6) cost reductions (7) reliability. Of course, designs & characterizations are always important. 32
3D Integration Technologies
3D IC Packaging 3D IC Integration 3D Si Integration
Full swing production for memories.
Mass Production
Commercialization
Die Stacking with wire bonds
Testing and yield challenges give way for package stacking
Maturity
Applied R&D Basic R&D
Package on Package Stacking (PoP)
Active applied R&D is undertaken by Research Institutes. System level challenges are key. In the phase of industrialization.
Still in upstream research, technological challenges such as yield & device architecture are key issues.
C2C, C2W, W2W Stacking W2W Stacking
Technology
Lau Lau, Lee, Prem, Yu, 3D MEMS Packaging, McGraw-Hill, 2009
Moore Law vs. Moore-Than-Moore s

Moore Law s
2D SoC
More than Moore

3D IC Integration
Thin Chip
3D Si Integration
Thin Chips

MEMS
TSV
MEMS
Micro Bumps
Wafer-to-wafer bonding (Bumpless) Very short wiring in 3D Si integration with very tiny TSVs, thin wafers/chips, and bumpless (no bumps!) Thermal management is a huge problem
Lau, 3D MEMS, IMAPS09
Lau
3D Si Integration
3D Si integration is one of the more-than-Moore and is a very old idea, which consists of two or more layers of active electronic components that are integrated vertically into a single circuit. It was trigged by the advance of the silicon-on-insulator (SOI) technology first reported by Gat and his colleagues more than 30 years ago, when people thought Moore law could be hitting s the wall by the 1990s. (Of course, the fact showed that it didn t.)
Vertical Interconnect (We called TSV today)
YOlCHl AKASAKA, Three-Dimensional IC Trends PROCEEDINGS OF THE IEEE, VOL. 74, NO. , 12, DECEMBER 1986, page 1703. 35
IBM 3D Si Integration (Cu-to-Cu W2W) s

(a) Two device layers bonded in a faceto-face approach (b) Two device layers bonded using face-to-back approach
(a) a bonded wafer processed with not-optimized Cu-bonding process, with some areas that did not survive dicing test (b) A well-bonded wafer processed with fully optimized Cubonding technique
Lau
A 4-m Cu interconnect bonded to Cu pad showing a high quality Cu-to-Cu bonding interface
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MIT 3D Si Integration s
MIT Assembly Process for a s 3D Si integration: 1. Two completed circuit wafers are planarized, aligned, and bonded face to face. 2. The handle silicon is removed. 3. 3-D vias are etched through the deposited buried oxide (BOX) and the field oxides. 4. Tungsten plugs are formed to connect circuits in both tiers. 5. After tier 3 is transferred, bond pads are etched through the BOX for testing and packaging.
Lau
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MIT 3D Si Integration (SiO2 to SiO2) s W2W bonding
The tiers are bonded and interconnected with tungsten plugs; the conventional interlevel connections are seen in tiers 2 and 3, which are FDSOI tiers. Note that the 3-D vias are located in the isolation (field) region between transistors
Lau
The metal pattern of tier 3 is viewed through the BOX. Tiers 2 and 1 are visible at the edge of the wafer where the tiers did not bond because of nonplanar surfaces
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Solder Microbump vs. Pad-to-Pad (Bumpless)

Solder Microbump Bonding Method Bonding Temperature Bump size Pitch Surface Requirement
Thermal compression < 350C ~ 8m ~ 15m Surface pre-treatment easy
Pad-to-pad (Bumpless)
Metal fusion bonding > 350C (Room temperature bonding is far in the future) < 5m < 10m Very High Surface pretreatment to remove oxidation is very complicated. Also, surface roughness requirement is <1.0nm RMS 3D Si integration High
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Bonding Pressure Medium
Applications Cost
Lau
3D IC integration Low
3D IC Integration vs. 3D Si Integration

The biggest difference between the 3D IC integration and 3D Si integration is that 3D Si integration doesn not use bumps such as solder, gold, or t conductive adhesive to bond/connect two wafers together, i.e., bumpless. It should be emphasized that there is no (or infinitesimal) gap between wafers and the thermal management could be a very big problem. Also, W2W is the only way to perform the bonding operation. Thus, unlike 3D IC integration which utilizes C2C, C2W, or W2W bonding methods, the yield is a big issue (e.g., some bad chips are forced to bond on the good chips). Furthermore, the TSV size for 3D Si integration is much smaller (ranging from 1 to 5m and eventually will be in sub-micro scales), and thus its TSV manufacturing yield lost is higher. Finally, the requirements of the bonding conditions such as the surface cleanness, surface flatness, and the class of cleanroom (which are heavily affecting the yield) for 3D Si integration are much tougher than those for 3D 40 IC integration.
Lau
3D IC Integration vs. 3D Si Integration

The advantages of 3D Si integration over the 3D IC integration are: (1)better electrical performance, (2)less power, (3)lower profile, (4)less weight, (5)potentially lower cost. Basically there are two different W2W bonding methods for 3D Si integration, namely Cu-to-Cu bonding and oxide-to-oxide bonding . Again, the thermal management of 3D Si integration is much tougher than that of 3D IC integration.
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MEOL (Mid-End of Line) 3D IC Integration

The key technology for electronic products which require: Form Factor Smaller is Better, e.g., cameras, PDAs, Mobiles (COMS image sensors) Performance Faster is Better, e.g., shorten global interconnect lengths. Cost Cheaper is Better, e.g., system improvements without the high-cost of scaling. Reliability Low-risk is Better, e.g., it still works after drops.
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3D Integration Laboratory in the World

(1) IMEC TSV and 3D IC Integration programs located at Belgium, funded by s EU government and companies, 2006. (2) Leti TSV and 3D Integration programs located at Grenoble, funded by EU s companies and government, 2006. (3) IME TSV Interposer and 3D Chip Stacking consortium, funded by 21 s companies, June 2007. (4)DAVID (Downscaled Assembly of Vertically Interconnected Devices) project funded by the Commission of the European Communities, September 2007. (5) Taiwan 3D IC Consortium (Ad-STAC: Advanced Stacked-System s Technology and Application) hosted by ITRI, supported by government, July 2008. (6) SEMATECH's 3D Interconnect Program located at the University at Albany, New York, March 2009 (7) Fraunhofer All Silicon System Integration Dresden ASSID located at s Berlin and Munich in Germany (49M for the first phase), January 2010.
Lau
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3D Stacking (wirebonds) CMOS image sensor with TSV (PCB technology) PoP Passive TSV interposer to support highperformance chips
3D IC Integration
3D Si Integration
Cu-Cu bonding
Mass Production
Bumpless
SiO2 bonding

Lau
3D MEMS; 3D LED
Bumpless
2008 2011-13
2010 2013-15
2012 2015-17
Don care t to guess!
Low volume production = only a handful of companies are SHIPPING it; Mass production = many companies are SHIPPING it.
Potential Real Applications of TSV with RDL

The preferred via size is 30m. (For tapered via, its the larger dimension.) Eventually, it will go down to 5m. Most of the people use straight vias. The preferred depth of the thickness for memory stacking is 50m for now, but it will go down to 20m. The preferred depth of the thickness for active/passive interposer is ranging from 100 to 200m.
The via size should be as small as possible. Why?

1) Less thermal expansion mismatch between the Si (2,5x10-6/oC) and Cu (17.5x10-6/oC) 2) Lower cost (less Cu to be plated) 3) Higher throughput 4) More space for routing
Lau
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Key TSV Processes

1. Via formation by either deep reactive ion etch (DRIE) or laser drilling 2. SiO2 deposition by either thermal oxidation for passive interposers or PECVD (plasma enhanced chemical vapor deposition) 3. Barrier and seed layer deposition by physical vapor deposition (PVD) or electrografting (eG) 4. Cu plating or W (tungsten) sputtering to fill the vias 5. CMP (chemical and mechanical polishing) of Cu plating residues (overburden)
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Bosch DRIE Process

Fluoroionbased etching step Passivation step
Under cut
Scalloped sidewall
Lau
The process cycles between an etch stepusing SF6 gas and a polymer deposition step using C4F8. The polymer protects the sidewalls from etching by the reactive fluorine radicals 47
TSV/MEMS by Deep Reactive Ion Etch (DRIE)

Invented by Bosch and STS (Surface Technology System) sell the equipments. The scheme is time-multiplexing:many alternating passivation and etching cycles
GAS FLOW RATE SF6 C4F8 TIME
ETCH PASSIVATE ETCH
Shallow, isotropic trench
Silicon Silicon Protective fluorocarbon film Photoresist or SiO2

Lau
Room temperature process. Photoresist or silicon dioxide as etch mask High aspect ratio up 30 High etch rate from 2 to 30 m/min (the cycle time for each 48 deposition or etch step is a few seconds) Lau, 3D IC Integration PDC
Results of TSV DRIE

W w
1.0 0.8
Rw
0.6 0.4 0.2 1.0 1.2 1.4 1.6 1.8
Passivation step, thin layer of polymer coated on the sidewall
Rt Relationship between Rt & Rw
1. Rt: etch cycling time/passivation cycling time; Rw: narrowest sidewall width w/original designed sidewall width W 2. The alternating of etching and passivating cycles forms scallops on the sidewall. The larger the Rt, the larger the scallop 3. The Si at the entrance of via is more easily isotropic etched, as the etch process going on, under-cut becomes larger and also the bow shape at the entrance
Lau Yu, Lau, et.al.
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Results of Plasma Deposited SiO2

Top Middle
Deposited oxide thickness: 1.9-2.0m on top side Sidewall oxide thickness at top sidewall is 1.3-1.4m Sidewall thickness in middle is 0.7-0.8m Thickness of oxide on the via-base is 0.35-0.45m
Lau Ranganathan, et.al, IEEE/ECTC 2008 Proceedings, pp. 859-865.
Bottom
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Dielectric Isolation by Wet Thermal Oxidation

Top Top Middle
Middle
Bottom
Bottom of via Bottom
Lau
100% conformal growth of 1m SiO2 in top middle and bottom of the via within 5% variation (>1000oC) Sidewall roughness decreases from 200-250nm to <100 nm due to 51 silicon consumption in wet oxidation
Ranganathan, et.al, IEEE/ECTC 2008 Proceedings, pp. 859-865.
Seed Layer by PVD - Tango
Lau
The Ti barrier/adhesion layer and Cu seed layer were deposited in 52 Tango Systems Axcela PVD (Physical Vapor Deposition) chamber.
TSV Seed Layer by Alchimer's Electrografting (eG)

Wet deposition of the insulation and barrier layers inside highaspect-ratio TSV have been achieved by Electrografting (eG), which transients chemical bond initiated by small electric current followedjust a dumb wire, and one cannot be paying $400 a wafer to create them. A TSV is by electroless chemical propagation. This is to replace dry vapor deposition with less expensive wet processing using low-cost electroplating tools.
Seed Layer: Ti (100nm) Cu (1m) Alchimer's eG ViaCoat tackles the challenge of conformal copper seed layers in deep TSVs. Vias with a high aspect ratio are needed to reduce TSV costs
53
Alchimer TSV Seed Layer by (eG) s
Jagged edges on deep TSVs require a conformal seed layer. Alchimer ViaCoatapproach s eG for insulation, barrier and seed deposition in deep TSVs.
Lau
54
Solid Via Filling by Pulse-Reverse (Damascene) Plating Process

I, A
1 2 22 32 54
Cu Deposition (Plating)
t, ms
-3
Etch-Back (Dissolve Cu)
Lau 55 Ranganathan, et.al, Integration of High Aspect Ratio Tapered Silicon Via for Through-Silicon Interconnection IEEE/ECTC ,
Void-Free!
Cu Via Filling by Damascene Process

Multi-step pulse reverse plating technology
56 Lau Ranganathan, et.al, Integration of High Aspect Ratio Tapered Silicon Via for Through-Silicon Interconnection IEEE/ECTC ,
Established void free Through Silicon Via plating process
Damascene Plating of TSV

95-100m
40-50m
Plating results: Void-free filling Overburden: ~30m
Via geometry: Tapered (~85) Depth: ~200m Mean Dia:~80m
Ranganathan, et.al, Integration of High Aspect Ratio Tapered Silicon Via for Through-Silicon Interconnection , 57 IEEE/ECTC Proceedings, pp. 859-865. Lau
Copper polish & Via exposure

Over burden copper is removed by chemical mechanical polishing (CMP) Back-grind + Polishing to 200m thickness by using temporary handle wafer process
Process Conditions Spindle Speed C.T Speed Cutting depth Feed rates Mesh Sizes Rough Grind 3200 rpm 250 rpm 400 micron 100um/mins 325 # Via exposure 2800 rpm 150 rpm 100 micron 20um/mins 600 #
200m
Ranganathan, et.al, Integration of High Aspect Ratio Tapered Silicon Via for Through-Silicon Interconnection , 58 IEEE/ECTC Proceedings, pp. 859-865. Lau
How to Improve the TSV Manufacturing Yield: Via Forming by DRIE

What we want: 1.Sidewall roughness: as smooth as possible. 2.Via straightness: vertical or slightly taped are preferred. 3.Via uniformity: < 5% variations across the whole wafer. 4.Via forming speed: reasonable. What we should do: 1.The etch rate (Rt) = etch cycle time/passivation cycle time (Figure 6) should be balanced. (SF6 will be used in etch cycle whereas C4F8 in passivation cycle.) If etch cycle time is too long and passivation cycle time is too short, then the via will not be straight and sidewall will be rough. If etch cycle time is too short and passivation cycle time is too long, then the etch rate will be slow. Rt = 7s/5s is a good starting point. 2.The most common mask processes are photoresist and photoresist+SiO2. Photoresist is simple, but undercut could be larger. Photoresist+SiO2 is better, but it needs more process steps. 3. Higher etch power will increase etch rate. However, if etch power is too high, mask layer will be etched away. 59
Lau Lau, IEEE/ECTC2010
How to Improve the TSV Manufacturing Yield:

Dielectric Deposition by Thermal Oxidation and PECVD
What we want: 1.Conformity: the via sidewall (from top to bottom) is covered by SiO2 (>1m). 2.Adhesion: the adhesion between Si and SiO2 is good. 3.Uniformity: < 5% variations across the whole wafer. 4.Sidewall roughness: < 100nm. What we should do: 1.Thermal oxidation can achieve very uniform isolation layer, but its operating temperature is very high (~1000oC) and thus it is suitable for via-first process. 2.PECVD (plasma enhanced chemical vapor deposition) of SiO2 is operated at a temperature between 250 - 400oC and is not easy to cover the sidewall of high aspect ratio vias uniformly. Gas flow (SiH4, N2O or Si(OC2H5)4) need to be controlled. In addition, lower temperatures ( 350oC) should be used because 400oC is too close to the allowable temperature of most IC devices.
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How to Improve the TSV Manufacturing Yield:Barrier/Adhesion/Seed Metal Layer by PVD and Electrografting
What we want: 1.Conformity: 100% sidewall coverage. 2.Dimensions: >100nm of Ti (for adhesion) and >1m of Cu (for seed metal layer). 3.Uniformity: < 5% variations across the whole wafer. What we should do: 1.Physical vapor deposition (PVD) sputtering power is important. Usually higher power can increase adhesion and better sidewall coverage 2.Before sputtering, pre-cleaning the wafer in the sputtering chamber (using Ar plasma to bomb the wafer surface) is important. 3.Wet deposition of the insulation and barrier layers inside high-aspectratio TSV can also be achieved by Electrografting (eG), which transients chemical bond initiated by small electric current followed by electroless chemical propagation. This could replace the dry vapor deposition with less expensive wet processing using low-cost electroplating tools.
61
How to Improve the TSV Manufacturing Yield:Via filling with Cu and W

What we want:
1.Uniformity: < 5% variation across the whole wafer 2.Void free: no voids in the Cu filling 3.Plating speed: reasonable 4.Overburden: < 20m of Cu on wafer surface
What we should do:

1.Plating current is the most important parameter. Smaller current (e.g., 0.1A) will help to achieve better via filling especially for high aspect ratio vias, but the plating speed is slower. 2.Plating solution additives/components (suppressor, leveler and accelerator) need to be controlled. The suppressors are typically polyalkylene glycol type polymers which are used to improve the morphology and profile of the via filling. The levelers are typically alkane surfactants containing sulfonic acids and amine or amide functionalities, which are also used to improve the morphology. The accelerators are typically sulfur derivatives of propane sulfonic acid which are used to brighten the plated Cu color, i.e., to prevent Cu from oxidation. 3.Beside plating current and chemistry, pre-treatment (wetting + DI rinsing + pre-absorbing accelerator) is also a key contributor to void-free filling. 4.Plating uniformity can also be improved by agitation of the solution and rotating the wafer during the plating. 5.Plating waveform such as the multistep pulse-reverse (damascene) plating process is recommended. 6.For 3D Si integration, since the via is very small (~1m) tungsten (W) is usually used and deposited by CVD (using WF6 and H2 as gas). Normally the flow rate and volume of WF6 and H2 need to be matched and temperature needs to be controlled at about 450oC. For 3D IC integration, since the via is much larger than that of 3D Si integration, if W is used, sputtering would do it. 62
How to Improve the TSV Manufacturing Yield:- CMP

What we want: 1.Uniformity: wafer total thickness variation (TTV) should be as small as possible (<5%). 2.Residual stress: no micro cracks on the wafer. What we should do: 1.Slurry flow rate and down force should be optimized to achieve high removal rate, better uniformity, and less stress. A 180cc/min slurry flow rate and a 330g/cm2 down pressure are good starting points. 2.The head (clockwise) speed should be 1 to 2 times the table (counterclockwise) speed. 3.To reduce the warpage (stress), 500 of SiN is deposited on the Cu, and then annealed at 200oC for 80 minutes under N2.
63
Large Chip Supported by a TSV Interposer
21x21mm Cu-low-k Chip

Overall Package Top Chip Body size Thickness Chip Size 65nm Technology I/O Pitch /Solderbumps Top-side with CuNiAu as UBM Chip size Tapered shape Top-side Bottom-side Thickness Via diameter Size/Metal layer Core thickness Pitch I/O and solder 45 x 45 mm 1.8 mm 21 x 21 mm Cu/low-k, 9-metal layer 11,000 150 m/SnAg Bottom-side with SnAgCu (300m pitch, 100m height) 25x25x0.3mm 100 m / 50 m 2-metal layer 1-metal layer 3 m 40 m 45x45x1mm (1-2-1) 800 m 1 mm 2000 SnAgCu balls
TSV Interposer
25x25mm TSV Interposer
TSV Cu RDL (Redistribution Layer) Organic Substrate
Lau
45x45mm BT-substrate
64
Zhang-Lau, et. al.
Models for Simulations of TSV

SiO2
Schematic of simplified TSV
(a)
2 H Cu D 1 Si u1 = 0 u2 0
(b) Quarter model of TSV with applied boundary conditions
Axi-symmetric about 2-axis Si
Cu
SiO2
Symmetry about 1-axis A B
Mesh of critical regions

25m, 50m, 75m 1, 2, 3, 5, 7, 10, 12 for D= 25 Aspect ratio m (H/D) 1, 2, 3, 5, 7 for D= 50 m 1, 2, 3, 5 for D= 75 m Lau Diameter (D)
(c)
D
Selvanayagam, Lau, et.al, ECTC08
65
Deformation of TSV at Critical Region Exaggerated 100X

(a)
A B
C 2 1
(b)
B A
2 1
Lau
Selvanayagam, Lau, et.al, ECTC08
66
Simulation Results of the TSV

(a)
290 2 70
Stress at Point A (Cu)
11 (MPa)
Radial stress (11) at critical corner for copper (Point A)
2 50 230 2 10 1.6 0 19 0 170 150 20 30 1.4 4 1.73
1.2 6
(b)
340 320
D ( ) m Stress at Point B (Si oxide)
40
50
60
70
80
300 2 50
Stress at Point A (Cu)

1.3 5
Radial stress (11) at critical corner for silicon dioxide (Point B)
11 (MPa)
300 280 260 240
200 150
1.71
11
1.53 1.8 3
10 0 50
220 20 0 30 40
20
40
H/ D =1 H/ D =2
D ( ) 6 0 m
50
60
70
80
80
H/ D =5
D
67
Selvanayagam, Lau, et.al, ECTC08 Lau
H/ D =3
Simulation Results of the TSV

(a)
3000 2 50 0
Stress at Point C (Cu)
Axial strain (22) at mid-plane for copper
2000
22 ()
150 0 10 0 0 50 0 0 0 2
(b)
Stress at Point H/D oxide) D (Si
10
12
3000 2 50 3 0 0 0 0
Stress at Point C (Si oxide )
150 0 10 0 0 10 0 0
50 0 0 0
22
Axial strain (22) at mid-plane for silicon dioxide
2 2 0 0 0 50 0
22 ()
2000 150 0
50 0 0 0
2 2 44 6 6
Selvanayagam, Lau, et.al, ECTC08 Lau
H/D
88
10 10
12 12 H/D
D = 2 5m
D = 50 m
D = 75m
68
Cracking of SiO2 Due the Thermal Expansion Mismatch in the Z-direction

SiO2 (a) 2 H Cu D 1 Si
SiO2
(b) Axi-symmetric about 2-axis u1 = 0 u2 0
Cu
Symmetry about 1-axis (c) A B
1 45
Selvanayagam & Lau, IEEE/ECTC08 Lau
This is due to the local thermal expansion mismatch between the Cu (17.5x10-6/oC) and Si (2.5x10-6/oC) in the Z-direction reported in May at IEEE/ECTC2008 by [Selvanayagam and Lau] and the mismatchCu pushes the silicon oxide to crack. This phenomenon copper pumpingshown in the figure above was reported in the fall of 2008 by Patti of Tezzaron (according to Philip Garrou, Contributing Editor of Semiconductor International 69 on December 3, 2009.)
Finite Element Modeling of the TSV Assembly
Solder microbumps
Low-k die
UF-top: between low-k chip and TSV interposer TSV interposer
Organic substrate
Low k (4.5um) 80 micron 60 micron FTEOS: (5.6um)
Via top: 100um SiO2
Cu
Si
Via bottom 50um 70

Lau Zhang-Lau, et. al.
3D IC Integration Process Flow

Memory/active interposers Passive (Bare) interposers
Support Wafer
(1) Clean
(1) SiO2
(7) Support wafer (temporary) bonding

Support Wafer
(2) Photoresist (PR), develop, clean, oxide mask patterning, DRIE, PR strip, remove oxide mask, clean
(8) Via exposing by thinning

Support Wafer
(3) SiO2/barrier/seed layer deposition
(9) Back-side metallization/UBM

Support Wafer
(4) PR Patterning, Cu plating or W screen printing, PR & seed layer removal
(10) Wafer bumping

Support Wafer
(5) Residual Cu CMP
(11) De-bonding support wafer, Clean
(6) Front-side metallization/UBM

(12) C2C or C2W bonding
71
TSV Interposer with 2RDL on Top and 1RDL at Bottom

(a)
(c)
(d)
72
3D X-Ray showing the seams (voids) of Copper filled TSV

Cross-section of TSV with seams
3D x-ray image with the CT (computed tomography) reconstruction of the electroplated Cu

Lau
Seams/Voids
73 Phoenix nanomelx CT x-ray microscope in ASM, Singapore Zhang-Lau, et. al.
Electroplated Cu-Filled Void-Free TSVs

2D X-ray image at tilted angle (70o) for thru-view of the Cufilled TSV array in the Wafer
Lau
3D X-ray with CT (Computed tomography) Re-construction for Cu-filled TSVs
SEM Image showing Void-free Electroplated Cu Vias

Zhang, Lau, et al., IEEE/ECTC09
74
TSV Integrity Check: Resistance & FIB-SEM Inspection

SiN Ti Cu contact
CuNiAu PI
Cu via (top)
TSV SiO2/SiN PI
Cu via (bottom) PI Cu contact
TI PI
SnAg bump
TSV daisy chain resistance measurement: 10 vias + RDL + bump pad + probe contact = ~ 1.7 Single via resistance: < 0.17
75
Lau
Zhang-Lau, et. al.
Package Interconnects (Not-to-Scale)

Chip SnAg CuNiAu UBM Microbumps
TSV
SiO2/SiN
SnAgCu ordinary solderbumps Cu Pad BT-Substrate SnAgCu Solder Balls PCB

Lau
76
Potential Real Applications of TSV with RDL

The preferred via size is 30m. (For tapered via, its the larger dimension.) Eventually, it will go down to 5m. Most of the people use straight vias. The preferred depth of the thickness for memory stacking is 50m for now, but it will go down to 20m. The preferred depth of the thickness for active/passive interposer is ranging from 100 to 200m.
The via size should be as small as possible. Why?

1) Less thermal expansion mismatch between the Si (2,5x10-6/oC) and Cu (17.5x10-6/oC) 2) Lower cost (less Cu to be plated) 3) Higher throughput 4) More space for routing
Lau
77
Most TSVs are Blind Vias!

Since in most applications, the thickness of all device and bare wafers are > 200m, and the thickness of memory stacked is ranging from 20 to 50m and of active/ passive interposers is ranging from 100 to 200m, thus most
TSVs should be blind vias!

Note: The TSVs of CMOS image sensor are made by a via-last process, thus they are blind vias! 78
Reliability Assessment of the Package with TSV Interposer

21x21mm Chip on the 25x25mm TSV Interposer on the BT Substrate Si Interposer Chip A typical Thru-scan Image showing no Delamination after 1000 Thermal Cycles
BT substrate MST Level 3 CSAM + Thru-scan Electrical test measurement

Lau
Passed (0/8) Passed (0/8)
1000 TC Cycles (-40 to 125oC) Passed (0/8) Passed (0/8)

79
Zhang, Lau, et al., IEEE/ECTC09
Reliability Assessments
Uunderfill B
MST Level 3 CSAM + Thru-scan Electrical test measurement Passed (0/8) Passed (0/8) 1000 TC Cycles Passed (0/8) Passed (0/8) CSAM + Thru-scan Electrical test measurement ITEM Filler content Filler size ave. Filler size max. Tg (TMA) CTE < Tg CTE > Tg Modulus Viscosity UNIT Wt% um um C ppm/C ppm/C GPa Pa.s
Uunderfill A
MST Level 3 Passed (0/8) Passed (3/8) 1000 TC Cycles Passed (2/8) Passed (0/8)
Underfill A 65 2 10 100 28 90 11 80
Underfill B 65 0.6 3 100 26 90 12 45
A typical Thru-scan image showing no delamination after 1000 TC cycles (-40 C to 125 C)
Lau
Underfill B with smaller filler sizes (BETTER) 80
Zhang-Lau, et.al
TSV with 2-RD on Top-side and 1-RDL at the bottom-side (After 1000 cycles from -25 to 140oC)
After 1000 cycles (-25 to 140oC)
81
Lau Zhang, Lau, et.al
Failure Analysis (Thermal Cycling)

A B
A Area of delamination cracks B
Thru-scan Image of failed unit
cracks
The corner delamination leads to crack in the underfill below the chip corner.
Lau
Insufficient underfill 82 coverage at the chip corner.

Zhang-Lau, et.al
Various Approaches to Make TSV

Via First Approaches Start from the bare wafer
Start from the passivation Via Last Approaches Start from the complete wafer Etching first Start from the complete wafer Etching first
Lau
83
Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps
Aibin Yu1, John H Lau1*, Soon Wee Ho1, Aditya Kumar1 Wai Yin Hnin1, Ming Ching Jong1, Vaidyanathan Kripesh1, Damaruganath Pinjala1, Scott Chen2, Chien-Feng Chan2, Chun-Chieh Chao2, Chi-Hsin Chiu2, Chih-Ming Huang2, Carl Chen2
of Microelectronics, Singapore (Agency for Science, Technology and Research) (*now with Department of Mechanical Engineering Hong Kong University Science & Technology) 2Siliconware Precision Industries Co., Ltd.
84
Lau
1Institute
Side-Wall Evaluation
etch time = 1.8 times of passivation time
etch time = passivation time
1. The larger the ratio of etch cycling time/passivation cycling time, the thinner the sidewall 2. The etch/passivation time need to be balanced in order to make sure the passivation layer on the sidewall is thick enough to protect the sidewall during the Si etch
Yu, Lau, et.al.
85
Lau
Results of Assembly
Solder joints Si chip
Si carrier
TSV with Cu filling
1. The joining conditions are: pressure of 20MPa; bottom substrate temperature of 300 C up arm temperature of 350 C and time of 60 seconds. 2. Shear strength > 10MPa 3. Chip to chip assembly. More studies need to be done for chip to wafer assembly
Lau Yu, Lau, et.al.
86
Thermal Management Technology for 3D IC Integration
87
Lau
Integrated Liquid Cooling Solutions for 3D Stacked Modules

Heat exchanger Mini-Pump Mini Pump Adaptor Chip 1 Carrier 1 Si Spacer TSV PCB Fluid out Fluid in Gasket Adaptor Heat Exchanger
Not to scale!
Mechanical connection
Chip 2 Carrier 2 Solder joint
Lau
3D stacked module mounted on a PCB
Develop liquid cooling solutions for 3-D stacked module by integrated liquid cooling scheme using miniature pump to dissipate 200W. DARPA funded project: (HR0011-06-2-0007)
88
Navas, Tan, Tang, Lau, et.al., 2008 IEEE/EPTC
Chip Carrier Thermal Design
Single Inlet/Outlet Design

Large temperature variation in the chip (18C)
Dual Inlet/Outlet Design

Small temperature variation in the chip (10C)
89
Lau
Tan, Navas, Lau, et.al., 2008 IEEE/EPTC
Chip Carrier with Fluidic & Electrical Interconnection

Heat transfer enhancement structures Dual port fluid inlet Fluidic sealing ring TSV Seal ring for fluidic isolation from electrical I/O Micro-channels for heat transfer enhancement
Chip Carrier with Flip-chip mounted
Cut-away view of Chip Carrier
Developed chip carrier with electrical and fluidic interconnection for in-direct liquid cooling Fluidic sealing using solder joint to withstand pressure upto 1 Bar
Lau
Tang, Navas, Lau, et.al., 2008 IEEE/EPTC
90
Si-Carrier with TSVs and Fluidic Channels

Critical Dimensions TSV diameter: 200m TSV depth: 400m TSV pitch: 500m No. of TSV: 144 Fluidic channel depth: 350m Fluidic channel width: 100m Inlet & outlet: 0.5x3mm Carrier: 15.1x15.1mm
Fluidic Inlet TSV Fluidic Channels
Fluidic Outlet
Lau
Sealing ring around fluidic channel
* After bonding, electrical interconnects through the carrier are made by TSV with on wall metallization. * The fluidic channels are connected through inlet/outlet ports in the carrier. * There are sealing rings around both the fluidic path and the individual TSV to isolate the fluid from the electrical interconnects. After 1000 cycles of thermal cycling (-40C to 125C), the average die shear strength is 26.8MPa and shows no degradation after thermal cycling test. 91
Yu, Navas, Lau, Navas, et.al., IEEE/ECTC 2008
Integration of Fabrication Process

1. PECVD SiO2 deposition & pattern for TSV & fluidic channel 7. UBM deposition & pattern on both sides 8. PECVD SiO2 deposition & pattern on backside
2. Photoresist coating & pattern for TSV
3. Via etch with 100um deep & strip off photoresist
9. Fluidic in-let & out-let open with laser drill
4. Via & channel etch with 300um
10. Au/Sn deposition & pattern on front side Fluidic in & out-let TSV electrical interconnection
5. PECVD SiO2 strip & backside wafer grinding to 400um
6. 1um PECVD SiO2 deposition on both sides

Lau
11. Wafer bonding 92

Optical Images of a Silicon Carrier after Dicing
Top Surface
Bottom Surface
93
Lau Yu, Navas, Lau, Navas, et.al., IEEE/ECTC 2008
3.5m 2.7m
Si-Carrier Fabrication Results

150m
300m
Sealing ring around fluidic channel
TSV
500m
Embedded channel and TSV TSV
Cross-section of TSV TSV
Sealing ring around TSV

2.7m 100m
UBM
AuSn solder
3.5m 2.7m 100m
Lau
UBM (Ti/Cu/Ni/Au:0.1/2/0.5/0.1m) layer around the TSV
AuSn solder ring after lift-off

94
Pressure Drop Measurements: Single vs. Two inlet and outlet

1200 Carrier with single inlet and outlet 1000 800 New carrier with 2 inlets and 2 outlets
DP (mbar)
600 400 200 0 0.05 0.15 0.25 0.35 0.45
Flow Rate (L/min)

Lau
Navas, Lau, et.al., 2009 ECTC 95
Thermal Cycling & Fluidic Test Results

Thermal cycling test between -40C (15min) and 125C (15min) for 500 cycles has been conducted for the bonded silicon carrier. The temperature ramping rate is 15C per minute. After test, the average shear strength of 20 samples is 26.8MPa, which is kept almost same as that before thermal cycling test. A test setup has been developed to circulate water under high pressure through the carrier. The water flow rate is increased gradually up to 400ml/min. It is found that no leakage is observed at high flow rate. The maximum pressure drop in the carrier is 6x104Pa, which indicates the quality of AuSn-solder bonding ring is good enough to seal the fluidic path.
Lau
Navas, Lau, et.al., 2009 ECTC 96
Thermal Analysis Model with Equivalent Thermal Conductivity

TSV Chip-1 Chip-2 Si Interposer with TSV
Chip-1
Chip-2
Equivalent Si Interposer without TSV
Lau
Lau, Tang, el.al., ECTC09
97
Thermal Analysis Model with Equivalent Thermal Conductivity

TSV Chip Non-TSV Lump-Block
PCB
PCB
TSV
keq,x = keq,y keq,z

Silicon Copper 390
98
Lau, Tang, el.al.
Lau
Thermal Conductivity (W/m-oC)
150
Equivalent Thermal Conductivity of TSV Chips

Copper-Filled TSV (many) TSV Chip
TSV Micro Bump Solder Bump
z y x
z Chip
q T z PCB
z
Adiabatic
Underfill
Adiabatic T q
x z
Isotherm (T1= 25oC)
q keq, z q keq, x
Lau
T dT z keq, z keq,z q dz z T T dT x keq, x keq,x q dx x T
Adiabatic x
Lau, Tang, el.al.
keq, y keq,x
Equivalent Thermal Conductivity of TSV Chips

q keq,z
q keq, x
T dT z keq,z keq,z q dz z T
T dT x keq, x keq,x q dx x T
keq, y keq,x
z D1 D1
P x D2 D2
D = (D1 + D2)/2
keq,z = 150 + 188D2P-2 keq,x = keq,y = 150 + 105D2P-2

Lau, Tang, el.al. Lau
100
Material Properties for Simulations

Chip Material k (W/m/oC) Dimension (mm) Power (W)
Si (TSV) Empirical Equation 5x5 0.2W
TSV
Cu 390 0.05 N.A
Bumps
SnAg 57 0.20 Height = 0.15 N. A
Underfill
Polymer 0.5 5x5x 0.15 N.A
PCB
FR4 // 0.8 0.3 76x114 x1.6 N.A
Lau
Lau, Tang, el.al.
101
Tj vs. Number of Stacked TSV Chips (Uniform Heat Source)

Tj 85 0C
Uniform Heat Source over the whole TSV Chip
TSV Chip
Chip thickness = 50m Chip power = 0.2W/Chip Heat Source Area = 5x5mm
Lau
Lau, Tang, el.al. 102
Tj vs. TSV Chip Thickness (Heat Source at Chip Center)
Heat Source
Chip
Chip Power = 0.2W/Chip Chip Heat Source Area = 0.2x0.2mm
Lau
Lau, Tang, el.al.
103
Hot Spot for Different TSV Chip Thickness

t=10m t=25m t=50m
t=100m
t=200m
Chip Power: 0.2W/Chip Chip Heat Source Area: 0.2x0.2mm
Lau
Lau, Tang, el.al. Lau, Lee, Prem, Yu, 3D MEMS Packaging, McGraw-Hill
104
Tj vs. the Gap (b) Between Heat Sources

a b a Chip Power = 0.2W/Chip Heat Source Area = 0.2x0.2mm b
Overlapped sources
Staggered sources
Lau
Lau, Tang, el.al.
105
A High-performance Chip on a TSV interposer

Micro Solder Bumps Ordinary Solder Bumps BT-Substrate
High Performance Chip
Special Underfill
RDL TSV Interposer
PCB
Solder Balls Ordinary Underfill
Lau, Tang, el.al.
106
Schematic Diagram and Modeling of the SiP

Chip Solder 2 Solder 3 Substrate PCB Chip Solders Equivalent model for TSV Interposer/Chip Substrate PCB Tj Equivalent model for TSV Interposer/Chip Solder 1 1-2-1 BU Substrate
Lau, Tang, el.al.
107
Geometry and thermal conductivity of materials for TSV interposer/chip

Component Interposer Material Thermal Conductivity (W/moC) Dimension detail (mm) Silicon TSV Copper TSV filler Polymer with Polymer with filler particles filler particles Al Copper
150
390
4.0
25
237
390
1.4 x 1.4 x 0.3
Varied
Copper plating thickness for partial filled via (5~25m) 0.15 ~ 0.6
TSV pitch (mm)
Lau, Tang, el.al.
108
Geometry and Thermal Conductivity of Materials for the SiP

Component Material Thermal Conductivity (W/m/C) Chip Si Solder 1 Interposer SnAg Si+ TSV (Cu) Solder 2 SnAg Substrate Buildup Solder3 SnAg PCB FR4
150
57
Keq
57
// 100 0.5
57
// 0.8 0.3
Pitch: 0.15 Pitch: 0.5 Pitch: 1.0 Height: 1-2-1 101x114 Dimension 21x21 Height:0.6 Variable Height: 0.1 0.08 0.75 (45x45x1) x1.6 (mm) Aver D: 0.1 Aver D: 0.6 Aver D: 0.08
Lau, Tang, el.al.
109
Equivalent thermal conductivity of TSV interposer/chip with different TSV pitches

200 190
z
Keq,z
Keq,x=Keq,y
0.1
Equivalent conductivity (W/m/K)
mm
180
0.3mm
x
B 0.05
170
mm
160
150
Pure Si
140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
TSV pitch B (mm)

Lau, Tang, el.al.
110
Junction to Ambient Thermal Resistance for Different Power Dissipation

Thermal resistance, Rja (degree C/W) 17 16.5 16 15.5 15 14.5 14 13.5 13 1 3 5 Power, P (W) 7 9 11
Tj 85 0C Tj 125 0C
Without interposer Interposer 25mmx25mm Series3 Series4
Interposer thickness: 0.3 mm Chip size: 21x21mm TSV parameter: pitch 0.3mm; size: 0.075mm; fully filled with cooper;
Lau, Tang, el.al.
111
Junction to ambient thermal resistance for different TSV interposer/chip size

17 Thermal resistance, Rja (degree C/W) 16 15 14 13 12 11 Without interposer 21 25 Interposer size, L (mm)
Lau, Tang, el.al. Interposer thickness: 0.3 mm Chip size: 21x21mm TSV parameter: pitch 0.3mm; size: 0.075mm; fully filled with cooper; LxL Tj
BU Substrate
P=2.5 W P=7.5 W
P=5 W P=10 W 35 45
112
Junction to Ambient Thermal Resistance for Different TSV Interposer/Chip Thickness

15.5
Thermal resistance, Rja (degree C/W)
15
14.5
14
13.5
Interposer size: 21mmx21mm
13
Interposer size: 25mmx25mm Interposer size: 35mmx35mm Interposer size: 45mmx45mm
12.5 0 0.1 0.2 0.3 0.4
Interposer thickness, t (mm)
Lau, Tang, el.al.
113
Junction to Ambient Thermal Resistance for Different TSV Parameters

21 Thermal resistance, Rja (degree C/W) 20 19 18 17 16 15 14 13 12 14 15 16 17 18 Chip size, a (mm) 19 20 21 22 bxb axa ratio b/a=1 ratio b/a=1.19 ratio b/a=1.67 ratio b/a=2.149
Lau, Tang, el.al.
114
Hot Spot for Different TSV Chip Thickness

t=10m t=25m t=50m
t=100m
t=200m
Chip Power: 0.2W/Chip Chip Heat Source Area: 0.2x0.2mm
Lau
Lau, Tang, el.al. Lau, Lee, Prem, Yu, 3D MEMS Packaging, McGraw-Hill
115
Solder Microbumps for 3D IC Integration
Lau
116
Micro Bumping & Assembly

Bump size = 30 m Bump pitch = 100 m Qualified by JEDEC T/C reliability tests
ENiG pad
Solder bump after reflow
50um Stack silicon die assembly with microbump

Lau
Cross-Section of Stack Die Assembly

117
Wafer Level Bumping
100m pitch (Solder) 25m pitch
200m pitch (Solder)
100m pitch (Cu post)

Lau
Focused ion beam (FIB) and SEM images

118
Progressive moving to micro bumping
25m-Pitch Solder Microbumps for 3D Chip Stacking

Si chip Solder micro bumps TSV UBM pad Si carrier
Organic Substrate
a. Bump Height b. Bump width c. Ti adhesion d. Cu seed layer e. Cu f. Sn g. Passivation:SiO2 Yu., Lau, et.al, 2008 IEEE/EPTC Si Chip a. Passivation 1 (SiO2) b. Passivation 2 (SiO2) c. Al pad (daisy chain) d. Electroless Ni e. Immersion Au f. Al pad opening 119
SEM and FIB Images of the 25m-Pitch Microbumps

Plated Sn at 25m pitch Cu6Sn3 Sn Cu3Sn
Cu
Focus Ion Beam (FIB) image Reflowed Sn at 25m pitch

Lau
120
Yu., Lau, et.al, 2008 IEEE/EPTC
Electroless Ni and Immersion Au UBM

Electroless Ni & Immersion Au at 25m-pitch
4m
Au Ni
Passivation
Yu., Lau, et.al, 2008 IEEE/EPTC 121
Cross-section of the Chips Joined at 300C, 60sec, 1 Kg (25-m Pitch)

Cu Si Chip Sn
Ni Si Carrier
Solder Joints (25m pitch) between Chips

Lau
Close-up look at one Solder Joint

Assembly Results of Solder Microbump/UBM with 8m Pads on 15m Pitch

Chip with solder bumps Cu Sn Ni
Chip with UBMs
Yu, Lau, et.al., IEEE/ECTC09

Lau
123
Shear Test Results of Microbumps

Shearing tool Shear direction Memory die 400 m Shear Height Solder joints at left side Logic die Solder joints at center Solder joints at right side
Al pad Ni (a) (b) (a) (b) (a) (b)

Lau
Underfill between the Chip and Chip Carrier

Si chip Underfill Si chip
Underfill in the assembly gap
Si carrier Si carrier Si chip Si chip Underfill and Microbumps in the assembly gap Underfill
Si carrier
Lau
Si carrier
125 Yu., Lau, et.al, 2008 IEEE/EPTC
Thin Wafer Handling

50m Thick (200mm Wafer)
126
3M Wafer Support System

(partnered with SUSS MicroTec AG in June 2009)
Lau
127
3M Wafer Support System with a Glass Supporting Plate
Lau
128

LTHC = light-to-heat conversion 3M UV-curable liquid adhesive LC-2201
Lau
129
Lau
130
EVG Thin Wafer Handling Technology s

(Partnered with Brewer Science)
Device Wafer: Front end processing (lithography, etching, etc.) Flip Wafer Device Wafer Carrier Wafer with intermediate layer
TEMPORARY BONDING
Device Wafer bonded on carrier wafer
Brewer Science s WaferBOND Back thinning and further processing

Device wafer (thin) on carrier wafer
DEBONDING
Cleaning Thin wafer handling Unloading in output format Lau
131
EVG Coating Equipment s
Lau
132
EV Group De-Bonding and Cleaning s Processes
133
Challenges in Support Wafer Method for Ultra-thin Wafer Handling Debonding

Wafer debonding 50um thick wafer Stripping of adhesive Perforated support wafer (Can be re-used) Perforated support wafer with 1mm diameter release hole
+
50m thick wafer
Problem encountered in support wafer method is wafer debonding 50um thick wafer breaks easily during wafer debonding Problem was solved by optimizing
Reduce the pitch of the release hole on the perforated wafer from 3.5mm to 2mm Increase the number of perforations on the edge of the support wafer 134
Lau Zhang, Lau, et.al., Eurosensor 2008
Process Steps for Making the Support Wafer

Si-Wafer
Photoresist lithography
DRIE & stripping of PR

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart y our computer, and
Back-grinding
The image cannot be displayed. Your computer may not have enough memory to op
Perforated support wafer

Zhang, Lau, et.al., Eurosensor 2008
135
Lau
Process Steps for Wafer Bonding and DeBonding

Wafer Bonding
Device wafer Spin coating of adhesive
The image cannot be displayed. Your computer may not h
Wafer Debonding
Wafer bonding
Device wafer Support wafer Device wafer
Stripping of adhesive
The image cannot be displayed. Your computer may not ha
Back-grinding to 50m
Perforated support wafer (can be reused) + 50m thick device wafer
Lau
136
Optimized Wafer Debonding Process

Stripping of adhesive Perforated support wafer (Can be re-used)
De-bonding Parameters Soak in waferbondTM remover solution at 90C Further clean with fresh waferbond remover solution 1. 2. Reduce the pitch of the release hole on the perforated support wafer from 3.5mm to 2mm Increase the number of perforations on the edge of the support wafer 50m thick wafer
+
50m thick wafer
Wafer Debonding
50m thick wafer
Support wafer
Lau
The process for ultra-thin (50um) wafer handling using support (or sacrificial) wafer has been established
137
Toshiba CIS with Through Chip Vias s

October 2007: Toshiba unveils its TCV Through Chip Viatechnology to enter mass production from January 2008 on its Dynastron series portfolio of CMOS image sensors :
Key features:
Dynastron series of CMOS image sensors, featuring an ultra small CSCM (chip scale camera module) will be the first camera module manufactured with TCV (Through Chip Via) technology By reducing pixel size, module size reduction up to 64% smaller than camera modules manufactured with the same sensors can be achieved Reduced wire bonding substrate area by mounting components directly on the wafer and running electrodes through the vias on the circuit board, securing them with balls of solders on the substrate The application of balls of solder and heat resistant lenses that are not affected by reflow significantly reduces the process for camera mounting to the circuit boards of mobile consumer products manufacturers.
Key manufacturing locations:

Lau
Source: Toshiba
CMOS image sensors at Oita Operations Camera module to be manufactured at Iwate fab
138
Finite Element Analysis of Toshiba CIS with TCV (TSV) s
139
Toshiba CMOS Image Sensor with TSV s
YAG laser
140
Important Process Steps in Toshiba CIS s with TCV (or TSV)
Drilling on Si (YAG laser)
1st
Si
Ni bump on Al-pad
2nd Drilling on epoxy resin (YAG laser)
Resin film lamination
Cu plating
Resin
141
Design and Process of 3D MEMS Packaging
John H. Lau Department of Mechanical Engineering Hong Kong University of Science & Technology Clearwater Bay, Kowloon, Hong Kong 852-2358-7181, johnlau@ust.hk
IMAPS 42nd International Symposium on Microelectronics, November 1-5, 2009, San Jose, California, USA
Lau
142
3D MEMS/ASIC Integrations
ASIC
MEMS
PCB
Advantages:
Less footprint Higher performance Lower cost Smaller form factor ASIC integrated with the MEMS device in 3D
MEMS
TSV (Through Silicon Via)
ASIC
PCB
Lau
143
2D vs. 3D Examples
MEMS ASIC
Seal Ring
Analog DevicesMEMS (accelerometer) integrated into an ASIC (SoC) 2D
MEMS chip attached to an ASIC chip (3D IC integration) [Prem and Lau, ECTC2008]
Lau
Cap Wafer Cavity Made by KOH Wet Etch and Dry Laser Machining
TSV Cavity TSV
Cross Section of Cap Wafer by Laser Machining
Cavity Cavity
Cavity by Laser Machining

Lau
Chen, Prem, Lau, et.al., C2W Low Temperature bonding method for MEMS applications IEEE/EPTC, December 2008, pp. 1-7. ,
Cavity by KOH Wet Etch 145
Cap Wafer TSV Made by Laser Machining
Cross Section of Cap Wafer by Laser Machining
Top View of Laser Drilled TSV

Lau
Cross Section of Laser Drilled TSV

146
Chen, Prem, Lau, et.al., C2W Low Temperature bonding method for MEMS applications IEEE/EPTC, December 2008, pp. 1-7. ,
ASIC Wafer
Fabricated ASIC wafer

Lau
ASIC Chip
Seal Ring
Prem, Lau, et.al., Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform, 147 A Chip-Size Wafers for MEMS and 3D SIP Applications IEEE/ECTC, May 2008, pp. 314-318 ,
C2W Bonding with Flip Chip Bonder (FC150)
Lau
Prem, Lau, et.al., Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform, 148 A Chip-Size Wafers for MEMS and 3D SIP Applications IEEE/ECTC, May 2008, pp. 314-318 ,
Bonding Accuracy: +/- 1 micron
Support Wafer with Cavity
Cavity Seal ring with low temperature solder
KOH etch is used for cavity formation

Lau Prem, Lau, et.al., Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform, 149 A Chip-Size Wafers for MEMS and 3D SIP Applications IEEE/ECTC, May 2008, pp. 314-318 ,
Results - Bond Characterization

Bond pad (MEMS/ASIC)
Support wafer
MEMS chip
LT Solder Seal ring bonding
Cross section picture of seal ring
X-ray picture of the bonded wafer
LT solder bonding on 300um pads
Lau
Cross section picture of bonding between MEMS and ASIC Prem, Lau, et.al., Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform, 150 A
Chip-Size Wafers for MEMS and 3D SIP Applications IEEE/ECTC, May 2008, pp. 314-318 ,
Results - Bond Characterization

Bond Force Temp Time Shear strength (Cap-ASIC) 71.6Mpa Shear strength (MEMS ASIC) 9.2MPa Hermeticity (atmcc/sec)
9KN
200degC
20mts
6x10-8
Completed package (Face-to-Face Bonding) with solder ball attached

Lau Prem, Lau, et.al., Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform, 151 A Chip-Size Wafers for MEMS and 3D SIP Applications IEEE/ECTC, May 2008, pp. 314-318 ,
High-Power AlGaInN (Flip-Chip) LED
MQW
Lau
152 J. Wierer, et.al., High-power AlGaInN flip-chip light-emitting diodes APL 2001, Lumileds ,
(a) A top view (through the substrate) and (b) schematic cross section view of the power AlGaInN FCLED. The dashed line represents the cross sectional cut shown in (b). The p contact is the lit area (blue). The p contact is reflective and redirects light (hv) up through the sapphire. The FCLED is flip-chip soldered to a submount allowing electrical connection. The MQW (multiple quantum well) consists of layers of InxGa1-xN wells and GaN barriers.
Lumileds FCLED on a Si Submount HP

Our eyes see the combined spectrum of blue and yellow LEDs as white! Blue LED out! Al2O3 Sapphire Substrate n-GaN n-electrode Solder p-GaN p-electrode Solder Si Submount
Lau
Yellow LED out! Y3Al5O12:Ce (YAG:Ce) Yellow Phosphor n-GaN MQW (InxGa1-xN wells and GaN barriers) p-GaN ITO, e.g., Sn2O3:In2O3=1:9 Reflective p-contact, e.g., Ni-Au, Ag, Al Passivation (Si2O)
153
Not to Scale!
Lumileds FCLED is in volume production HP

Input Power ~ 1 to 5W Chip 1x1mm2
Cathode Lead
154
3D LED and IC Integration

LED
IC chip such as ASIC, LED Driver, sensor, processer, power controller, RF, momory, etc.
Si Submount
Advantages: Less footprint Better performance Lower cost Lighter weight Smaller form TSV factor filled with Cu for
electrical, electrical and thermal, or just thermal
LED
3D integration of LEDs and IC chip such as LED Driver, ASIC, memory, sensor, RF, power controller, processor, etc.
ASIC, LED Driver, sensor, processer, power controller, RF, momory, etc. w/o cavity
TSV
Please be noted that the encapsulant, cover lens, thermal management system, etc. are not shown. Also, not to scale! Lau Lau, 3D LED, Semiconductor International, 2010
155
A Low-cost High-power 3D LED/IC Package
Plastic lens Transparent silicone encapsulant LED LED LED Driver, ASIC, or Processer TSV Die attach Cu Heat Slug PCB or Housing
TSV
Lau
Lau, 3D LED, Semiconductor International, 2010
156
A Low-cost High-power 3D LED/IC Package

Plastic Lens Active TSV interposer, e.g., LED driver, ASIC, or Processor Reflector cap
LED Driver, etc.
silicone encapsulant
TSV TSV LED TSV LED
TSV
Thermal Interface Material (TIM) Cu Heat Slug Heat spreader/sink
Solder PCB or Housing
Adhesive
Not to Scale!
Lau
Lau, 3D LED, Semiconductor International, 2010
157
3D Stacking of Optoelectronics on Optical Printed Circuit Board

TRANSMITTER
Heat Spreader
Serializer
Laser Driver VCSEL
RECEIVER
Heat Spreader
DeSerializer
TIA
Polymer Waveguide
PIN Photo Diode
PCB
Not to scale
10 cm (Polymer Waveguide) TRANSMITTER

*10 Gbps VCSEL (0.31x0.4x0.2mm, 2.2V, 33mW, 16W/cm2) *10.7 Gbps VCSEL Driver (2x2x0.3mm, 3.3V, 0.35W, 6-35W/cm2) *10 Gbps 16:1 Serializer or Multiplexer (4.5x4.5x0.8mm, 3.3V, 2.5W, 2.5-6.7 W/cm2) *10 Gbps PIN Photodiode (0.31x0.4x0.2mm) *10.7 Gbps Transimpedance Amplifier or TIA (2x2x0.3mm) *10 Gbps 1:16 DeSerializer or DeMultiplexer (4.5x4.5x0.8mm, 3.3V, 2.5W, 2.5-6.7W/cm2)
RECEIVER
Lau, et.al., Optical, Electrical, Thermal, and Mechanical Design and Analysis of 3D Stacked Optoelectronics on 158 Optical Printed Circuit Boards to be published in IEEE Trans. on Advanced Packaging. , Lau
VCSEL, Laser Driver, Serializer (Mux), and Polymer Waveguide

4.5 mm Multiplexer (Mux) 2 mm 0.7 mm
Laser Driver
VCSEL
0.8 mm 0.3 mm Cu Post Polymer Waveguide
Solder Joint 10 m Cladding 85x90 m
PCB
Not to scale
z x
Core 50x70 m
25 m
Polymer Waveguide: The refractive indices for the core and cladding are 1.5622 and 1.5544, respectively
VCSEL, Laser Driver (LD), Serializer (Mux), and Cu Post with Solder
Multiplexer (Mux) Cu Post
Multiplexer (Mux)
Cu Post LD Solder Joint Solder VCSEL
Lau, et.al., Optical, Electrical, Thermal, and Mechanical Design and Analysis of 3D Stacked Optoelectronics on Optical Printed Circuit Boards to be published in IEEE Trans. on Advanced Packaging. ,
160
Lau
Simulated Model Showing the Direct Coupling of the Optical Signal

VCSEL 30oC
Opt oele from ctroni wav c hei gh e gu ide t
45oC
Photodiode
Simulation Conditions: VCSEL: half-divergence angle = 15o PD: active area = 40m Assume no waveguide loss Assume mirror loss = 0.6dB
W av egu id
Simulation Results: (1) For VCSEL and PD height = 250m (wire bonding components) Direct Coupling Loss = 8.5dB (2) For VCSEL and PD height = 50m (flip chip components) Direct Coupling Loss = 5.0dB
Polymer Waveguide: The refractive indices for the core and cladding are, respectively, 1.5622 and 1.5544.
161
Lau, et.al., Optical, Electrical, Thermal, and Mechanical Design and Analysis of 3D Stacked Optoelectronics on Lau Optical Printed Circuit Boards to be published in IEEE Trans. on Advanced Packaging. ,
Coupling Loss vs. the Height of Optoelectronic Components

9 8.5 8
Loss (dB)
7.5 7 6.5 6 5.5 5 4.5 4 0 50 100 150 200 250 300
Height (um)
162
Lau
Simulation Model of LD with Serializer and Results

Driver Driver
Serializer 2 wires in parallel
Serializer 4 wires in parallel
Temperature Distribution of the 3D Stacked Optoelectronics
Cross-Section View
3D View
Heat Spreader
Mux LD VCSEL
Mechanical Analysis of the 3D Stacked Optoelectronics on PCB

Serialize r
LD or PIA VCSEL or PIN
or DeSer
ializer
Cu Post Solder Joint Optical PCB

140
Temperature (oC)
120 100 80 60 40 20 0 -20 -40 -60 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
Time (sec)
Max. Miss Stress and Equivalent Creep Strain at the Corner Solder Joint
Maximum von Mises Stress = 0.994 x 107Pa
Maximum Equivalent Creep Strain = 0.0121
166
Lau
Integrated Planar Optical Waveguide PCB

Solder Bumps
VCSEL Photodiode
Polymer Waveguide
FR-4 PCB
45Mirror (end) formed by Excimer Laser Processing
Lim, Lau, et.al., Demonstration of high frequency data link on FR4 Printed Circuit Board using optical waveguides to be published in IEEE Trans. on Advanced Packaging (Also, IEEE/ECTC 2007) . 167 Lau
Optical Waveguide PCB
Lim, Lau, et.al., Demonstration of high frequency data link on FR4 Printed Circuit Board using optical waveguides 168 to be published in IEEE Trans. on Advanced Packaging (Also, IEEE/ECTC 2007) . Lau
10 Gbps Optical Link on FR-4 PCB

Transceiver Module SMA Solder bump TX1
Waveguide
Transceiver Module Driver ICs MAX3 992 VCSEL & PD Semirigid Coaxial Cable 10 Gbps Tcvr Module Receiver circuits
Package see through from top Lenses
MAX3 992
RX2
Mirror
Driver ICs
VCSEL & PD
Transmitter circuits
10 Gbps Tcvr Module
Schematic cross section of the OECB module

Ramana, Lau, et.al., Bi-directional Optical Communication at 10 Gb/s on FR4 PCB using Reflow Solderable 169 SMT TransceiverIEEE/ECTC 2008 Proceedings
Lau
Final Assembly
Eye diagram for 6Gps
Eye diagram for 10Gps

170
Lau
Ramana, Lau, et.al., Bi-directional Optical Communication at 10 Gb/s on FR4 PCB using Reflow Solderable SMT TransceiverIEEE/ECTC 2008 Proceedings
Embedded Polymeric Optical Waveguide
VCSEL
waveguide
PD
Cu prepreg
Via hole Mirror
Via hole Mirror
Cu prepreg prepreg Cu prepreg Cu
Lim, Lau, et.al., Optimization and Characterization of Flexible Polymeric Optical Waveguide Fabrication Process 171 for Fully Embedded Board-level Optical InterconnectsIEEE/EPTC 2008 Proceedings. Lau
Fabrication Process for Embedded Polymer Waveguide

Polyimide Si Thermal Release Film Core Si 5. Peel off the soft PDMS mold after the core material is fully cured Mirror Si 6. Mirror forming with mechanical dicing Metal coating Core Material Si 7. Metal coating on mirror surface Peel off
1. Lamination of thermal release film with Cu-PI film Lower Cladding Si 2. Spin coating of lower cladding (WIR30-480) PDMS Mold Si 3. Align the PDMS Mold
Si 4. Filled up the core material (WIR30-500) by capillary force and vacuum
Lim, Lau, et.al., Optimization and Characterization of Flexible Polymeric Optical Waveguide Fabrication Process 172 for Fully Embedded Board-level Optical InterconnectsIEEE/EPTC 2008 Proceedings. Lau
Fabrication Process
Upper cladding
NOTE
The waveguide shown in Step 11 doesn have any alignment marks, t thus another layer of metal (Cu) is used for the lamination of optical PCBs/substrates and it is placed on top the polyimide film right after Step 1. Alignment
Cu Si Mark Thermal Release Film
Si
8. Spin-coat the upper cladding (WIR30-480) followed by UV exposure and post baking Polyimide film
Si
9. Lamination of polyimide film (25 m)
Polyimide
Si
Heat
10. Heat Up to 170C
Then go through all the same process Steps 2 through 11, then we have
Polyimide Waveguide Mirror Alignment Mark Cu 173
11. Final flexible waveguide after released out from Si wafer
Lim, Lau, et.al., Optimization and Characterization of Flexible Polymeric Optical Waveguide Fabrication Process Lau for Fully Embedded Board-level Optical InterconnectsIEEE/EPTC 2008 Proceedings.
Fabrication of PDMS Mold

Si
UV Expose
Spin-coating of SU-8 (70m)
Si Si
Dispense PDMS
Lithography Process Master Substrate of Waveguide Pattern PDMS (Poly-dimethylsiloxane) is dispensed on top of the master substrate
Peel Off
Si
PDMS Mold
Si
Lau
Peel off the cured PDMS Mold

174
Liang, Lau, et.al., Fabrication and Optimization of the 45 Micro-mirrors for 3-D Optical Interconnections IEEE/EPTC 2008 Proceedings. ,
Fabrication of the 45 Micro-mirrors

b)
45 Micro-Mirror
45 Micro-Mirror
Supporting substrate Supporting substrate
Light
Liang, Lau, et.al., Fabrication and Optimization of the 45 Micro-mirrors for 3-D Optical Interconnections , IEEE/EPTC 2008 Proceedings.
175
Lau
Micro-Mirror Forming by Dicing

Polymer Waveguide
Light
Mirror
Liang, Lau, et.al., Fabrication and Optimization of the 45 Micro-mirrors for 3-D Optical Interconnections , IEEE/EPTC 2008 Proceedings. 176 Lau
a)
The defect in the shape of the 45 micro-mirror will affect the coupling efficiency. It is due to the uncured waveguide material which is still in soft and elastic state. Solution: The waveguide must be fully cured and the optimizing curing condition for the waveguide is UV intensity of 15-18 mw/cm2 for 1.5 hours in nitrogen environment.
a) Defects b)
Micro-Mirror: Problems and Solutions b)
Side view of the 45 micro-mirror a) partially cured sample & b) fully cured sample Lau
Liang, Lau, et.al., Fabrication and Optimization of the 45 Micro-mirrors for 3-D Optical Interconnections IEEE/EPTC 2008 Proceedings. ,
177
Angle Determination of the Micro-Mirror

1. 2. 3. Cross section the optical waveguide. The cross-section is captured using the SEM. A 3D graphical software is used to measure the angle of the micromirror. The angle measurement results of Angle 1 and Angle 2
Dividing Line Dividing Line Mirror Line 1 1 Mirror Line Baseline Baseline Mirror Line 2 Mirror Line 2
g An
le 1
An gl
e2
178 Liang, Lau, et.al., Fabrication and Optimization of the 45 Micro-mirrors for 3-D Optical Interconnections IEEE/EPTC 2008 Proceedings. ,
Lau
Measurement of the 45 micro-mirror
Fabrication of Polymer Waveguides

6
Side ViewWaveguide
Polyimide
Si
5
Cu Alignment Marks for PCB/Substrate Singulation of 6 x5 Laminations
(by Mechanical Dicing) Top View

Alignment Marks for dicing the mirrors
Front View
Si
Liang, Lau, et.al., Fabrication and Optimization of the 45 Micro-mirrors for 3-D Optical Interconnections IEEE/EPTC , 2008 Proceedings. Lau
Waveguide
Dicing Line 179
Vertical-optical channel VCSEL
PCB Lamination with Polymer Waveguide Layer

PD Copper Prepreg Polymer waveguide layer First lamination UV laser open Cu window X-ray drill alignment hole & inner layer patterning
Prepreg Upper cladding
Copper Polymer waveguide layer Alignment Polyimide Copper marks Press dry film & CO2 laser drill blind via
Second lamination Lower cladding Polyimide Polymer waveguide Side view of Mirror Vertical-optical channel formation Etch bottom Cu & strip dry
VCSEL Top view of Mirror
PD
Flip chip assembly
180
IBM Backplane with Polymer Waveguide s (as an alternative to the Fiber) Solution
*Waveguides *Lamination Key Challenges: *Assembly (Alignment) *Performance *Reliability

Lau
Card (PCB) A
Polymer Waveguide Backplane)
Card (PCB) B
181
Design
3D IC Integration Technology Test
182
TSV w/o RDL Issues (Partial Listing)

1. Today, the only TSV product is the CMOS image sensor made by the PCB process 2. TSV cost is higher than that of wire bonding 3. TSV design software is lacking 4. TSV design guidelines are not commonly available. 5. Copper filling helps on thermal problems but increases TCE 6. Void-free copper filling usually takes a long time (lower throughput) 7. TSV cost for poor-yield IC wafers is high because TSVs are wasted on the bad dice 8. High cost for low TSV wafer manufacturing yield, especially for high-cost dice 9. TSV wafer yields are high (>99.99%) 10. Single-point touch-up on the TSV wafer is difficult 11. TSVs with high aspect ratios are difficult to manufacture at high yield 12. TSV wafer warpage is a problem owing to the TCE mismatch between Si and Cu 13. Thin TSV wafer handling is necessary during all the processes 14. Test methodology and software for TSV are lacking 15. High-volume production tools are lacking and/or expensive 16. TSV inspection methodology and software are lacking 17. TSV expertise, infrastructure, and standards are lacking 18. What are the cost-effective and reliable TSVs and for what IC devices? 19. How large is the TSV market? 20. What is the life cycle of TSV? 183
3D IC Integration Issues (Partial List)

Design guidelines & softwares are not available Test methods and equipments are lacking Known-good-die (KGD) are required TSV with RDL usually are required Microbumps usually are required Equipment accuracy for alignments Fast chips mixed with slow chips Large chips mixed with small chips Wafer thinning and thin wafer handling during processes Thermal issues: 3D circuits increase total power generated per unit surface area. Chips in the stack may be overheated if cooling is not provided properly Thermal issues: Space between chips may be too small for cooling channels (no gap for fluid flow) Thermal issues: Thin chips create extreme conditions for on-chip hot spots Thermal issues: Low cost thermal management solutions are desperately needed for widespread use of 3D IC integration 3D inspection methodology 3D expertises are lacking 3D infrastructure 3D standards
184
Our Opportunities
1.TSV w/o RDL (redistribute-layer) 2. Inspection of TSV with RDL 3.Testing of TSV with RDL 4.Thin wafer strengthening and handling 5. Micro solder bumping and assembly 6. Low-temperature C2C, C2W, and W2W bonding 7. Active/passive interposers 8. 3D Hybrid IC 9. 3D MEMS 10. 3D LED 11. Thermal managements of 3D systems 12. (a) Design for Performance, (b) Design for Reliability, (c) Characterization Measurements and (d) Reliability Tests of 3D IC Integration
185
3D IC Integration
3D Si Integration
Cu-Cu bonding
Mass Production
Bumpless
SiO2 bonding

Lau
3D MEMS; 3D LED
Bumpless
2008 2011-13
2010 2013-15
Low volume production = only a handful of companies are SHIPPING it; Mass production = many companies are SHIPPING it. 186
Moore Law vs. Moore-Than-Moore s

Moore Law s
2D SoC
More than Moore

3D IC Integration
Thin Chip
3D Si Integration
Thin Chips

MEMS
TSV
MEMS
Micro Bumps
Wafer-to-wafer bonding Very short wiring in 3D Si integration with very tiny TSVs, thin wafers/chips, and bumpless (no bumps!) Thermal management is a huge problem 187
Lau
Conclusions and Recommendations

TSV for 3D integration is at least a 26-year-old technology. However, with TSV and the new concept that every IC chip could have two active surfaces (3D IC integration), the doors are wide open for many innovative applications. The key difference between 3D IC packaging integration and 3D IC/Si integrations is that the latter two use TSV. The key difference between 3D IC integration and 3D Si integration is that the latter is bumpless. High volume products with 3D Si integration technology is far in the future. The electronics industry should strive to make more high-volume products with 3D IC integration technology chip yield (YT) plays the most important role in TSV manufacturing cost. If IC YT is low for a particular IC device, then it is not cost effective to use the TSV technology (because it makes the good dice too expensive), unless it is compensated for by density, performance, weight, and form factor. TSV manufacturing yield (YTSV) plays the second most important role in TSV manufacturing cost. Since this is the first post-wafer processing after the IC semiconductor fabs, the packaging assembly and test houses should strive to make YTSV > 99.99%. Otherwise, it will make the subsequent steps very expensive by wasting material and process on the damaged TSV dice.
188
Lau
Wafer-bumping yield (YB > 99.99%) plays the third most important role in TSV manufacturing cost. The wafer-bumping/packaging assembly and test houses should strive to make YTSVYB > 99.98% to minimize the hidden cost, since they cannot afford to damage good dice already having TSVs. Dates in the 3D IC integration roadmap most likely will be postponed because of the tough requirements of TSV manufacturing yield (YTSV > 99.99%) and the very high hidden costs2. Based on what happened about 20 years ago to the low-cost, solder-bump, flip-chip, and wafer-level packaging technologies, it will not be a surprise to see that, at the early stage, semiconductor foundries would like to do TSV and wafer bumping, but when the volumes pick up, the packaging assembly and test houses will do it all because they are flexible. Also, their core competence and major business are to build packages for the chips from the wafers given (made and tested) by the semiconductor foundries and to perform the final packaging test. Then they ship only the good ones to EMS (electronics manufacturing services) who perform the PCB assembly, in-circuit test, system (also called final or functional) test, and ship the product to the system houseshubs for distribution. Some system houses prefer to have their EMS ship them the in-circuit tested good PCBs, perform the final test in-house, and then ship the product. This is the infrastructure and how the electronics industry works. Of course, for some special reasons or niche applications, there are always a few exceptions.
189
Lau
Who going to do the TSV for 3D IC Integration? s

There are billions of vias (~0.1m) filled with Cu or W and in sub-micron scale, which Semiconductor Foundries do best! Thus, one of the core competences and major businesses of Foundries are to make these tiny vias! Foundriespersonals and equipments are too expensive to make the 3D IC integration TSVs, which are many times larger and less than the vias! Many tiny vias filled with Cu or W right on top of the devices, e.g., transistor This is a to-scale schematic of a 3D IC integration TSV (~5m). Usually, the TSV size is ~25 m Thus, the 3D IC integration TSVs should be done by Packaging Assembly and Test Houses. After packaging and testing, they will only ship the good ones to the EMS, who do the PCB assembly, in-circuit test, system test, and ship the product to the hubs of System Houses. This is the infrastructure and how the electronic industry works!
65nm Cu/low-k Chip by GlobalFoundries (2006) to show the tiny vias. A 3D IC integration TSV is drawn to show their contrast
Lau
TSV (Via-Middle) Process

Foundries want to do the TSVs! After they build the devices, e.g., transistor, then they build the TSV. After that, they build the tiny vias for those metal layer. Right now, because their equipments are too expansive to build the TSV, they cover the devices with a photoresist and open the areas for others to make the TSV. After the TSV is made, then the Foundries make the metal layers with tiny vias. Do you think the industry would work this way? What are the advantages? What are the drawbacks?
TSV (5m)
Lau
Thank you very much for your attention!
192
Lau

3D IC-Si Integrations (ECTC2010)

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State-of-the-art and Trends in 3D Integration

Objective of This Lecture

Lau, IEEE/ECTC09 PDC

Key Inventions and Driver for the Electronic Industry

Analog DevicesMEMS (accelerometer) integrated into an ASIC (SoC) 2D

IC Electronics Products Food Chains

Substrate Layout Substrate FAB & Test

PCB Layout PCB FAB & Test

Rework Very Unlikely

PCB Test System Test of PCBs in Chassis Ship

Conventional Packaging Technologies

Plastic Ball Grid Array (PBGA)

Flip Chip Plastic Ball Grid Array (FC-PBGA)

Wire Bonding Chips on Board

Printed Circuit Board

Printed Circuit Board

TSV Via-middle approach Lau, CSR, Apr, 2010.

Some Terminologies (Packaging view) s

Some Terminologies (Semiconductor)

Testing and yield challenges give way for package stacking

Applied R&D Basic R&D

Package on Package Stacking (PoP)

C2C, C2W, W2W Stacking W2W Stacking

Flesh memory in volume production!

Conventional Package-on-Package (PoP)

2 chips with wire bonds

1 wirebond chip and 1 flip chip face-to-face (F2F)

2 chips with wire bonds and with 1 flip chip on top

Memory (50m) with TSV and microbump

Low Volume Production Mass Production

Lau, 3D IC Integration PDC

Moore Law vs. More-Than-Moore s

More than Moore

MEMORY DISPLAY OPTO B DSP

Long Wiring (from A to B) in 2D SoC MEMORY OPTO

For both cases, Thermal Management is a big issue!

PROCESSOR. A ASIC, MCU, etc.

Samsung 3D Stacking with s TSV (Through Silicon Via)

Wafer before back-grinding

8-stack chips (50m each) connected with TSV and microbumps

Samsung 8 Gb DDR3 DRAM is Stacking with s TSV Chips and Microbumps

Samsung 32-Memory Stacking s

32 memory chips each with 20m thick

Intel Copper Via Plating in 3D s Interconnects

Hitachi 3D Stacked with TSV s

Memory (50m) with TSV and microbump

Low Volume Production Mass Production

Lau, 3D IC Integration PDC

IBM Generic 3D Technology Roadmap s for High-Performance Computing Systems

TSV for Interposer

TSV for 3D chip stacking

3D Stacked Die MCP

Substrate Embedded Die MCP

3D IC Integration Memory on Active Interposer (CPU)

Memory Solder micro bumps TSV Ordinary solder bumps

UBM pad CPU

TSV: The Smaller the Better

UBM pad Active Interposer, e.g., Logic

Ordinary solder bumps

Don expect the TSVs are evenly distributed on t 28 the chip!

TSV Applications in 3D Packaging

DuPont TSV Image Sensor s