Digital Systems and VLSI Design

Sayandeep Nag

sayandeep.nag@gmail.com Lecture 1

Session 1

Course Organization
Session 7
Circuit characterization Resistance estimation Capacitance estimation Switching characteristics

Review of Digital Logic Circuits Design Combinational circuits - Design steps Arithmetic Circuits - Full adder, Serial Adder, Adder/Subtractor, Ripple Carry Chain, Carry Look-Ahead adder, Carry Select Adder, ALU, Parity Generator, Comparator, Multiplier. Generalization of these Principles.

Session 2
PLA, PAL, PLD, CPLD, ROM, FPGA introduction Sequential circuits - Design steps Flip-flops, registers, counters

Session 8
CMOS gate transistor sizing Power dissipation Scaling principles

Session 3

Finite State Machines Introduction to FSMs, capabilities, minimization and transformation of sequential machines Synchronous and asynchronous FSMs

Session 9
CMOS circuit and layout design

Session 4

Session 10
Basic physical design of simple gates CMOS logic gate design CMOS logic structures Clocking strategies

Mealy and Moore machines State assignment of synchronous sequential machines Structure of sequential machines Verification and testing of sequential circuits

Session 5
Review of logic families Different logic families and their comparison Logic levels & Noise margin features Fan-in, Fan-out, Active load, Sinking & Sourcing currents Propagation delay MOS technology and VLSI

Session 11
Memory, registers & System timing aspects 3 transistor memory cell nMOS pseudo static memory cell, Two 4-bit words of RAM array

Session 12
Practical realities and ground rules Performance, Floor plan & Layout I/O pad layout System delays

Session 6
MOS transistor theory Introduction MOS device design equations CMOS inverter DC characteristics Static load MOS inverters Pass transistor, Transmission gate, tristate inverter

Session 1

Course Organization
Session 7
Circuit characterization Resistance estimation Capacitance estimation Switching characteristics

Review of Digital Logic Circuits Design Combinational circuits - Design steps Arithmetic Circuits - Full adder, Serial Adder, Adder/Subtractor, Ripple Carry Chain, Carry Look-Ahead adder, Carry Select Adder, ALU, Parity Generator, Comparator, Multiplier. Generalization of these Principles.

Session 2
PLA, PAL, PLD, CPLD, ROM, FPGA introduction Sequential circuits - Design steps Flip-flops, registers, counters

Session 8
CMOS gate transistor sizing Power dissipation Scaling principles

Session 3

Finite State Machines Introduction to FSMs, capabilities, minimization and transformation of sequential machines Synchronous and asynchronous FSMs

Session 9
CMOS circuit and layout design

Session 4

Session 10
Basic physical design of simple gates CMOS logic gate design CMOS logic structures Clocking strategies

Mealy and Moore machines State assignment of synchronous sequential machines Structure of sequential machines Verification and testing of sequential circuits

Session 5
Review of logic families Different logic families and their comparison Logic levels & Noise margin features Fan-in, Fan-out, Active load, Sinking & Sourcing currents Propagation delay MOS technology and VLSI

Session 11
Memory, registers & System timing aspects 3 transistor memory cell nMOS pseudo static memory cell, Two 4-bit words of RAM array

Session 12
Practical realities and ground rules Performance, Floor plan & Layout I/O pad layout System delays

Session 6
MOS transistor theory Introduction MOS device design equations CMOS inverter DC characteristics Static load MOS inverters Pass transistor, Transmission gate, tristate inverter

Course Organization

Textbook:

Digital Design Fourth Edition M. Morris Mano, Michael D. Ciletti

ISBN-10: 0131989243 ISBN-13: 9780131989245 Publisher: Prentice Hall Copyright: 2007

http://www.scribd.com/doc/48286018/Digital-Design-4th-Edition-M-MorrisMano

Please follow the lectures regularly its important !

Logic Circuits

A combinational circuit consists of logical gates whose outputs at any time are determined from only the present combination of inputs. A sequential circuit employs storage elements in additional to logic gates. Its outputs are a function of the inputs and the state of the storage elements ( a function of previous inputs)

Combinational Circuits
A combinational circuit can be specified with a truth table that lists the output values for each combination of input variables. It can also be described by m Boolean functions, one for each output variable.

Analysis Procedure
Label all gate outputs that are a function of input variables with meaningful arbitrary symbols. Determine the Boolean functions for each gate output. Label the gates that are a function of input variables and previously labeled gates with arbitrary symbols. Find the Boolean functions for these gates .

Repeat step 2 until the output of the circuit is obtained.

By repeated substitution of previously defined functions, obtain the output Boolean function.

Analysis of the Combinational Circuit

Step 1:
F2 = AB + AC + BC T1 = A + B + C T2 = ABC

Step 2 & 3:
T3 = F2 T1 F1 = T3 + T2

Step 4: F 1 = T3 + T 2 = F2 T1 + ABC = (AB + AC + BC)(A + B + C) + ABC = ABC + ABC + ABC + ABC

Design Procedure
From the specification of the circuit, determine the required number of inputs and outputs and assign a symbol to each.

Derive the truth table that defines the required relationship between inputs/outputs. Obtain the simplified Boolean functions for each output as a function of the input variables. Draw the logical diagram and verify the correctness of the design (manually or by simulation)

Example Code Conversion

Example Code Conversion (cont.)

Example Code Conversion (cont.)

Simplification of output function

z = D y = CD + CD = CD + (C + D) x = BC + BD + BCD = B(C + D) + BCD = B(C + D) + B(C + D) w = A + BC + BD = A + B(C + D)

Example Code Conversion (cont.)

Binary Adder-Subtractor
Half adder: A combinational circuit that performs the addition of two bits. Full adder: A combinational circuit that performs the addition of two bits and a previous carry. Binary Adder-Subtractor: A combinational circuit that performs the addition and subtraction with binary numbers.

Half Adder

S = xy + xy C = xy

Half Adder (cont.)

Full Adder Truth Table

Full Adder K Map

S = xyz + xyz + xyz + xyz C = xy + xz + yz

Full Adder In SOP From

Full Adder Implemented w/ Half Adders

S = xyz + xyz + xyz + xyz = x(yz + yz) + x(yz + yz) = x(yz) + x(yz) = xyz C = xy + xz + yz = xy + xz(y + y) + yz(x + x) = xy(1 + z + z) + xyz + xyz = xy + (xy) z

Full Adder Implemented w/ Half Adders (cont.)

Binary Adder
Example

Subscript i:
Augend Addend

3
1 0

2
0 0

1
1 1

0
1 Ai 1 Bi

Binary Adder
Example

Subscript i:
Input Carry Augend Addend

3
1 0

2
0 0

1
1 1 1

0
0 Ci 1 Ai 1 Bi

SUM
Output Carry

0 Si
1 Ci+1

Binary Adder
Example

Subscript i:
Input Carry Augend Addend

3
1 0

2
1 0 0

1
1 1 1

0
0 Ci 1 Ai 1 Bi

SUM
Output Carry

1
1

0 Si
1 Ci+1

Binary Adder
Example

Subscript i:
Input Carry Augend Addend

3
0 1 0

2
1 0 0

1
1 1 1

0
0 Ci 1 Ai 1 Bi

SUM
Output Carry

1
0

1
1

0 Si
1 Ci+1

Binary Adder
Example

Subscript i:
Input Carry Augend Addend

3
0 1 0

2
1 0 0

1
1 1 1

0
0 Ci 1 Ai 1 Bi

SUM
Output Carry

1
0

1
0

1
1

0 Si
1 Ci+1

Binary Adder

Carry Propagation

The total propagation time in an adder is the propagation delay of the carry through the full adder.

Carry Lookahead

Carry propagate: Pi = Ai Bi Carry generate: Gi = AiBi Si = Pi Ci ; Ci+1 = Gi + PiCi Carry output:

C0 = input carry C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2 G1 + P2 P1G0 + P2 P1P0C0

Implementation of Carry Lookahead

Adder with Carry Lookahead

Binary Subtractor

Overflow
Overflow: When the result of an n-digit addition produce n+1 digits. In signed numbers, if the carry into the sign bit position and the carry out of the sign bit position are not equal, an overflow occurred. Carries: +70 +80 +150 01 0 1000110 0 1010000 1 0010110 Carries: 10 -70 1 0111010 -80 1 0110000 -150 0 1101010

Binary Multiplier

Example of Binary Multiplier

Magnitude Comparator

A = A3 A 2 A 1 A 0 B = B3B2B1B0 Ai = Bi if xi = AiBi + AiBi for I = 0, 1, 2, 3 Comparison: (A = B) = x3x2x1x0 (A>B) = A3B3 + x3A2B2 + x3x2A1B1 +x3x2x1A0B0 (A<B) = A3B3 + x3A2B2 + x3x2A1B1 +x3x2x1A0B0

Magnitude Comparator

Decoders
A binary code of n bits is capable of representing up to 2n distinct elements of code information. A n-to-m-line decoder is a combination circuit that converts binary information from n lines to a m<2n unique output lines.

3-to-8 Decoder

3-to-8 Decoder

2-to-4 Decoder

Demultiplexer

Demultiplexer: A circuit that receives information from a single line and directs it to one of possible 2n output lines through n selection lines . A decoder with enable input (e.g., Fig 4.19) can function as a demultiplexer, called decoderdemultiplexer.

Combining Decoders

Combinational Logic Implementation using Decoder

S = (1, 2, 4, 7) C = (3, 5, 6, 7)

Encoder

Encoder: A digital circuit that generates n-bit binary code corresponding to the input value of the 2n input lines. Can be implemented by OR gates. However, if more than two inputs are active, the output produces an undefined combination. Using an input priority to identify higher significant bit.

Encoder

z = D1 + D3 + D 5 + D7 y = D2 + D3 + D6 + D7 x = D4 + D5 + D6 + D7

Multiplexer
Multiplexer (MUX): A combinational circuit that selects binary information from one of the 2n input lines through n selection lines and directs it to a single output.

Multiplexer

Multiplexer

Boolean Function Implementation using MUX

F(x, y, z) = (1, 2, 6, 7)

F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)