REDUCTION OF POWER DISSIPATION IN LOGIC CIRCUITS USING STACK TECHNIQUE CONTENTS

Chapter No. Description

Synopsis List of Figures List of Tables 1. 1.1 1.2 1.3 1.4 1.4.1 1.4.2 2. 2.1 2.2 2.3 Introduction Need of Low Power Design Technology Scaling and Its Induced Problems Power Dissipation in CMOS Circuits Mechanism of Power Dissipation Dynamic Power Static Power Leakage Power Background Work Leakage Power Reduction Techniques Power Cut-Off Techniques Leakage Reduction Techniques for SRAM Based Caches Implementation of Stack Techniques in Logic Circuits 3.1 3.2 3.2.1 3.2.2 Stack Effect Based Method Stack Technique Forced NMOS Stack Technique Forced PMOS Stack Technique 1 2 3 7 8 10 10 15 16 16

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19

3.

22 23 24 25 26

3.2.3 4. 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.5 4.5.1 4.5.2 4.5.3 4.6 4.6.1

Proposed Stack Technique Implementation of Stack Techniques in Combinational Circuits CMOS Inverter Forced NMOS Technique Forced PMOS Technique Proposed Stack Technique CMOS NAND Forced NMOS Technique Forced PMOS Technique Proposed Stack Technique CMOS NOR Forced NMOS Technique Forced PMOS Technique Proposed Stack Technique CMOS AND Forced NMOS Technique Forced PMOS Technique Proposed Stack Technique CMOS OR Forced NMOS Technique Forced PMOS Technique Proposed Stack Technique XOR GATE Forced NMOS Technique

27

28 29 31 32 33 34 36 37 38 39 40 41 43 44 46 47 48 49 50 52 53 54 55

4.6.2 4.6.3 4.7 4.7.1 4.7.2 4.7.3 5.

Forced PMOS Technique Proposed Stack Technique Full Adder Forced NMOS Technique Forced PMOS Technique Proposed Stack Technique Implementation of Stack Techniques in Sequential and Memory Circuits

56 57 58 60 61 62

64 65 65 66 67 69 70 71 71 72 72 74 75

5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.3.1 5.3.1.1 5.3.1.2 5.3.1.3 5.3.2 5.4 5.4.1 5.4.2 5.4.3

Sequential Circuits D-Flip-Flop D-Flip Flop Using NAND Gates Forced NMOS Technique Forced PMOS Technique Proposed Stack Technique Memory Module (SRAM) SRAM Cell Structure Stand By Reading Writing Differential Sense Amplifier

Schematic Of Conventional SRAM Cell Structure 76 Forced NMOS Technique Forced PMOS Technique Proposed Stack Technique 78 80 82

6. 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.2

Results and Observations Output Waveforms CMOS Inverter CMOS NAND CMOS NOR CMOS AND CMOS OR CMOS XOR Full Adder D-Flip Flop 6T SRAM Comparing Power Dissipation of Logic Circuits with the Stack Technique Conclusion BIBILOGRAPHY APPENDIX

84 85 85 85 86 87 87 88 88 89 90

91 93

7.

REDUCTION OF POWER DISSIPATION IN LOGIC CIRCUITS USING STACK TECHNIQUE

SYNOPSIS
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In todays IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits due to temperature-induced accelerated device and interconnects aging processes, and increases the cooling and packaging costs of these circuits. High power consumption leads to reduction in the battery life in the case of batterypowered applications and affects reliability, packaging, and cooling costs. The main sources for power dissipation are: 1) capacitive power dissipation due to the charging and discharging of the load capacitance; 2) short-circuit currents due to the existence of a conducting path between the voltage supply and ground for the brief period during which a logic gate makes a transition; and 3) leakage current. The leakage current consists of reversebias diode currents and subthreshold currents. Scaling down of threshold voltage results in exponential increase of the subthreshold leakage current. In this thesis the main aim is to reduce power dissipation. A new design method for various logical circuits design which is low power compared to general Static CMOS logic. In this technique the main aim is to reduce power dissipation in logical circuits, this is done by using stack techniques. The techniques include Forced Nmos Technique, Forced Pmos technique and implementing both Forced Nmos and Forced Pmos techniques in the same logical circuits which is known as proposed technique in this thesis, and calculated the power dissipation for each stack technique. The technique is implemented for basic gates, combinational circuits, and sequential circuits and also for memory cell structure namely 6T SRAM cell structure. The power dissipation of static logic circuits and the power dissipation by implementing the stack techniques are compared. The power dissipation of various logical circuits has been decreased by implementing the stack techniques when compared to the

conventional logic circuits. The tool used for simulation is Tanner EDA tool by using BSIM 4 180nm technology parameters. The results observed are noted in the tables.

REDUCTION OF POWER DISSIPATION IN LOGIC CIRCUITS USING STACK TECHNIQUE LIST OF FIGURES
Figure No.
1.1 1.2

Description
The Original Moore Law Moores law as illustrated by the transistor count per IC for Intel microprocessor from the 4004 to the Italium 2(9 bytes) Dynamic and leakage power trend as predicted Leakage mechanisms in an off-state NMOS transistor with Vg=Vs=0 and Vd=Vdd

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4 5

1.3 1.4

9 17 17 18 24 25 26 26 27 29 29 30 30

2.1 2.2 2.3 3.1 3.2 3.3 3.4 3.5 4.1 4.2 4.3 4.4

Leakage current paths in SCCMOS technique Leakage current paths in ZCCMOS technique Leakage current paths in GSCMOS technique Reducing the leakage using stacking Stack Technique Forced NMOS Stack Technique Forced PMOS Stack Technique Proposed Stack Technique CMOS inverter Symbol of CMOS inverter Schematic of CMOS inverter Layout of CMOS inverter

4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25

Schematic of Forced NMOS Technique inverter Layout of Forced NMOS Technique inverter Schematic of Forced PMOS Technique inverter Layout of Forced PMOS Technique inverter Schematic of Proposed stack Technique Layout of Proposed stack Technique Symbol of CMOS NAND Schematic of CMOS NAND Layout of CMOS NAND Schematic of Forced Nmos NAND Layout of Forced NMOS NAND Schematic of Forced PMOS NAND Schematic of Forced PMOS NAND Schematic of proposed stack technique NAND Layout of Proposed stack technique NAND Symbol of CMOS NOR Schematic of conventional NOR Layout of CMOS NOR Schematic of Forced Nmos NOR Layout of Forced NMOS NOR Schematic of Forced PMOS NOR

31 31 32 32 33 33 34 35 35 36 36 37 37 38 38 39 39 40 40 41 42

4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46

Layout of Forced PMOS NOR Schematic of proposed stack technique NOR Layout of Proposed stack technique NOR Symbol of CMOS AND Schematic of CMOS AND Layout of CMOS AND Schematic of Forced Nmos CMOS AND Layout of Forced NMOS AND Schematic of Forced PMOS AND Layout of Forced PMOS AND Schematic of Proposed Stack Technique AND Layout of Proposed Stack Technique AND Symbol of OR gate Schematic of CMOS OR Layout of CMOS OR Schematic of Forced NMOS OR Layout of Forced NMOS OR Schematic of Forced PMOS OR Layout of Forced PMOS OR Schematic of Proposed Stack technique OR Layout of Proposed stack Technique OR

42 43 43 44 45 45 46 46 47 47 48 48 49 50 50 51 51 52 52 53 53

4.47 4.48 4.49 4.50 4.51 4.52 4.53 4.54 4.55 4.56 4.57 4.58 4.59 4.60 4.61 4.62 4.63 4.64 5.1 5.2 5.3

Symbol of XOR Schematic of XOR Layout of XOR Schematic of Forced NMOS XOR Layout of Forced NMOS XOR Schematic of Forced PMOS XOR Layout of Forced PMOS XOR Schematic of Proposed stack Technique XOR Layout of Proposed Stack Technique XOR Full Adder Schematic of Full Adder Layout of Full adder Schematic of Forced NMOS Full Adder Layout of Forced NMOS Full adder Schematic of Forced PMOS Full Adder Layout of Forced PMOS Full adder Schematic of Proposed Stack technique Full Adder Layout of Proposed Stack technique Full Adder Block diagram of sequential circuits Symbol of D-Flip Flop D-Flip Flop using NAND gates

54 54 55 55 56 56 57 57 58 58 59 60 60 61 61 62 62 63 65 66 66

5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 6.1 6.2

Schematic of D-Flip Flop Layout of D-Flip Flop Schematic of Forced NMOS D-Flip Flop Layout of Forced NMOS D-Flip Flop Schematic of Forced PMOS D-Flip Flop Layout of Forced PMOS D-Flip Flop Schematic of Proposed Stack Technique D-Flip Flop Layout of Proposed Stack Technique D-Flip Flop Basic 6T SRAM cell CMOS SRAM Read analysis cell CMOS SRAM Write analysis cell Differential Sense Amplifier Schematic of Conventional 6T SRAM Cell structure Layout of 6T SRAM cell structure Forced Nmos SRAM CELL structure Schematic of Forced Nmos SRAM CELL structure Layout of Forced Nmos SRAM CELL structure Forced PMOS SRAM CELL structure Schematic of Forced PMOS SRAM CELL structure Proposed SRAM Cell Structure Schematic of Proposed SRAM Cell Structure Layout of Proposed SRAM Cell Structure Output Waveform of CMOS Inverter Output Waveform of CMOS NAND

67 67 68 68 69 69 70 70 72 73 74 75 77 78 79 79 80 81 81 82 83 83 85 86

6.3 6.4 6.5 6.6 6.7 6.8 6.9

Output Waveform of CMOS NOR Output Waveform of CMOS AND Output Waveform of CMOS OR Output Waveform of CMOS XOR Output Waveform of CMOS Full Adder Output Waveform of CMOS D-Flip Flop Output Waveform of CMOS 6T SRAM

86 87 87 88 89 89 90

REDUCTION OF POWER DISSIPATION IN LOGIC CIRCUITS USING STACK TECHNIQUE LIST OF TABLES
Table No.
1.1 4.1 4.2 4.3 4.4 4.5 4.6 4.7 5.1 6.1 6.2 6.3 6.4

Description
Technology scaling trends Truth table of CMOS inverter Truth Table of CMOS NAND Truth Table of CMOS NOR Truth Table of CMOS AND Truth Table of CMOS OR Truth Table of CMOS XOR Truth Table of Full Adder Truth Table of D-Flip Flop Power dissipation of combinational logic circuits

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6 30 34 39 44 49 54 59 66 91 91 92 92

Power dissipation of Sequential and memory circuits Delays and Pdps of combinational logic circuits Delays and Pdps of sequential and memory circuits