Microelectronics Failure Analysis

2004 ASM International. All Rights Reserved.
Microelectronics Failure Analysis Desk Reference, 5th Edition (#09109Z)
www.asminternational.org
Microelectronics Failure Analysis

_____________________________ Desk Reference Fifth Edition _____________________________
Edited by The Electronic Device Failure Analysis Society Desk Reference Committee
Published by ASM International Materials Park, Ohio 44073-0002 www.asminternational.org
2004 ASM International. All Rights Reserved. Microelectronics Failure Analysis Desk Reference, 5th Edition (#09109Z)
Copyright 2004 by ASM International All rights reserved No part of this book may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the written permission of the copyright owner. First printing, October 2004
Great care is taken in the compilation and production of this book, but it should be made clear that NO WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE GIVEN IN CONNECTION WITH THIS PUBLICATION. Although this information is believed to be accurate by ASM, ASM cannot guarantee that favorable results will be obtained from the use of this publication alone. This publication is intended for use by persons having technical skill, at their sole discretion and risk. Since the conditions of product or material use are outside of ASM's control, ASM assumes no liability or obligation in connection with any use of this information. No claim of any kind, whether as to products or information in this publication, and whether or not based on negligence, shall be greater in amount than the purchase price of this product or publication in respect of which damages are claimed. THE REMEDY HEREBY PROVIDED SHALL BE THE EXCLUSIVE AND SOLE REMEDY OF BUYER, AND IN NO EVENT SHALL EITHER PARTY BE LIABLE FOR SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES WHETHER OR NOT CAUSED BY OR RESULTING FROM THE NEGLIGENCE OF SUCH PARTY. As with any material, evaluation of the material under end-use conditions prior to specification is essential. Therefore, specific testing under actual conditions is recommended. Nothing contained in this book shall be construed as a grant of any right of manufacture, sale, use, or reproduction, in connection with any method, process, apparatus, product, composition, or system, whether or not covered by letters patent, copyright, or trademark, and nothing contained in this book shall be construed as a defense against any alleged infringement of letters patent, copyright, or trademark, or as a defense against liability for such infringement. Comments, criticisms, and suggestions are invited, and should be forwarded to ASM International.
ISBN: 0-87170-804-3 SAN: 204-7586 ASM International Materials Park, OH 44073-0002 www.asminternational.org Printed in the United States of America Multiple copy reprints of individual articles are available from Technical Department, ASM International.
Contents
GENERAL Chapter 1: Introduction Foreword The Microelectronics Desk Reference Charles F. Hawkins Chapter 2: Failure Analysis Process Flow Failure Analysis Process .. M. Steven Ferrier 1 ix x
System Level Failure Analysis Process: Making Failure Analysis a Value Add Proposition in Todays High-Speed, Low-Cost PC Environment 16 Michael Lane, Roger Bjork, Jeff Birdsley Board Level Failure Mechanisms and Analysis in Hand-Held Electronic Products 23 Sridhar Canumalla, Puligandla Viswanadham Failure Analysis Flow for Package Failures .. 34 Rajen Dias Wafer Level Failure Analysis Process Flow ... J.H. Lee, Y.S. Huang, D.H. Su Flip-Chip and "Backside" Sample Preparation Techniques .. Daniel L. Barton, Edward I. Cole, Jr., Karoline Bernhard-Hfer 40
43
Failure Analysis in a Fabless/Outsourced World 50 William Eslinger Circuit Edit at First Silicon .. Ted Lundquist, Mark Thompson 59
The Process of Editing Circuits Through the Bulk Silicon 72 Nicholas Antoniou Chapter 3: Failure Verification Curve Tracer Data Interpretation for Failure Analysis 77 D. Wilson A Primer on Simple Device Problems and Curve Tracer Characteristics 87 Douglas McCormac
Electronics and Failure Analysis .. Jerry Soden, Jaume Segura, Charles F. Hawkins
90
Analog Device and Circuit Characterization ... 111 Steve Frank IC Testing: Background, Directions, and Opportunities for Failure Analysis 123 Anne Gattiker, Phil Nigh, Thomas Vogels Using Scan-Based Techniques for Fault Isolation in Logic Devices 133 Greg Crowell, Ron Press Chapter 4: Failure Mode Failure Classifications The Power of Semiconductor Memory Failure Signature Analysis 140 Cary A. Gloor Common Defects Encountered During Semiconductor Manufacturing 147 B. Engel, K. Barth System Level Board Fabrication and Assembly Process Anomalies and Associated Failure Categories 153 Mary Ann Nailos, Dan Stein, Victor Hernandez Characterization of Anomalies in Flip-Chip Solder Joins in Ceramic Packaging. 158 Hsichang Liu, Jerry Nuzback, Robert Dineen Identification of Latent Defects in Advanced Glass-Ceramic MCM Packaging 163 Hsichang Liu, Thomas A. Wassick Electrostatic Discharge (ESD) and Latchup Failures in Advanced CMOS Technologies 168 Chris Putnam, Mujahid Muhammad, Robert Gauthier, Kiran Chatty, Min Woo, Mahmoud Mousa Electrical and Optical Characterization of Latchup .175 Franco Stellari, Peilin Song, Alan J. Weger, Moyra K. McManus, Robert Gauthier, Pia Sanda Chapter 5: Special Devices Failure Analysis of Microelectromechanical Systems (MEMS) 194 Jeremy A. Walraven, Bradley A. Waterson, Ingrid De Wolf Failure Analysis of Passive Components . 220 Stan Silvus Failure Analysis and Reliability of Optoelectronic Devices. 230 Robert W. Herrick
FAULT LOCALIZATION PACKAGE LEVEL Chapter 6: Non-Destructive Analysis Techniques Die-Level Fault Localization with X-ray Microscopy. 254 Steve Wang X-ray Microtomography Tools for Advanced IC Packaging Failure Analysis 261 Steve Wang Acoustic Microscopy of Semiconductor Packages. 269 Cheryl D. Hartfield, Thomas M. Moore Electronic Package Fault Isolation Using TDR. 290 D. Smolyansky Current Imaging Using Magnetic Field Sensors. 304 L.A. Knauss, S.I. Woods, A. Orozco FAULT LOCALIZATION DIE LEVEL Chapter 7: Depackaging Chip Access Techniques.. 313 S. Perungulam, K.S. Wills Low Stress FA Sample Preparation of Flip-Chip Devices with Low-K Dielectric Interconnect Layers.. 324 Charles Odegard, Becky Holdford, Cheng Chiu, Roger Stierman, Marvin Cowens, Nancy Ota Plastic BGA Module FA Process Flow Development. 330 Zhaofeng Wang, Lars Wagner, Chuan Cheah Chip-Scale Packages and Their Failure Analysis Challenges.... 333 Susan Xia Li Backside Analysis Using Re-Packaging Techniques. 342 Jianbai Zhu, Ray Harrison Chapter 8: Photon Emission (Electroluminesence) Localization Techniques Photon Emission Microscopy.. 348 Gary Shade Fundamentals of Photon Emission (PEM) in Silicon Electroluminesence for Analysis of Electronic Circuit and Device Functionality.. 357 Christian Boit Picosecond Imaging Circuit Analysis PICA 370 D. Vallett
Chapter 9: Microthermography Thermal Defect Detection Techniques.. 379 Daniel L. Barton, Paiboon Tangyunyong Thermal Failure Analysis by IR Lock-In Thermography... 399 O. Breitstein, J.P. Rakotoniaina, F. Altmann, T. Riediger, O. Schreer Chapter 10: Laser and Particle Beam-Based Localization Techniques Beam-Based Defect Localization Methods . 407 Edward I. Cole, Jr. Principles of Thermal Laser Stimulation Techniques 418 F. Beaudoin, R. Desplats, P. Perdu, C. Boit Introduction to Laser Voltage Probing (LVP) of Integrated Circuits 427 Siva Kolachina SEM and FIB Passive Voltage Contrast . 432 Z. Gemmill, L. Durbha, S. Jacobson, G. Gao, K. Weaver Electron Beam Probing ...439 John T.L. Thong DEPROCESSING AND IMAGING TECHNIQUES Chapter 11: Deprocessing Delayering Techniques: Dry Processes, Wet Chemical Processing, and Parallel Lapping 445 Kendall Scott Wills, Srikanth Perungulam Plasma Delayering of Intergrated Circuits .465 A. Crockett, M. Almoustafa, W. Vanderlinde The Art of Cross Sectioning .. 474 B. Engel, E. Levine, J. Petrus, A. Shore Delineation Etching of Semiconductor Cross Sections 494 S. Roberts, D. Flatoff Special Techniques for Backside Deprocessing . 497 Seth Prejean, Brennan Davis, Lowell Herlinger, Richard Johnson, Renee Parente, Mike Santana Deprocessing Techniques for Copper, Low K, and SOI Devices 502 Xuixian Wu, James Cargo PCB SMT Solder Joint Failure Analysis . 514 Norman J. Armendariz
Improved Methodologies for Identifying Root-Cause of Printed Board Failures 524 C. Hillman Chapter 12: General Imaging Techniques Optical Microscopy .. 541 John McDonald Scanning Electron Microscopy .. 560 W. Vanderlinde Ultra-High Resolution in the Scanning Electron Microscope.. 575 W. Vanderlinde Chapter 13: Local Deprocessing and Imaging Focused Ion Beam (FIB) Systems: A Brief Overview 584 Kultaransingh (Bobby) Hooghan Transmission Electron Microscopy for Failure Analysis of Integrated Circuits 596 Swaminathan Subramanian, Raghaw S. Rai, Sandeep Bagchi, Vidya S. Kaushik Atomic Force Microscopy: Modes and Analytical Techniques with Scanning Probe Microscopy .. 616 J. Colvin, K. Jarausch Chapter 14: Materials Analysis Techniques Energy Dispersive X-ray Analysis . 629 W. Vanderlinde Analysis of Submicron Defects by Auger Electron Spectroscopy (AES) 641 Juergen Scherer, Patrick Schnabel, Kenton Childs SIMS Solutions for Next Generation IC Processes and Devices 653 Gary Mount, Yung Liou, Han-Chung Chien Chapter 15: Important Topics for Semiconductor Devices Submicron CMOS Devices .. 663 Theodore A. Dellin Reliability and Quality Concepts for Failure Analysts 673 David L. Burgess CAD Navigation in FA and Design/Test Data for Fast Fault Isolation 677 William Ng Best of the EDFAS E-mail Discussion Forum 2000-2004 685 Dermot Daly, editor, Ted Hasegawa, Jerry Soden
Chapter 16: FA Techniques/Tools Roadmaps Failure Analysis Roadmaps .... 702 Lawrence C. Wagner Assembly Analytical Forum Analytical Tool Roadmap 706 Rajen Dias, Rama Goruganthu, Deepak Goyal, Cheryl Hartfield, Doug Hunt, Dick McClelland, Jim Cargo, Gay Samuelson, Roger Stierman Chapter 17: FA Operation and Management Education and Training for the Analyst . 718 Christopher L. Henderson Managing the Unpredictable A Business Model for Failure Analysis Service 723 C. Boit, K. Scholtens, R. Weiland, S. Grlich, D. Schlenker Management Principles and Practices for the Failure Analysis Laboratory 731 Richard J. Ross Education/Training Sources and References . 741 Christopher L. Henderson Chapter 18: Appendix Failure Analysis Terms and Definitions . 744 Ryan Ong JEDEC Standards for Failure Analysis.. 760 T. Hasegawa ISTFA Subject Index ...... 762 Ryan Ong
Foreword
This book is an updated version of all the Desk References that have come before it. All the previous editions have been an attempt (and a successful one, I might add) to gather various techniques and knowledge vital to electronic devices failure analysis and have them handy in one convenient reference volume. We never get them all because failure analysis is growing and evolving with every new technology node and new device type. New techniques are developed, older ones are refined and/or have had new uses found for them. Rather like failure analysts themselves, come to think of it. I wouldnt describe this book as a labor of love, but that phrase does describe the pay scale for the authors and committee members. Analysts the world over have taken the time to write articles for, edit, and compile this book. The members of the Desk Reference Committee are very grateful to those authors included here. And I am very grateful to my fellow members of the Desk Reference committee for making my job as committee chair so easy. Ill take this opportunity to name the members of this committee so the rest of you will know whom to thank. Ted Hasegawa, National Semiconductor Corporation, Santa Clara, CA USA Seth Prejean, AMD, Austin, TX USA Dermot Daly, Xilinx, Dublin, Ireland Brett Engel, IBM Microelectronics, Hopewell Junction, NY USA Bill Vanderlinde, Laboratory for Physical Sciences, College Park, MD USA Chris Boit, TUB Berlin University of Technology, Berlin, Germany David Su, TSMC, Hsin-Chu, Taiwan Tony Godrich, Intersil, Santa Clara, CA USA Stan Silvus, Southwest Research Institute, San Antonio, TX USA We dedicate this book to failure analysts everywhere, of all experience and educations levels. We know youll find it useful. Becky Holdford 2002-2004 Desk Reference Committee Chair Texas Instruments, Inc., Dallas, TX USA
The Microelectronics Desk Reference

Charles F. Hawkins University of New Mexico Albuquerque, New Mexico USA
Introduction How did you learn failure analysis? You took your background in physics, electrical engineering, chemistry, biology, or chemical engineering and were thrown into the lab for your on-the-job-training. You read abundantly in the ISTFA Proceedings, Electron Device Failure Analysis Magazine (EDFA), and equipment manuals, attended tutorials, and perhaps found a book or two. However, the single best source for all information was the ASM/EDFAS Desk Reference. You are th reading the 5 Edition of the Desk Reference, and it updates the field for leading edge techniques as well as retaining the tried and true methods. It also has a reference section to bring us all into a common understanding of the basic physics and electronics of the chips that we analyze. Dick Ross manages the failure analysis lab at the IBM Vermont facility. In his numerous talks on failure analysis management he estimates that it takes two years and $250k to bring a person up to productivity [Chapter 17]. He also observes that the average time that a person stays with the department is about five years. Rapidly training failure analysts is not just a pain, but also an economic necessity. The Microelectronics Desk Reference is perhaps the most consistent support for failure analysis education.
The major change since the previous Desk Reference Edition in 1999 is that the deep submicron technologies got deeper. We have gone from 0.25 um to 90 and 65 nm technologies, and that brought not only small feature size and huge numbers of devices on a die, but new materials. Copper, low-k and high-k dielectrics, and SOI are some of the examples of rapid challenge to failure analysts. Imaging techniques had to respond to the challenge of observing materials whose minimum features were smaller than the shortest wavelength of visible light. Failure analysis is now visibly a science requiring specialty teams. Who wrote this book? The EDFAS Desk Reference Committee invested considerable time to recruit from a pool of the best authors that they could find for each of the topics. The committee networking skills acquired from ISTFA, EDFAS, and business experience identified target authors. The authors are from around the world and from many companies. Many authors were invited based upon their ISTFA tutorial topics and positive ISTFA audience reviews. It does not get any better than this. The Desk Reference Editors built upon the previous edition. Where topics were retained, authors were asked to update the material. Failure analysis complexity grows like a rising tide, and this Desk Reference edition reflects this with new and expanded chapters. This
fifth Edition of the Desk Reference is more complex than previous editions reflecting the challenge of dealing with advanced technology parts. The Desk Reference has been used by counless failure analysts and in university courses. It is the best total collection of knowledge available, and that is why you bought it. While teaching separate courses in failure analysis, test engineering, reliability, design, and IC fabrication, a unique property appears. The failure analyst must know a significant fraction of the other disciplines, but the other disciplines have little demands made on them to learn the complexities of failure analysis. For example, electromigration, stress voiding, hot carrier injection, package failures, and corrosion are reliability issues that appear in failure analysis labs [Chapter 16]. Test engineering includes knowledge of complex testers, the electronic behavior associated with bridge, open, and parametric failures, defectbased test concepts and practice, the nuances of delay, path, and stuck-at fault testing, IDDQ testing, and low VDD testing [Chapter 3]. Design includes the different styles, such as high performance design with pipelining and domino circuits, low power, analog, and wireless circuits bring more knowledge demands on the failure analyst. And from the fab, we must understand all operations that can lead to yield loss. Failure analysts must understand materials of all types related to ICs. What copper dual damascene issues are treacherous? What are the contact and via mechanics that lead to failures? And how are these failures manifested? What about the chemistry of acids, bases, and organic solvents [Chapter 11]? Do we thoroughly understand EOS/ESD and why that damage mechanism so
penetrates failure analysis lab practice? No other discipline makes these knowledge demands. Now that weve acquired knowledge of this staggering list of topics outside of our labs, what about the knowledge and hands-on experience required of our own failure analysis practice.? We respect the failure analysis process from the painful experience of trying to take short cuts [Chapter 2]. First, we replicate the failure sent to the failure analysis lab. The issue of false failures (also called Type I or errors) never ceases to amaze us. The percentage of false failures, or good parts in a failed population, typically varies from 10% to 70% as experienced in the lab and reported in the literature. We throw away perfectly good parts that were expensive to make. People send parts to the failure analysis lab for analysis, and there is nothing wrong with them. That is a huge waste of time, but it happens as surely as the sun rises each morning. We also learn to respect the acquisition of as much data as possible before physically altering the part with decapsulation or backside exposure [Chapter 6,7,8]. As we go through the failure analysis process of gathering data at each level of disassembly, we learn to be so careful to extract the maximum information before moving to the next level. You typically cannot back up if you forgot some essential of data. During the process, all of your background knowledge and experience is intensely alive looking for the magic connection of facts that lead you to the failure localization. As the failure analysis process deepens, you find yourself using new and old tools and asking questions. How should the different
IVA tools be optimized [Chapter 10]? What does a failure detection imply? What are the laser-based, photon emission, and microthermal localization techniques, and where do we insert them in the process [Chapter 8, 9]. Soft defect localization and LADA are leading edge tools for finding the critical timing paths and timing related defect failures [Chapter 10]. These tools are laser-based demanding that we move creatively with laser wavelengths, beam sweeping equipment, and the image video monitor. We might find that we need a sophisticated digital tester to drive the part while we search for clues with our laser sweeps. Then its off to the layout maps to seek corroboration of observed failure symptoms to possible electronic structures. The failure analysis process wont let us go when we think at this point, we have found the fail site. The question is whether an aberrant fail site signature is truly the source of failure, or is something else driving this identified fail site? The next physical step is a bit scary, as it usually requires delayering or physical cuts that most likely will electrically disable the part. No more global level stimulus-response measurements are possible after this step. If the failure analysis process has been scrupulously followed to this point, then experience shows that you have a high chance of hitting the fail site accurately with your FIB cuts. FIB cuts of the defect site should show an aberrant structure consistent with all of the data previously collected. Lets back up for a moment. What about fail sites that cannot be photographed? This is a particularly relevant problem with the large statistical variation that we see within a die, die-to-die, or wafer-to-wafer. A single
transistor high threshold voltage could make a part fail a speed test. Or transistor carrier mobility may be low due to poor local crystalline structure, or a drain resistance may lie on he high side. Another invisible defect possibility is a soft thin oxide breakdown in a gate to drain region. These invisible fail mechanisms deal with slowing a signal. Statistical variation can also cause a digital part to fail if a signal propagation delay is too short. A fast clock signal to a flip-flop can violate setup time causing a functional failure. How do we approach these invisible failure sites in FA? Some techniques show promise. The PICA timing imager has had some success in identifying invisible sites by imaging the timing sequence of a part under repetitive cycles of a test pattern. However, PICA is showing some sensitivity issues as power supply levels are dropping below 1.5 V. More recent tools such as soft defect localization (SDL) and laser assisted device alteration (LADA) also address this difficult problem [Chapter 10]. Laser scanning has reported timing failure localization successes using thermal wavelengths (1340 nm) and electronhole pair generating wavelengths (1064 nm). A part is placed on the pass-fail edge by adjusting VDD or clock frequency, and when the scanning laser strikes a sensitive spot on the part, then the output signal is driven to a full pass or fail state. If the invisible failure site is speed sensitive to heat or electron-hole pair generation, then identification is reported. This problem is mentioned because it challenges the present boundaries of failure analysis capability, and these tools are described in Chapter 10.
Either of the two failure mechanisms sited above still requires a final identification. We cant afford to guess. A FIB cut and photo of a resistive via, or a TEM picture of a crystal dislocation [Chapter 12] or a subtle bridge defect leads to next question. What is the defect material, and what caused it to appear in this particular part? Element analysis identifying the atomic nature of the defect is often required [Chapter 14]. A stainless steel sliver indicates sloughing of particles in a vessel used in the fabrication process. A Cu sliver may indicate a CMP induced defect, or a resistive vias may be from poor manufacturing of this tiny structure, or it could be mask misalignment. The failure analysis process concludes when this root cause information is taken back to the relevant process activity, and process correction is done. The failure analysis process loop must close here to reduce the chances of it happening again. The whole failure analysis process can be tedious, but that is the nature of the challenge. How can we do it faster and more accurately. This brief description of the failure analysis process and some of its challenges was written to give you a flavor of what lies in the Desk Reference. The failure analysis world has achieved a rapid unity in a few short years. World cooperation lets us see the world outside of the four walls of our labs. The 5th Edition of the Desk Reference is proof that our combined efforts can make our jobs more efficient. Be grateful for the volunteers around the world who gave this work to you.
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2004 ASM International. All Rights Reserved.

Microelectronics Failure Analysis Desk Reference, 5th Edition (#09109Z)

Published by ASM International Materials Park, Ohio 44073-0002 www.asminternational.org

The Microelectronics Desk Reference

ASM International is the society for materials

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