Experiment-3 Experiment-3

Common-Emitter and Cascode BJT Amplifiers

Introduction The objectives of this experiment are to observe the operating characteristics of the two BJT amplifiers: the common-emitter singlestage BJT amplifier, and the cascade multi-stage BJT amplifier. When the BJT is regarded as a two-port network, one of the terminals must serve as a common point between the input port and the output port. If the input is on the base and the output on the collector, the emitter must therefore be common between the input and output ports, and the configuration is referred to as a commonemitter (CE) amplifier stage. In addition to the performance measurements, you should also pay attention to how the biasing of each amplifier stage is achieved, how the signal is coupled from stage to stage, and what design strategy has been adopted to desensitize the amplifier performance to variations in the transistor parameters. For each amplifier in this experiment, try to answer the question: What has been achieved by connecting the transistors in this configuration? To begin to answer this question, first identify whether a particular transistor is providing bias stabilization for other transistors, or is a gain stage in the signal path. Some transistors may simultaneously function in both roles. Then try to determine what components set the voltage gain of the amplifier. Track the path of the signal through the different stages of the amplifier and try to understand how much voltage gain is produced across each stage, how big the signal is at each node along the path, and what limits the signal swing at each node. Draw a schematic of the amplifier in your lab notebook and mark it up extensively to show the DC bias voltage at each node, the path that the signal takes from input to output, and any thing else that is of interest to you. The cascode circuits described in this experiment are not as simple as those previously used in this lab. While all of the component values are fairly close to the values needed to make the circuits work, normal variations in transistor parameters will require that each amplifier circuit be tuned-up slightly to center the signal swings or trim out the gain. This is left for you to do without any explicit instructions and is intended to force you to understand how the circuits work and to gain skill in electronic troubleshooting. Similarly,

R. B. Darling/R. Yotter/T. Chen

EE-332 Laboratory Handbook

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Experiment-3 the procedures will only ask you to measure certain performance parameters without giving explicit instructions. At this point, you should be comfortable making all of these measurements. Refer back to experiment 2 if you need to refresh your memory on making gain and frequency response measurements. Comment Some of the procedures in this experiment will utilize the CA3046 npn BJT array. The CA3046 is an RCA part number, and it is the same as the National Semiconductor part number LM3046. This integrated circuit comprises five npn BJTs which are fabricated on the same piece of silicon, and is a first approximation to the behavior of BJTs that one would find in a bipolar integrated circuit. The first two BJTs are tied together with a common emitter (pin 3), and the last BJT has its emitter tied to the substrate (pin 13), as shown in Fig. E3.0 below. All five npn BJTs have their collectors embedded into a common ptype substrate, which is connected to pin 13. In order to keep the collector-substrate pn-junctions reverse biased so that the BJTs will remain electrically isolated, the substrate on pin 13 MUST be tied to the lowest potential in the circuit, even if the fifth transistor is not being used. Any circuits using the fifth BJT of the CA3046 array MUST tie the emitter of this transistor to the lowest potential power supply rail. Failure to tie pin 13 to the lowest circuit potential will result in very unpredictable behavior for the circuit. Be warned!!
1 5

Q1

Q2

11

Q3

Q4

7 14

10

12

Q5 SUBSTRATE

Figure E3.0

13

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EE-332 Laboratory Handbook

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Experiment-3

Procedure 1
Comments

NPN common-emitter stage characteristics

With in input signal delivered to the base terminal and the output signal pulled from the collector terminal, the emitter terminal of the BJT is common to the input and output ports. Thus, this configuration is termed a common-emitter transistor stage. In the following circuit a potentiometer R3 will be used to adjust the value of the collector resistor. To keep the value of this resistance from accidentally being reduced all the way to zero, an additional pot-stop resistor R2 is added in series to establish a minimum resistance for this branch. This is always good practice for potentiometers to avoid producing unwanted short circuits which could cause serious circuit problems, in this case destroying the transistor. Whenever you design a circuit with a potentiometer in it, always consider the worst cases that will occur at each of the two endpoints of the potentiometer s settings. A little forethrought here will save you lots of parts and frustration later!

Set-Up

Using the solderless breadboard, construct the circuit shown in Fig. E3.1 using the following components: R1 = 100 k; 5% 1/4 W R2 = 330 ; 5% 1/4 W R3 = 5 k; potentiometer Q1 = 2N3904 npn BJT
+10V +10V

VDD PPS1

R 3 5k POT

R 2 33 0 OUTPUT V1 Signal generator GN D R 1 100k Q1 2N390 4 GN D

SCOPE CH-2

SCOPE GND

INPUT

SCOPE CH-1

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EE-332 Laboratory Handbook

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Experiment-3 Figure E3.1

Configure the PPS1 DC power supply to implement the VCC DC source in Fig. E5.1. Adjust the PPS1 power supply output to +10.0 V. Initially adjust the R3 potentiometer for a value of zero ohms, i.e. the series combination of R2 + R3 should be just R2 = 330 ;. Configure the signal generator to output a +3.0 V amplitude, +1.5 V DC offset, 60 Hz sinewave. Set the output impedance to a large value. Connect a 10v probe to the BNC connectors on each of the two input channels of an oscilloscope. Connect the probe from Ch-1 to the input end of R1 to monitor the input signal, and connect the probe from Ch-2 to the output node between R2 and Q1 to monitor the output signal, as shown in Fig. E3.1. Both oscilloscope probe ground leads and the ground lead from the DC power supply should all be connected to the emitter lead of transistor Q1. Configure the oscilloscope to display both channels with a vertical scale of 5 V/div, which includes the attenuation of the 10v probes. Set the input coupling of both channels to DC, and make sure that channel-2 is not inverted. Set the timebase to 5 ms/div. Set the trigger mode to AUTO with a source of Ch-1. Finally center both traces on the center of the screen by switching the input coupling for each channel to GND, moving each trace to the center hairline of the screen using the position controls, and then returning the input coupling switches to the DC position. Measurement-1 Next, turn the laboratory transformer ON. At this point, the oscilloscope should show a sinewave input for Ch-1 and only the positive half cycles of a sinewave output for Ch-2. Sketch both of these waveforms on the same set of axes in your lab notebook. The oscilloscope will now be used to directly display the voltage transfer characteristics (VTC) of this circuit. Do not change any of the connections from those of Fig. E3.1 and simply reconfigure the oscilloscope to display Ch-1 versus Ch-2 in an X-Y mode. Ground the inputs to both channels by setting the coupling switches to GND, and then switch the oscilloscope into the X-Y mode. (On Tektronix oscilloscopes, all you need to do is push the X-Y button in; on Hewlett-Packard oscilloscopes, you will need to access the X-Y mode through the MATH function menu.) Use the position controls to move the dot onto the cross-hairs in the exact center of the screen. Change the input coupling on each of the two channels back to DC
R. B. Darling/R. Yotter/T. Chen EE-332 Laboratory Handbook Page E3.4

Experiment-3 and the display should now show the VTC. Sketch the VTC shown on the oscilloscope screen in your notebook. Using the built-in meter on the DC power supply, vary the output voltage VCC over the range of 0.0 to +10 V. Switch back and forth between the voltage versus time and VTC (X-Y) modes of the oscilloscope to observe the effect on the output waveforms and the VTC. (On Tektronix oscilloscopes, you can do this by simply pushing the X-Y button in and out.) Jot down in your notebook the effect of varying the power supply voltage. Now examine how the VTC is affected by the value of collector resistance, R2 + R3. Vary the R3 potentiometer from 0 to 5 k; and switch the oscilloscope back and forth between displaying the VTC and displaying the voltage versus time waveforms to better appreciate what is happening in the circuit and how this is represented on the VTC. For larger values of R2 + R3, the VTC should have three distinct segments. Identify the region of transistor operation for each of these as: {cutoff, forward active, reverse active, or saturated}. Question-1 (a) From the measured VTC, is the npn common emitter stage inverting or non-inverting? (b) Explain why the VTC does not exhibit a saturation segment when the value of R2 + R3 is reduced to below a certain point. (c) Explain why R1 is needed in the circuit of Fig. E3.1. I.e., why can t the lab transformer be directly connected to the base of Q1? If this totally stumps you, short out R1 in the circuit and see what happens; just be prepared to buy a new 2N3904 from the stockroom, along with some new transformer fuses!

R. B. Darling/R. Yotter/T. Chen

EE-332 Laboratory Handbook

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Experiment-3

Procedure 2
Comment

PNP complement to the common-emitter stage

Every transistor circuit has a complement which is constructed by reversing the power supply polarities and reversing the sex of each transistor. If the parameters for each device are maintained, the performance of the complementary circuit will be symmetrical to that of the original. It is often easier to learn the characteristics of one type of circuit, say npn, and then simply take to complement to remember how the pnp version behaves. Procedure 2 duplicates procedure 1, but with the pnp complementary circuit. On the solderless breadboard construct the circuit of Fig. E3.2 using the following components: R1 = 100 k; 5% 1/4 W resistor R2 = 330 ; 5% 1/4 W resistor R3 = 5 k; potentiometer Q1 = 2N3906 pnp BJT This circuit can be constructed by simply replacing the Q1 transistor of procedure 1 with a type 2N3906 and reconfiguring the power supply to be negative on the collector of Q1.
INPUT SCOPE CH-1

Set-Up

GN D Signal generator V1 R 1 100k Q1

GN D

SCOPE GND

2N390 6 OUTPUT R 2 33 0

SCOPE CH-2

VDD PPS1 R 3 5k POT -10V -10V

Figure E3.2

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EE-332 Laboratory Handbook

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Experiment-3 Note that both oscilloscope probe grounds are again connected to the emitter terminal of Q1, but that the more positive terminal of the DC power supply is connected to the emitter. Configure a DC power supply to implement the VCC DC source in Fig. E3.2. Use a pair of squeeze-hook test leads to connect the output of the power supply to your breadboard. Turn the DC power supply ON and initially adjust its output to -10.0 Volts. Initially adjust the R3 potentiometer for a value of zero ohms. Connect a 10v probe to the BNC connectors on each of the two input channels of an oscilloscope. Connect the probe from Ch-1 to the input end of R1 to monitor the input signal, and connect the probe from Ch-2 to the output node between R2 and Q1 to monitor the output signal, as shown in Fig. E3.2. Configure the oscilloscope to display both channels with a vertical scale of 5 V/div, which includes the attenuation of the 10v probes. Set the input coupling of both channels to DC, and make sure that channel-2 is not inverted. Set the timebase to 5 ms/div. Set the trigger mode to AUTO with a source of Ch-1. Finally center both traces on the center of the screen by switching the input coupling for each channel to GND, moving each trace to the center hairline of the screen using the position controls, and then returning the input coupling switches to the DC position. Measurement-2 Next, turn the laboratory transformer ON. At this point, the oscilloscope should show a sinewave input for Ch-1 and only the negative half cycles of a sinewave output for Ch-2. Sketch both of these waveforms on the same set of axes in your lab notebook. The oscilloscope will now be used to directly display the voltage transfer characteristics (VTC) of this circuit. Do not change any of the connections from those of Fig. E3.2 and simply reconfigure the oscilloscope to display Ch-1 versus Ch-2 in an X-Y mode. Ground the inputs to both channels by setting the coupling switches to GND, and then switch the oscilloscope into the X-Y mode. Use the position controls to move the dot onto the cross-hairs in the exact center of the screen. Change the input coupling on each of the two channels back to DC and the display should now show the VTC. Sketch the VTC shown on the oscilloscope screen in your notebook. Using the built-in meter on the DC power supply, vary the output voltage VCC over the range of 0.0 to -10 Volts. Switch back and forth between the voltage versus time and VTC (X-Y) modes of the oscilloscope to observe the effect on the output waveforms and the
R. B. Darling/R. Yotter/T. Chen EE-332 Laboratory Handbook Page E3.7

Experiment-3 VTC. Jot down in your notebook the effect of varying the power supply voltage. Now examine how the VTC is affected by the value of collector resistance, R2 + R3. Vary the R3 potentiometer from 0 to 5 k; and switch the oscilloscope back and forth between displaying the VTC and displaying the voltage versus time waveforms to better understand what is happening. For larger values of R2 + R3, the VTC should have three distinct segments. Identify the region of transistor operation for each of these as: {cutoff, forward active, reverse active, or saturated}. Question-2 (a) From the measured VTC, is the pnp common emitter stage inverting or non-inverting? (b) From the recorded VTCs, estimate the voltage gain of the stage when it is used as an amplifier with the transistor Q1 in the forward active region of operation. Note: the voltage gain will be the slope of the VTC. (c) Verify that the voltage gain of the common emitter stage is proportional to the value of the collector resistance. Do this by dividing the voltage gain by RC = R2 + R3 = 330 ;, and by RC = R2 + R3 = 5330 ;, at the two limits of travel for the potentiometer.

R. B. Darling/R. Yotter/T. Chen

EE-332 Laboratory Handbook

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Experiment-3

Procedure 3
Comment

CE-CB cascode with EF buffer

A common-emitter (CE) followed by a common-base (CB) stage is termed a cascode. This is a very useful configuration which offers high bandwidth with good voltage and current gain. Build the circuit shown in Fig. E3.3. The insertion of the Q4 BJT produces the cascode. R6 will also need to be added to adjust the biasing. R1, R6 = 1.0 k; 5% 1/4 W R2 = 6.8 k; 5% 1/4 W R3, R5 = 3.3 k; 5% 1/4 W R4 = 100 ; 5% 1/4 W C1, C2 = 10 QF electrolytic Q1, Q2, Q3, Q4 = CA3046 npn BJT array
+10 V R 2 6.8 k 8 R 3 3.3 k Q 4 CA304 6 R 4 10 0 Q 3 CA304 6

Set-Up

+10 V

1 1 1 0

VC C PPS1 VI N C 1 + 10 uF SUBSTRATE 1 3 GN D R 1 1.0 k Q 1 CA304 6

R 6 1.0 k 1 2 3

6 7

C +2 10 uF

VOUT

5 4 3

Q 2 CA304 6

R 5 3.3 k

GN D

Figure E4.2 Measurement-3 Adjust the circuit and signal generator to produce clean 1.0 kHz sinewaves on the input and output. Measure and record the amplitude of both input and output, and then take the ratio to determine the voltage gain. Increase the frequency of the signal generator until the voltage gain falls to 70 percent of its value at 1.0 kHz. Measure and record this -3 dB bandwidth of the amplifier. Restore the frequency to 1.0 kHz, and increase the amplitude of the signal generator until the output signal is clipped at both the positive

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EE-332 Laboratory Handbook

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Experiment-3 and negative peaks. Measure and record the output voltage levels at which clipping occurs. Question-3 (a) Using your measured data, calculate the voltage gain of the amplifier in decibells (dB). (b) Explain what determines the bias current level of Q4. (c) Explain what advantage the addition of Q4 provides.

R. B. Darling/R. Yotter/T. Chen

EE-332 Laboratory Handbook

Page E3.10

Experiment-3

Procedure 4
Comment

High gain cascode

The input resistor R1 in the previous two amplifiers establishes the voltage gain and the input impedance. This stabilizes the gain against variations in transistor F, but produces a rather low value of voltage gain. By rearranging the first stage of the circuit, the input can be directly applied to the base of the input CE stage, greatly increasing its gain. Modify the circuit of Fig. E3.3 to that of Fig. E3.4 by altering the connections and bias resistors around Q1 and Q2. R1, R6 = 100 k; 5% 1/4 W R2 = 10 k; 5% 1/4 W R3 = 4.7 k; 5% 1/4 W R4 = 100 ; 5% 1/4 W R5 = 3.3 k; 5% 1/4 W C1, C2 = 10 QF electrolytic Q1, Q2, Q3, Q4 = CA3046 npn BJT array
+10 V R4 R2 10k 8 R3 4.7k 9 10 11 Q3 CA3046 Q4 CA3046 7 C3 10 uF SUBSTRAT E 13 GN D + Q1 CA3046 3 3 1 2 R1 100k R6 100k 4 5 Q2 CA3046 R5 3.3k 10 uF + C2 VOUT 100

Set-Up

+10 V

VC C PPS 1

GN D

C1 VI N + 10 uF

Figure E3.4 Measurement-4 Adjust the circuit and signal generator to produce clean 1.0 kHz sinewaves on the input and output. Measure and record the amplitude of both input and output, and then take the ratio to determine the voltage gain. Increase the frequency of the signal generator until the voltage gain falls to 70 percent of its value at 1.0 kHz. Measure and record this -3 dB bandwidth of the amplifier.

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EE-332 Laboratory Handbook

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Experiment-3 Restore the frequency to 1.0 kHz, and increase the amplitude of the signal generator until the output signal is clipped at both the positive and negative peaks. Measure and record the output voltage levels at which clipping occurs. Question-4 (a) Using your measured data, calculate the voltage gain of the amplifier in decibells (dB). (b) Compare the bandwidth of this amplifier to that of procedures 1 and 2 and explain the cause for the differences or similarities. (c) Explain what function Q1 provides in this new configuration, if any.

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