Comm2013 Measurements Project Project Regulations:

Number of students per group: 4 or 5 (not less and not more) Format of the report: there are no strict guidelines for the report, but it should have not more than 5 pages, you should deliver a CD that contains all project files with the report Examination procedure: projects will be graded based upon the delivered report and an oral discussion that must be attended by all team members. Deadline for sending group names: Thursday, 10 March 2011 12:00 am, send the names as st nd rd attachment in excel sheet (1 column is names in Arabic, 2 column is the section and the 3 column is the B.N.) please leave the subject and the mail content blank. If the names should be updated send the updated version with the mail subject updated email: comm2013@yahoo.com

Comm2013 Microprocessor Second Year Project Project Description:

-In this project, you should design a general purpose processor using VHDL targeting FPGA platform. The general purpose processor has the following instruction set:

Opcode 00000XXX

Instruction NOP

Operation No Operation

Register Instructions 00001Reg. 00010Reg. 00011Reg. Memory Instructions 00100Add. 00101Add. Logic instructions 00110Reg. 00111Reg. 01000Reg. 01001XXX Opcode Arithmetic instructions 01010Reg. 01011Reg. 01100XXX 01101XXX Branching instructions 01110Add. 01111Add. IN/OUT instructions 10001Reg. 10010Reg.

CLEAR Reg. MOV Reg. MOVR Reg. LOAD Reg. STORE Reg. AND Reg. OR Reg. XOR Reg. NOT Reg. Instruction ADD Reg. SUB Reg. INC DEC JMP Add. JMP Pos. IN Reg. OUT Reg.

Reg. 0 AC Reg. Reg. AC AC M[Add.] M[Add.] AC AC AC AND Reg. AC AC OR Reg. AC AC XOR Reg. AC NOT(AC) Operation AC AC + Reg. AC AC Reg. AC AC+1 AC AC-1 Unconditional jump If (AC>0) jump to address Add. Input to Reg. Output from Reg.

- Reg.: is an operand specifies which Register is used in the instruction. - Add.: is an operand specifies which Memory Location is used in the instruction. - AC: Accumulator - Opcode: is 5bits Given that we have eight data registers (Reg1 to Reg7) and the Comm2013 is interfaced with (8K X 1B) memory with an address bus that you will design its width and a data bus of 8bits. The (IR, MAR, PC) are 16bit registers (divided to Low and High Registers), the (AC, Data Registers, and MDR) are 8bit registers and the internal and the external bus of the Comm2013 core is 8bits. Design the memory as an array of registers or any other technique you may know by self-reading. Requirements: First: Design the ALU and verify its functionality using random input. Second: Design the Data path and verify its functionality for random inputs for the different operations. Show clearly in your reports the internal design and the main steps of design verification. Third: Design the control unit using any method you want.

Fourth:
To verify the correctness of your design, you will test it for a simple test program. Pseudo code: IN X, IN Y, Z= X+Y, OUT Z

Fifth: Write a simple code that provides certain functionality (innovation here is required and graded) on the microprocessors memory. Burn your design on an FPGA (it will be available in the lab). You will need to design the external circuit that is interfaced with the microprocessor. Try to be simple (feasible) and innovative.

Best Regards,