4

4.1 Circuit Structures

The TTL Logic Gate Series

In general, the functions of the various stages of any gate are similar to those of the inverter and NAND gates. It is good to remember, however, that many logic functions are implemented by the actual connections made in a circuit structure. Recall, for example, the input stage of the inverter. The input transistor T1 acts as a current steering and amplifying stage. It is T2 that essentially performs the inversion. Hence, in TTL structures, the
T1 T2

HI LO

combination of transistors in Fig. 4.1 will always perform an inverting operation.

LO HI

LO HI

Fig. 4.1 Inverting Structure

Remember, also, the input structure of the NAND gate. The input combination of multiple d a b
T1

emitters performs a logical AND operation on the inputs in the current steering mechanism. It is T2 that performs the inversion to give an overall NAND operation.

T2

Fig. 4.2 AND ing Structure

Consider a final structure where two transistors are essentially connected in parallel with a common load as shown in Fig. 4.3. Basically, if either transistor is turned on, it will conduct and draw current through the load making the output go low. Only when both transistors are OFF, tending to make the c a b VO output HI individually, will the output actually be HI. This is an AND operation and the connection is referred to as a WIRED AND connection. This circuit structure is equivalent to two inverters on the input of an AND gate which is logically equivalent to an NOR structure as can be seen from the table below and Fig. 4.4. Fig. 4.3 OR ing Structure 1

A LO

B LO HI LO HI

C HI LO LO LO

LO HI HI

Fig. 4.4 Logical Equivalent of Or ing (NOR) Structure 4.2 Standard TTL 74-Series Logic Gates Figs. 4.7 4.11 show complete circuit diagrams for some of the basic logic gates in the TTL 7400 series with typical component values included. The diodes shown on the inputs are protection diodes for the input transistors. These prevent negative voltages being developed at input terminals due to ringing on inductive lines connecting gates. Large, negative spikes at the input would tend to overbias the base-emitter junction of the input transistors and destroy them. These voltages are clamped to a diode drop by the input protection diodes.

(I) (II)

Inverter 7404 NAND Gate 7400 already covered

(III)

NOR Gate 7402

Transistor pairs T1 + T2 and T5 + T6 form inverters to the inputs. The parallel connection of T2 and T6 provides wired AND function as previously described. The output stage, T3 + T4 , is as before. This provides the function a . b = (a + b) which is the NOR operation.

(IV)

AND-OR-INVERT Gate 7451

This is really a combination of the NAND and NOR gate circuits. The multiple emitter input transistors T1 and T5 perform an AND function on their individual inputs. The subsequent transistors T2 and T6 invert the AND functions. The parallel connection of T2 and T6 provides the wired AND function as in the NOR gate. The overall situation is equivalent to that shown in Fig. 4.5. The notable feature of this gate is that it allows Boolean functions to be implemented in

sum-of-products form (the inversion can be corrected for) in a single gate with a propagation delay equal to that of an inverter.

a b c d

a b.c d = a b + c d

a b c d

Fig. 4.5 Logical Equivalent of the AND-OR-INVERT Structure

(V)

EXCLUSIVE-OR Gate 7486

It can be seen that T1 to T6 of this structure is identical to that of the A-O-I Gate and performs the same logical operation. The transistors T7 + T8 and T9 + T10 simply include an inversion on one pair of inputs. The circuit is logically equivalent to the structure shown below. a b

a b + a b = a b = a b EX OR
Fig. 4.6 Logical Equivalent of the Exclusive OR Gate Structure

VCC = 5V INVERTER 7404

RB 4 k R3 130

R1 1.6 k

T4 T2

T1

T3
R2 1k

Fig. 4.7 Schematic Diagram of the 7404 Standard TTL Inverter

VCC = 5V

2-INPUT NAND GATE 7400

R1 RB 4 k 1.6 k

R3 130 T4

T1

T2

T3
R2 1k

Fig. 4.8 Schematic Diagram of the 7400 Standard TTL NAND Gate

VCC = 5V

2-INPUT NOR GATE 7402

4k

4k

1 .6 k

130

T4 T1 T2

T5

T6

T3 1k

Fig. 4.9 Schematic Diagram of the 7402 Standard TTL NOR Gate

VCC = 5V 4k 2x2-INPUT AND-OR-INVERT GATE 7451 T5 4k

1 .6 k 130

T4

T6 D
T2

T1

T3 1k

Fig. 4.10 Schematic Diagram of the 7451 Standard TTL AND-OR-INVERT Gate

2-INPUT EXCLUSIVE OR GATE 7486 VCC = 5V 4k 4k 4k

T1 T2

4k

1 .6 k

130

T4

T7

T8

T5

T6

T3 T9 T10 1k

Fig. 4.11 Schematic Diagram of the 7486 Standard TTL EXCLUSIVE-OR Gate