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AM/FM Software Radio Receiver Implementation in FPGA


Thanh H. Le
could be applied here as radio functions are implemented in software, multiple software modules implementing different standards can co-exist in a handset. An appropriate software module can be chosen to run depending on the network requirements [2]. While there are a variety of hardware platforms for implementing SDR, FPGA is an attractive option due to its performance and configurability. The logic fabric of today's FPGAs is not only made up of look-up tables, registers, multiplexers, distributed and block memory, but also dedicated circuitry for fast adders, multipliers, and I/O processing (e.g., giga-bit I/O) [3]. Furthermore, the memory bandwidth of a modern FPGA far surpasses that of a microprocessor or DSP processor running at clock rates two to ten times that of the FPGA [3]. In addition, FPGA has a capability for implementing highly parallel arithmetic architectures, making it perfectly suited for tasks such as digital filtering, fast Fourier transforms and forward error correction [3]. In this paper, to demonstrate the feasibility of SDR, we present the implementation an FPGA-based software AM/FM radio receiver. II. AM/FM DIGITAL RADIO RECEIVER DESIGN A. SYSTEM OVERALL
Speaker

Abstract This paper describes the implementation of an AM/FM radio receiver in Field Programmable Gate Array (FPGA). Using FPGA as the hardware platform, this approach brings together the flexibility of software and the speed of hardware to build a reconfigurable system, i.e the behaviour of the radio receiver can be changed by simply modifying the software without new hardware. RF modulated signals are digitally sampled and demodulated in real time using digital circuits of the FPGA. To program the FPGA, the receiver structure is described in HDL software which is used to synthesize the system into the FPGA. The design, simulation and initial testing of the AM/FM radio receiver will be presented with emphasis on the concepts and techniques being employed. Index TermsFPGA, SOFWARE RADIO, HDL

I. INTRODUCTION

ecent advancement in semiconductor technology has made it possible to process high speed communication signals in radio systems using as much digital technology as possible. This makes the system very flexible and adaptive. Such a technology is called Software Defined Radio (SDR) [1]. Traditional analog radio receivers and transmitters consist of dedicated analog circuits for filtering, tuning, and demodulating/modulating a specific type of waveform [2]. These hardware based radio systems are inflexible and hard to modify if changes are to be made to its fundamental characteristics such as demodulation/modulation types. To make the system more flexible, SDR technology facilitates implementation of some of these functions in software. This results in reconfigurable software radio systems where changes to its fundamental characteristics can be made simply by modifying the software, whereas a complete hardware based radio system would require hardware modification in order to change these parameters [2]. With its reconfigurability, the potential applications of SDR are numerous. One example is in wireless communication industry, where due to the many communication standards being used around the world, there is a need to build multimode handsets capable of connectivity irrespective of the underlying network technology used [2]. SDR technology

Antenna

Digital Implementation in FPGA


Audio Amplifier
Digital Mixer

A/D

DIgital Low Pass Filter

Digital Demodulation

D/A

Anti-Aliasing Filter

Digital Local Oscillator

Channel Select

Figure 1: System Overview of a Digital AM/FM Receiver

The detailed implementation of the AM and FM receivers are

2 different in term of the sampling techniques and demodulation techniques employed as will be presented in subsequent sections, this section aims to present some general concepts and key components pertinent to both AM and FM receivers. Figure 1 shows the system overview of the Digital AM/FM Receiver being implemented. Radio signals received by an antenna first go through an Anti-Aliasing Filter to remove all signals out of AM/FM bands. This analog filter is necessary in order to avoid aliasing problems in digital implementation. The analog input is then digitized into digital samples by an A/D (analog-to-digital) converter. From this point, all subsequent operations including mixing, filtering and demodulation is done using digital signal processing techniques to extract radio channels of interest. These operations are supported by key components of the digital receiver including Digital Mixer, Digital Local Oscillator, Digital Low Pass Filter and Digital Demodulation. After demodulation, digital samples of radio channels of interest are converted back to analog format using a D/A (digital-toanalog) converter. The radio signal is amplified and played by a loud speak. Digital Local Oscillator The Local Oscillator generates digital samples of a sine (or cosine) wave having the same frequency as that of the desired radio channel. The output frequency of the local oscillator is dependent upon the channel selected by the user. The Local Oscillator produces a sinusoidal sample at exactly every output sample of the A/D converter, therefore it is driven by the same sampling clock of the A/D converter. Digital Mixer The Digital Mixer is simply a 2 inputs multiplier which outputs the product of two digital samples. Digital output samples from the A/D are mathematically multiplied with digital samples of a sine (or cosine) signal from the local oscillator. Note that the input samples from the A/D and sine (cosine) samples from the Local Oscillator are generated at the same rate fs (the sampling frequency of the A/D). The multiplication is sample-by-sample and thus the mixer produces samples at the same rate of fs. Note that unlike analog mixer which produces many unwanted mixer products, the digital mixer only produces the sum and the difference frequency signals [4]. Figure 2 illustrates the effect of mixing RF signal with a local oscillator signal. The mixer shifts the spectrum of the RF portion at the frequency of the local oscillator down to DC level. It should be pointed out here that thanks to the accuracy of the digital multiplication of the mixer, translation right down to 0 Hz is achieved. Therefore by varying the frequency generated by the Local Oscillator, any portion of the RF input signal can be translated down to DC [4].

Mixer translates input signal band to DC

Local oscillator at carrier frequency

Frequency of desired channel

Figure 2: Effect of Mixing Low Pass Filter Once the RF signal has been shifted down to DC level, a low pass filter can be used to filter out unwanted high frequency components. The filter accepts digital samples from the output of the Mixer at the sampling frequency, fs. It employs digital processing techniques to implement an FIR (finite impulse response) filter transfer function. The filter passes all frequencies from 0 up to a cutoff frequency equal to the bandwidth of the message signal of interest, and rejects all frequency above that cutoff frequency.
Filter bandlimits the translated signal

Mixer translates input signal band to DC

Local oscillator at carrier frequency

Frequency of a desired channel

Figure 3: Filtering Figure 3 illustrates the effect of band-limit filtering in the frequency domain. As can be seen, the filter only captures frequencies below its cutoff frequency and rejects all other. Note that the mixer has translated the input signal down to 0 Hz, thus allowing the filter to select only a narrow slice of the RF spectrum corresponding to a channel of interest. B. AM DIGITAL RADIO RECEIVER DESIGN AM band frequency ranges from 526.5 kHz to 1606.5 kHz. To avoid aliasing, the ADC (analog-to-digital converter) needs to sample signal at sampling rate at least twice the highest frequency in the AM spectrum, thus a sampling rate of 4 MHz was chosen for the ADC to allow for some margin. Figure 7 shows the structure of the AM Digital Receiver. As mentioned previously, an ADC is used to digitize the analog

3 signal received from the antenna into digital representation. And in Figure 7, sAM (n) represents the digital samples of the modulated AM signal whose spectrum contains all AM channels. These samples are multiplied with digital sinusoidal samples (cos(2fcn)) of a local oscillator whose frequency is that of the channel of interest. In other words, the frequency of the sinusoidal signal generated by the local oscillator is dependent upon the channel selected by the user. The effect of this multiplication is to shift the spectrum of the AM signal down to DC level so that a low pass filter having a fixed cutoff frequency can be used to pass the baseband message of the radio channel of interest.

fs

2 fs

MHz

DC

22
fs / 2
Baseband alias, DC to 20 MHz

44

66
3 fs / 2

88

110
5 fs / 2

f s = 44 MHz

FM signal 88-108 MHz

sAM (n)

g(n)
LPF

s(n)baseband

Figure 4: Undersampling, FM signal from 88-108 MHz is aliased between DC and 20 MHz by sampling at 44 MHz

Literature suggests a technique called Undersampling, which only samples signal at about twice its bandwidth (not twice the highest frequency in the signal). This technique In digital sample representation, we have: applies for signals which do not extend to DC (bandpass signals), and for such signals the minimum sampling rate depends on the bandwidth of the signal as well as its position s AM = Ac [1 + am( n )] cos(2f c n ) in the frequency spectrum [9]. The sampling rate fs is chosen Ac g(n) = Ac [1 + am(n)]cos(2f cn) * cos(2fcn) = [1 + am(n)][cos( (2 fc )n) +such that the entire band of the bandpass signal lies within a 2 1] 2 single region of length fs/2, not multiples of fs/2. Figure 4 Ac Ac illustrates this technique by considering the FM signal (88 = [1 + am(n)] + [1 + am(n)]cos(2 (2 fc )n) 2 2 MHz to 108 MHz) being sampled at 44 MHz. For fs = 44 MHz, the entire FM band lies within 2 fs and 5 fs /2

cos(2f c n)

The low pass filter after the mixer is design to remove all but the baseband signals. Consequently, the output of the demodulator will be

s ( n ) baseband =

Ac [1 + am( n )] 2

which has an AC component proportional to the baseband message signal m(n ) . Thus we have successfully demodulated the AM signal. C. FM DIGITAL RADIO RECEIVER 1) Sampling Rate Consideration, Undersampling Technique Since FM spectrum has the highest carrier frequency at 108 MHz, to satisfy Nyquist criterion, the signal must be sampled at around 216 MHz to avoid aliasing. However, this sampling rate is too fast for current ADCs technology (the ADS807 used in this project has maximum sampling rate of 53 MHz). Therefore, unlike the AM Receiver, for the FM Receiver, due to the high frequency signal, a different approach to sampling is needed.

After sampling, the actual FM signal between 88 an 108 MHz is aliased around multiples of fs . Notice that any one of the alias components is an accurate representation of the original signal. In particular, the component lying in the baseband region from DC to 20 MHz is the output spectrum from the ADC, and is also the accurate representation of the original signal. In summary, the effect of undersampling is shifting the original spectrum down to baseband level, while keeping the frequency content of the signal intact. As a result of undersampling at 44 MHz, all carrier frequencies in the FM signal are now shifted down to baseband by an amount of 88 MHz. Therefore, the original carrier frequencies at 88.1, 88.3, 107.9 MHz now appear at 100 kHz, 300 kHz, 19.9 MHz in the sampled data of the ADC. It can be observed that the effect of undersampling is very similar to mixing, when the FM signal is undersampled, its frequencies are aliased into baseband (the first Nyquist zone from 0 to fs/2) as if they were in the baseband originally. 2) FM Phase-locked Loop Demodulator A Phase-Locked Loop (PLL) can be used to demodulate a FM modulated signal. The PLL is a feedback loop that is commonly used in analog demodulation of FM signal. Based on the original development in [6] of a Phase-lock loop for

4 FM demodulator in continuous time domain, we have transferred this into an equivalent PLL demodulator in discrete time domain (suitable for digital implementation) as presented below. Figure 5 shows the block diagram of a Phase-Locked Loop. FM modulation embeds the baseband message in the variation of the frequency. The idea of a PLL is that with the help of a feedback loop, the controlled frequency should follow the reference frequency. The controlled frequency in this case is the output signal (demodulated signal), and the reference frequency is the FM modulated signal. The Phase Comparator compares the output of the Voltage Controlled Oscillator (VCO) with the reference signal to produce an output consisting of the phase difference. This output forces the phase of the VCO to move closer to that of the reference signal. When the system settles down, the VCO is basically locked onto the reference signal.
Received Signal Output Signal

Ac cos(2f c n + ( n ))
FM received signal

g(n)
LPF

e(n)

-1

Av sin( 2f c n + v ( n ))
Output of VCO

Figure 6: Phase Comparator Structure The phase comparator (Figure 6) is basically a multiplier and a Low Pass Filter (LPF). The multiplier mixes the incoming FM modulated signal with the VCO signal to produce an output consisting of baseband component and a high frequency component (centered at 2 fc ). The LPF passes only the baseband component and rejects all high frequency components. (The design of this filter will be described separately in the next section). In Figure 15, mathematically, we have

Phase Comparator

Loop Filter G(f)

g ( n ) = Ac cos( 2f c n + ( n )) Av sin(2f c n + v ( n )) = 1 Ac Av [ sin( ( n ) v ( n )) + sin( 2 ( 2 f c )n + ( n ) + v ( n ))] 2 Hence 1 Ac Av sin( ( n ) v ( n )) 2

VCO

e( n ) = ( 1) g ( n ) hLPF ( n ) =

Figure 5: Block diagram of Phase-Locked Loop FM Demodulator

where the difference

( n ) v ( n ) = e ( n ) is

the phase

Analysis of a PLL Demodulator in discrete time domain


The reference signal is the FM modulated signal

error. Let assume that the PLL is in lock, and thus

v (n ) is

very close to (n ) . In that case, the phase error is very small and

sin( ( n ) v ( n )) ( n ) v ( n ) = e ( n )
(n)
+

s FM ( n ) = Ac cos(2f c n + ( n ))

e (n)

The VCO generates a sinusoidal of a fixed frequency, in this case the carrier frequency fc, in the absence of an input control voltage. The voltage control to the VCO is the output of the loop filter (the demodulated signal), denoted as v(n). Thus the instantaneous frequency of the VCO is

Loop Filter G(f)

v(n )

v (n )

f v = f c + k v v (n )
where kv is a deviation constant. Therefore, the VCO output may be expressed as y v ( n ) = Av sin( 2f c n + v ( n )) (2.1) where
Figure 7: Linearized PLL Model

2kv v(i )
i =0

n 1

v ( n ) = 2k v v (i )
i =0

n 1

Under this condition, we can approximate the PLL in Figure 5 by a linearized model in Figure 7. We can write the phase error as

e ( n ) = ( n ) 2k v v (i )
i =0

n 1

(2.2)

Differentiate (2.2) in discrete time domain, we have

e ' ( n ) + 2k v v ( n ) = ' ( n )

e ' ( n ) + 2k v

k =

(k ) g (n k ) = ' (n )
e

(2.3)

AM Filter Fpass = 3 kHz Fstop = 4.5 kHz Apass = 3 dB Astop = 30 dB

FM Filter Fpass = 90 kHz Fstop = 100 kHz Apass = 3 dB Astop = 30 dB

Taking the Discrete Fourier transform of (2.3) and, hence,

( j 2f ) e ( f ) + 2k v e ( f )G ( f ) = ( j 2f ) ( f )
e ( f ) = 1 k 1 + v G( f ) jf ( f )

The corresponding equation for the control voltage to the VCO is

V ( f ) = e ( f )G ( f ) =

G( f ) ( f ) kv 1+ G( f ) jf
(2.4)

In designing the FIR filter, we seek to minimize the filter order (or number of filter taps) while satisfying requirements specified above. FIR filter theory states that the filter order is approximately proportional to the input sampling frequency and inversely proportional to the width of the transition band. That is the higher the input sampling frequency, the higher the filter order, and the narrower the transition band, the higher the filter order. Filter order

Suppose that we design G(f) such that

Fs Fs = given that F Fstop F pass

kv G ( f ) >> 1 jf
j 2f ( f ) 2k v

passband ripple and stopband attenuation are kept fixed [7]. (2.6) For AM receiver the FIR filter specified above, Fs = 4000 kHz (sampling rate of the ADC), Fpass = 3 kHz and Fstop = 4.5 kHz, thus using the above approximation, the number of filter taps required would be 4000/(4.5-3) = 2670.This number of taps is astronomically large due to very high input sampling rate and the narrow transition band. Therefore, a single FIR filter satisfying our requirements would be impossible to be realized in hardware. However, close observation reveals that since the output of the filter is a baseband message of bandwidth around 4 kHz, the output sample rate needs not be maintained at 4000 kHz, but could be reduced to around twice the bandwidth of the baseband message (about 8 kHz) just to satisfy the Nyquist theorem. This fact allows us to employ a common strategy of multistage filtering to reduce the number of filter taps. This technique suggested in [8] is illustrated in Figure 8. The single stage Filter of very high order is replaced by a chain of N stages of smaller order filters and downsample operations. At each stage, the cutoff frequency of the filter is at the desired cutoff frequency of the original single filter, but its stopband frequency is set at half the new sampling rate (to the next stage).Therefore, the filter at each stage has lower input sample rate and broader transition band, resulting in a much smaller number of taps at each stage.
A single stage Filter of very high order

in the frequency band f < W of the message signal. V(f) can be approximated by

V( f ) =

or equivalently,

v(n) =

k 1 ' ( n ) = f m( n ) 2k v kv

(2.5)

which is proportional to the original message signal. Hence v(n) is the demodulated signal. Note that in this project we decided to replace the loop filter response G(f) by a constant for resource saving, the value of the constant is large enough such that condition (2.4) is satisfied. Simulation shows that G = 2 and kv = 5000 give best performance (for a typical value kf = 50000 in FM broadcasting). D. MULTISTAGE FILTERING TECHNIQUE For both AM and FM receivers, the Low Pass Filter (LPF) plays a critical role in isolating adjacent channel interferences, and thus minimizing the noise at the output. The bandwidth of an AM channel is 9 kHz, thus a LPF having passband from 04.5 kHz is desired, whereas the bandwidth of FM channel is 200 kHz, thus the filter should have passband from 0-100 kHz. The following table shows the summary of filter requirements for AM and FM receivers.

FIR

An equivalent N-stage Filter of significantly reduced order

fin

FIR 1
Low order filter

M1
Down sample by factor M1

FIR 2
Low order filter

M2
Down sample by factor M2

.......

f out

FIR N
Low order filter

MN
Down sample by factor MN

Figure 8: Multi-stage Filtering

Consider the fundamental case (Figure 9) where at each stage, the sampling rate is reduced by a half (a factor of 2), let fin be the input sampling rate (to the first stage), and fout be the desired output sampling rate (of the last stage), then

Thus the maximum number of taps (when stage k can be written as

fc =

f in ) for 2 N +1

fout =

hence the number of stages is given by

fin , 2N

N = log 2 (
fin

f in ) f out
fin / 2

(2.7)
fin / 4
fin / 2 N

f in / 2 k 1 f / 2 k 1 4 = = M k = in f in f in 1 f in 1 fc 2 N k 2 k +1 2 N +1 2 k +1
(2.10) Examining expression (2.10), we can see that the number of taps for stage k is approximately 4 if

FIR 1
Low order filter

2
Down sample by factor 2

FIR 2
Low order filter

2
Down sample by factor 2

.......

FIR N
Low order filter

2
Down sample by factor 2

f out

1 is small. In fact 2 N k

M k 4 for

Figure 9: N-stage Filter with down-sample by a factor of 2 at each stage

1 0.2 2 N k

Let fc be the cutoff frequency of all the filters in the chain, noting that fc is our designed cufoff frequency for the original single stage high order filter. The stopband frequency of the filter in each stage is set at half the new sampling rate for the next stage. Table shows details of the cutoff and stopband frequency for each filter in the chain. Table 1: N-stage Filter Design Filter Cutoff frequency FIR 1 FIR 2 FIR 3 FIR k fc fc fc fc

(2.11) Hence M k 4 (for k N 3 ) In other words, the estimated filter order for the first (N-3) stages of the N-stage filter is 4(N-3). Therefore, the total number of filter taps in the N-stage filter (2.8) can be rewritten as

M 4( N 3) + M N 2 + M N 1 + M N 4 1 1 2 N ( N 2) + 4

= 4( N 3) +
Stopband frequency fin/4 fin/8 fin/16 fin/2k+1

1 1 2 N ( N 1)

+ MN

= 4( N 3) + 5 + 8 + M N = 4N + 1 + M N
(2.12) With MN in (2.10) is the filter order of the last stage, which can be estimated to be about 10, depending on the actual value of fc relative to fout. Therefore, we have shown that the total number of taps of the N-stage filter is approximately given by

Using the approximation (2.6), we can estimate the total number of filter taps (denoted M) required in this case as follow f / 2 k 1 f /4 f /2 f in + in + in + + in M = f in f in f in f in fc fc fc fc 4 8 4 2 k +1
(2.8)

f M 4 N = 4 log 2 ( in ) f out

(2.13)

As mentioned previously, for applications of this type, the output sampling rate of the filter could be reduced to just above twice the bandwidth of the baseband message (to satisfy Nyquist Theorem). Therefore,

f f out = in 2 f c 2N f f c in N +1 2

Hence (2.9)

Compare (2.13) with the estimate of the number of filter taps for the single filter (2.6), it can see seen that the N-stage filter has dramatically reduced the number of filter taps. In fact, the filter order of the N-stage filter is of logarithmic order of the input sampling rate whereas the order of the single stage filter is the order of the input sampling rate. In other words, we can draw a very important conclusion below A N-stage filter achieves a reduction in the number of filter taps by a factor of (Fs/(4*log2Fs) compared to a single stage filter. Where Fs is the input sampling rate of the input data. (2.14) Return back to the design of the filter for the AM Digital Receiver, the input sampling rate is 4000 kHz and the baseband message is of 4 kHz bandwidth, therefore we

7 decided to reduce the output sampling rate to around 15 kHz to allow for some margin. The number of stages of a N-stage filter would be N = log2(4000/15) = 8, wherein the sampling rate is reduced by a factor of 2 at each stage as discussed above. Table 2 summarizes the design. Table 2: A 9-Stage Filter for AM Digital Receiver Filter Stopband Stage Sampli Passband frequency frequency Order ng Fs (kHz) freque (kHz) M= Fstop Fpass ncy (kHz) 1 4000 0-4 1000 and 4 above 2 2000 0-4 500 and 4 above 3 1000 0-4 250 and 4 above 4 500 0-4 125 and 4 above 5 250 0-4 62.5 and 4 above 6 125 0-4 31.25 and 5 above 7 62.5 0-4 15.625 and 6 above 8 31.25 0-4 7.8125 and 9 above 9 15.625 0-3 4.5 and 11 above 51 Total number of filter taps required Note that an extra stage (stage 9) is added to fine-tune the transition bandwidth of the overall filter to meet the 3 kHz to 4.5 kHz requirement as described earlier. The total number of filter taps required is only 51 taps, which is an enormous reduction compared to the 2670 taps required if a single stage filter was used.

Table 3: an 8-Stage Filter Design for FM Receiver Stage Samplin g frequenc y (kHz) 44000 Passban d frequenc y (kHz) 0-90 Stopband frequency (kHz)
Filter Order

M=

Fs Fstop Fpass

1 2 3 4 5 6 7 8

11000 and above 5500 above 2750 above 1375 above and and and

4 4 4 4 5 6 9 18 54

22000 11000 5500 2750 1375 687.5 343.75

0-90 0-90 0-90 0-90 0-90 0-90 0-80

687.5 and above 343.75 and above 171.875 and above 100 above and

Total number of filter taps required

III. FPGA IMPLEMENTATION A. Hardware Model Construction To implement the system in FPGA, it is necessary to describe our design models developed above in Hardware Description Language (HDL). The software can then be used to synthesize the design into the FPGA platform. In this project, we chose not to describe our design directly in HDL, but used a system level tool called Xilinx System Generator software to speed up the development cycle. This tool allows us to describe the design in high level abstraction and the tool automatically maps the system to a faithful hardware implementation. It allows us to model a system graphically from a set of common signal processing blocks such as adder, multiplier, filter etc. In addition, System Generator automatically produces command files for FPGA synthesis, HDL simulation, and implementation tools, so that the user can work entirely in graphical environments in going from system specification to hardware realization [7].

Similar to AM filter, multi-stage filtering technique is utilized to build the FM filter. The input sampling rate is 44 MHz, the bandwidth of the baseband message is about 100 kHz, and thus the output sampling rate is reduced to about 350 kHz. Therefore the number of stages = log2(44000/350) = 7, at each stage the sampling rate is reduced by a factor of 2. Table 3 summarizes the design. Again, the number of filter taps is only 54, which is an enormous reduction compared to an estimate of 44000/(10090) = 4400 taps required if a single filter was used.

1 From ADC output

dbl

fpt

xlregister d z-1 q InReg

Gateway In1

a xlmult (ab) b z-2 Mixer

In1

Out1

fpt

dbl

1 To DAC Input

Gateway Out Low Pass Filter

2 Channel Selection Input

dbl

fpt

xlregister d z-1 q InReg1

In1

Out1 Sy stem Generator

Gateway In2

Local Oscillator

Figure 10: Hardware Model of the AM Receiver Figure 10 shows the AM receiver model constructed in Xilinx System Generator. As can be seen, using System Generator, the receiver design can be built from common signal processing blocks such as filter, multiplier, adder, etc. These blocks can be parameterized to suit the task at hand. The number of bits to be used in hardware implementation can also be specified. After constructing the model, the model can be simulated in Simulink environment to evaluate system performance before testing in actual FPGA hardware. B. Hardware Model Simulation A great advantage of using Xilinx System Generator is that the hardware model constructed above could be simulated in Simulink using all the flexibility and convenient facilities provided by Matlab and Simulink. Since the models constructed from Xilinx Blocks behave in exactly the same way in Simulink as they do in hardware, this simulation gives us a good indication of the system performance in actual hardware. Also, System Generator allows us to specify the number of bits to be used for digital implementation at key points in the design (such as at the Gateways from the outside world). This facility enables us to experiment with different level of fixed precision used in hardware implementation, and choose a value which does not sacrifice significant system performance (compared to the double precision system) while resulting in a hardware efficient system. To choose a suitable number of bits for digital hardware realization, the hardware model was tested with input message is a sinusoidal signal of 3 kHz at three level of fixed point precision: 8 bit, 12 bits and 16 bits used for data representation. Figure 11 shows a) the input spectrum, b) the output spectrum at 8 bits, c) the output spectrum at 12 bits, and d) the output spectrum at 16 bits. As can be seen, at 8 bitprecision, the output signal contains high level of noise (due to quantization noise), while at 12 and 16 bit-precision, the noise level is negligible. Close observation of the output spectrums shows that using 16 bits arithmetic offers no further improvement compared to using 12 bits arithmetic. Using 16 bit-precision would cost more hardware resources, and thus the 12 bit- precision was chosen as the most suitable implementation.

Figure 11: Hardware AM Receiver Test with different level of fixed point precision.

9 The hardware model was also tested with other types of input message. To evaluate the frequency response of the system, a Chirp signal (from 300 Hz to 4 kHz) was applied. Figure 12 shows a) the spectrum of the input Chirp signal and b) the spectrum of the output Chirp signal. As evident, the system shows good frequency response for all frequency in a typical voice message from 300 Hz up to 4 kHz. record message of the word matlab. Figure 13 shows a) the spectrum of the voice input, b) the spectrum of the demodulated output, and c) the time plot of the input (top) and output (bottom). Listening to the input and output message on the computer speaker indicates that the demodulated message resembles very closely the input message with very negligible background noise.

Figure 12: Hardware AM Receiver Test with Chirp input signal from 300-4000 Hz

c)

Figure 13: Hardware AM Receiver Test with a voice record message of the word matlab

And finally, the system was tested with a 0.5 second voice

10 IV. EXPERIMENTAL TESTING This chapter presents the preliminary testing of our design in actual FPGA hardware. Due to time constraints, testing was only done for the AM Receiver system and was just an initial testing. A comprehensive testing of the designed AM and FM Receivers should be the next step for those who continue working on this project. The testing was done using a Virtex-II Pro FPGA Development Board. The board has all the basic hardware required for this project, including a Virtex-II Pro FPGA chip, an ADC (analog-to-digital converter), and a DAC (digital-toanalog converter).The procedure for testing the design in actual FPGA hardware is as following. 1. First, the hardware model as presented in Chapter 5 should be configured to have its input and output ports properly connected to the appropriate pins of the FPGA chip. This includes connection of the data input port to the output of the ADC, the channel selection input port to the 8 user switches, and the output port to the input of the DAC. This could be done from Xilinx System Generator by specifying the pin name in the Gateway in and Gateway out blocks in the hardware model. 2. Next, VHDL software targeted into the FPGA platform (in this case is a Virtex-II) is generated from the hardware model using Xilinx System Generator tool. 3. The input to the ADC could come from a Signal Generator configured to generate an AM (or FM) modulated signal. 4. The output from the DAC is the demodulated message, and thus could be connected to an Oscilloscope for viewing purposes. A comprehensive testing would involve the connection of an antenna to the input of the ADC with through an Anti-aliasing filter. The output of the DAC would be connected to a power amplifier and fed to a loud speaker. V. CONCLUSION In this project, we have looked into the concepts and design techniques of a new digital technology called Software Defined Radio by implementing an AM/FM Digital Radio Receiver in software running on a FPGA platform. We have developed two models for demodulating AM and FM signals, respectively, using all digital circuit technology right from the antenna. Simulation of our models using both double precision and fixed precision has shown that the general concepts and techniques of software radio are feasible in general and in particular to the implementation of an AM/FM radio receiver. The two most important findings in this project are the use of multistage filtering technique to reduce the filter order, and the use of undersampling technique to lower the sampling rate requirement for the ADC. Firstly, in applying multistage filtering technique, we have mathematically formulated a formula for estimating the total filter order in an N-stage filter. We also proved mathematically that compared to single stage filtering, multistage filtering reduces the number of filter taps approximately by a factor of (Fs/4log2Fs) where Fs is the sampling rate of the filter input data. Secondly, in employing undersampling technique for our FM receiver, we have confirmed that it is a powerful technique for lowering the sampling rate requirement for the ADC, and thus lowering the computational requirements for the entire system (e.g. lowing filter taps requirements). Undersampling can be an extremely valuable tool, especially for designing receivers operating at high frequency spectrum. Due to the scope of this project, only preliminary testing of the designed system in FPGA was carried out. Therefore, the most important future work extending on from this project would have to be a comprehensive testing of the designed system. All software required for testing the AM and FM receiver in actual FPGA have been developed in this project, ready to be synthesized into the targeted FPGA. Of particular note to individual pursuing the testing phase of this project is the design of Anti-aliasing filters, which for our AM receiver system should have a passband from 0-2 MHz, whereas for our FM receiver system, the filter should be a bandpass analog filter with passband from 88-108 MHz. These filters should ideally be high order analog filters with large stopband attenuation. Finally, from our experience during the initial testing phase of this project, a good advice to students continuing this project is that it is important to get all the necessary hardware components ready at the beginning of the year so that experimental testing can be carried out at the end of the development cycle. These include an AM/FM antenna with a suitable matching circuit to 50 Ohm input of the ADC, two anti-aliasing filters as mentioned above, a low noise audio amplifier and a loud speaker.

REFERENCES
[1] S. Haruyama, 2000, Software-defined radio Technology, Chapter 6, www.csl.sony.co.jp/ATL/papers/ Haruyama_Kluwer_book_chapter6_2000.pdf [2] Software-Defined Radio, a Technology Overview, 2002, Wipro Technologies, [3] www.broadcastpapers.com/broadband/WiproSDRadio.pdf [4] Xilinx System Generator v2.1Reference Guide, www.mathworks.fr/applications/dsp_comm/xilinx_ref_guide.pdf [5] R.H. Hosking, Digital Receiver Handbook: Basic of Software Radio, Pentek Inc., www.pentek.com/products/GetLit.CFM/ DgtlRcvrHbk43.pdf?Filename=DgtlRcvrHbk43.pdf [6] J.G. Proakis, 1994, Communication Systems Engineering, PrenticeHall Inc., New Jersey 07458 [7] P. Cooke, 2002, Noise and Modulation in Communication Electronics, National Library of Australia [8] K. Anderson & R. Supangat, 2003, Final year Report, University of Adelaide. [9] D. Gray, Signal Processing IV Course Notes, Department of Electrical and Electronic Engineering, University of Adelaide

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[10] W. Kester, Undersampling Application http://www.analog.com/UploadedFiles/Associated_Docs/533275342249 532163524457Section5.pdf

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