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Serial Adder Example

Block Diagram of a Serial Adder (p520)
A a Shift register Adder FSM Shift register b Sum = A + B B Clock s Shift register

Figure 8.39
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State Diagram for the Serial Adder

Reset
( ab s )

11 0 00 0 01 1 10 1 01 0 10 0 11 1

G 00 1 G: carry-in = 0 H: carry-in = 1

Figure 840
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State Table for the Serial Adder

Figure 841
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State-assigned Table for the Serial Adder

Figure 842
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Circuit for the Adder FSM

a b

s Full adder Y
carry-out

Q Q

Clock Reset
Figure 8.43
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State Diagram for the Moore-type Serial Adder FSM

Figure 8.44

G0: sum = 0, carry = 0; G1: sum = 1, carry = 0; H0: sum = 0, carry = 1; H1: sum = 1, carry = 1;
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State Table for the Moore-type Serial Adder FSM

Figure 8.45
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State-assigned Table for the Moore-type Serial Adder FSM

Figure 8.46
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Circuit for the Moore-type Serial Adder FSM

Figure 8.47
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Code for a Left-to-right Shift Register With an Enable Input

module shiftrne (R, L, E, w, Clock, Q); parameter n = 8; input [n-1:0] R; input L, E, w, Clock; output [n-1:0] Q; reg [n-1:0] Q; integer k; always @(posedge Clock) if (L) Q <= R; else if (E) begin for (k = n-1; k > 0; k = k-1) Q[k-1] <= Q[k]; Q[n-1] <= w; end endmodule
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Figure 8.48
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Serial Adder Logic Diagram

Figure 8.50
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Verilog Code for the Serial Adder

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Figure 8.49

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Finite State Machine Optimization

State minimization
Fewer states require fewer state bits Fewer bits require fewer logic equations

Encodings: state, inputs, outputs

State encoding with fewer bits has fewer equations to implement
However, each may be more complex

State encoding with more bits (e.g., One-hot) has simpler equations
Complexity directly related to complexity of state diagram

Input/output encoding may or may not be under designer control

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Algorithmic Approach to State Minimization

Goal identify and combine states that have equivalent behavior Equivalent states:
Same output For all input combinations, states transition to same or equivalent states

Algorithm sketch
Place all states in one set Initially partition set based on output behavior Successively partition resulting subsets based on next state transitions Repeat until no further partitioning is required
States left in the same set are equivalent

Polynomial time procedure

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Example 8.6

Figure 8.51
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Minimized State Table for Example 8.6

P5 = (AD)(B)(CEG)(F)

Figure 8.52
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Vending Machine Example 8.7

(p532)

Suppose that a coin-operated vending machine dispenses candy under the following conditions:
The machine accepts nickels and dimes. It takes 15 cents for a piece of candy to be released from the machine. If 20 cents is deposited, the machine will not return the change, but it will credit the buyer with 5 cents and wait for the buyer to make a second purchase.

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Signals for the Vending Machine

Clock sense N sense D N D

(a) Timing diagram

N sense N Clock D Q Q D Q Q

Figure 8.53 (b) Circuit that generates N

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State Diagram for Example 8.7

Figure 8.54
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State Table for Example 8.7

Figure 8.55
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Minimized State Table for Example 8.7

Figure 8.56
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Minimized State Diagram for Example 8.7

Figure 8.57
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Mealy-type FSM for Example 8.7

Figure 8.58
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Incompletely Specified State Table

Example 8.8 (p537)
Both unspecified outputs have a value of 0:

Both unspecified outputs have a value of 1:

Figure 8.59
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Implication Chart Method

Construct implication chart, one square for each combination of states taken two at a time. Square labeled Si, Sj, if outputs differ than square gets X, otherwise write down implied state pairs for all input combinations. Advance through chart top-to-bottom and left-to-right. If square Si, Sj contains next state pair Sm, Sn and that pair already labeled X, then Si, Sj is labeled X. Continue above step till no new squares are Xed. For each remaining unmarked square Si, Sj, then Si and Sj are equivalent.

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Example

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Minimizing Incompletely Specified FSMs

Equivalence of states is transitive when machine is fully specified. But its not transitive when don't cares are present. e.g., state S0 S1 S2 output 0 S1 is compatible with both S0 and S2 1 but S0 and S2 are incompatible 1

No polynomial time algorithm exists for determining best grouping of states into equivalent sets that will yield the smallest number of final states .
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State Assignment
Choose bit vectors to assign to each symbolic state
With n state bits for m states there are 2n! / (2n m)! [log n <= m <= 2n] 2n codes possible for 1st state, 2n1 for 2nd, 2n2 for 3rd, Huge number even for small values of n and m
Intractable for state machines of any size Heuristics are necessary for practical solutions

Optimize some metric for the combinational logic

Size (amount of logic and number of FFs) Speed (depth of logic and fanout) Dependencies (decomposition)

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State Assignment Strategies

Possible strategies
Sequential just number states as they appear in the state table Random pick random codes One-hot use as many state bits as there are states (bit=1 > state) Output use outputs to help encode states Heuristic rules of thumb that seem to work in most cases

No guarantee of optimality another intractable problem

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One-hot State Assignment

Simple
Easy to encode Easy to debug

Small logic functions

Each state function requires only predecessor state bits as input

Good for programmable devices

Lots of flip-flops readily available Simple functions with small support (signals its dependent upon)

Impractical for large machines

Too many states require too many flip-flops Decompose FSMs into smaller pieces that can be one-hot encoded

Many slight variations to one-hot

One-hot + all-0

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Heuristics for State Assignment

Adjacent codes to states that share a common next state To group 1's in next state map

Adjacent codes to states that share a common ancestor state To group 1's in next state map

Adjacent codes to states that have a common output behavior To group 1's in output map

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General Approach to Heuristic State Assignment

All current methods are variants of this
Determine which states attract each other (weighted pairs) Generate constraints on codes (which should be in same cube) Place codes on Boolean cube so as to maximize constraints satisfied (weighted sum)

Different weights make sense depending on whether we are optimizing for two-level or multi-level forms Can't consider all possible embeddings of state clusters in Boolean cube
Heuristics for ordering embedding To prune search for best embedding Expand cube (more state bits) to satisfy more constraints

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Output-based Encoding
Reuse outputs as state bits - use outputs to help distinguish states
Why create new functions for state bits when output can serve as well Fits in nicely with synchronous Mealy implementations

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Current State Assignment Approaches

For tight encodings using close to the minimum number of state bits
Best of 10 random seems to be adequate (averages as well as heuristics) Heuristic approaches are not even close to optimality Used in custom chip design

One-hot encoding
Easy for small state machines Generates small equations with easy to estimate complexity Common in FPGAs and other programmable logic

Output-based encoding
Ad hoc - no tools Most common approach taken by human designers Yields very small circuits for most FSMs

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State Assignment Summary

There are 6,720 different state assignments of 5 states to 3 variables.
And there are even more using 4 or more variables

Here are a few obvious or interesting ones:

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FSM As An Arbiter Circuit

The purpose of the machine is to control access by various devices to a shared resource in a given system. Only one device can use the resource at a time. Assume that all signals in the system can change values only on the positive edge of the clock signal. Each device provides one input to the FSM, called a request, and the FSM produces a separate output for each device, called a grant. A device indicates its need to use the resource by asserting its request signal. Whenever the shared resource is not already in use, the FSM considers all requests that are active. Based on a priority scheme, it selects one of the requesting devices and asserts its grant signal. When the device is finished using the resource, it deasserts its request signal.
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State Diagram for the Arbiter

Figure 8.72
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Figure 8.73

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Verilog Code for the Arbiter

Figure 8.74
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Example 8.12

Figure 8.90 Figure 8.89

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Example 8.12
Figure 8.90

Figure 8.91

Figure 8.92

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Example 8.13

Figure 8.16

Figure 8.3 Detecting 1s

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Example 8.13

Figure 8.93 Detecting zeros Figure 8.3 Detecting 0s

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Example 8.14

Figure 8.96 Figure 8.94

Figure 8.95
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Example 8.15

Figure 8.92

Figure 8.97

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Example 8.16
module sequence (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [3:1] y, Y; parameter [3:1] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100; // Define the next state combinational circuit always @(w, y) case (y) A: if (w) Y = D; else Y = B; B: if (w) Y = D; else Y = C; C: if (w) Y = D; else Y = C; D: if (w) Y = E; else Y = B; E: if (w) Y = E; else Y = B; default: Y = 3'bxxx; endcase

Figure 8.89

// Define the sequential block always @(negedge Resetn, posedge Clock) if (Resetn == 0) y <= A; else y <= Y; // Define output assign z = (y == C) | (y == E); endmodule Figure

8.98
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Example 8.17

Figure 8.94

Figure 8.99

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Example 8.18

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Example 8.18

Figure 8.100
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Example 8.18

Figure 8.101
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Parity Generation and Checking

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