ADPCM-HCO

PS-IP PS IP Product Brief

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ADPCM Voice Compression logic Core

(HCO) High Channel-count optimized Description
The Pinpoint Solutions Inc, ADPCM-HCO is a hardware optimized CMOS soft logic core, designed to perform the task of large-scale voice compression as a co-processing system element. The design is a unique realization of the G.726 algorithm that allows for a very high channel count up to 672 full duplex channels may be processed by the core. The product supports the ADPCM standard for digital voice compression as defined in the ITU-T G.726 specification. The true benefit of using the core is to significantly reduce transport or storage bandwidth requirements. The core is designed to offload the internal voice processing tasks from RISC or DSP centric architectures. Flexibility is key to the usage of this core for final implementation as an ASIC, FPGA or element in a SOC design.
SD_out [13:0] Data Out I/O Interface Control S_in [13:0] Data In DECODER Engine channel [10:0] CH # SEL enable code[2:0] decode law [1:0] algo_reset reset_n timer [2:0] clk
I/O COMMAND & CONTROL Encode/Decode

Block Diagram
ENCODER Engine RAM 1 Nx6x24 RAM 2 Nx6x24 RAM 3 Nx6x24 ADPCM-HCO ASIC/FPGA Example Implementation RAM 4 Nx6x24 RAM 5 Nx6x24 RAM 6 Nx6x24

PCM to ADPCM ADPCM to PCM

COMPRESSION "State" RAM DECOMPRESSION Interface STATE MACHINE

HOST INTERFACE LOGIC

Note: PSI does not supply the RAM "IP" elements. See memory requirements in the data sheet.

Product features:
Processes 1 to 672 full duplex, 1344 half duplex voice channels. Simple synchronous bus interface. No register based configuration or core setup is required. Sequential channel processing, addressed channel operation. Channel by channel, frame by frame encode/decode, and code format. Implements ITU-T G.726 specification. (32, 24, 16 fixed rate codes) A-law, -law, Linear code format selection on a per channel basis. Single cycle encoding/decoding of voice samples

Key Benefits of Implementation:

FPGA or ASIC Implementation. Lower power consumption. Scaleable channel count design. Reduced board space. Cost reduction (per channel associated cost). DSP/CPU Task offloading.

Applications:
(IAD) Integrated Access Devices. Voice/Data multiplexers. Channel Bank Voice Concentrators. Voice over IP/DSL (Packet/Cell/Frame) Voice Storage (selected record and playback). Wireless: DECT and Cellular. Voice Gateways. Videoconferencing. (SOHO) Small Office Home Office. DSL Modems. Cable Modem. (CO) Central office equipment. DSLAM. Cable Modem Head End equipment. Large scale Voice Concentrators. Computer Telephony Integration. Voice mail. WAN voice processing. PBX (Private Branch Exchange).

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ADPCM-HCO

PS-IP PS IP Product Brief

________________________________________________________________________ Specifications: Deliverables

Host Interface: Synchronous parallel Internal Ram requirements per channel: Nx6x24 bits per half-duplex channel Operating frequency: 43.008MHz processing 672 channels (336 full-duplex) 86.016MHz processing 1344 channels (672 full-duplex) Standards compliance: ITU-T G.726, (Optional G.727) Compression code rates: 32, 24, 16Kbs

Test bench for the logic core, and control scripts to run Verilog simulations to exercise the ITU standard vectors for the all G.726 rates. Primetime script/shell for verifying timing of the core. Synthesis script/shell to assist in synthesis of the core. Test bench core coverage analysis document. Verilog RTL soft-logic core.

Integrated Access Device (Voice / Data Multiplexer) Using the ADPCM-HCO

Location A
672 Voice Channels
1 4 7 * 2 5 8 8 3 6 9 #

Location B

672 Voice Channels

1 4 7 * 2 5 8 8 3 6 9 #

Voice Resources
HEWLETT PACKARD

T3 (45Mbs)

WAN Services (Frame-Relay) (ATM) (Channelized)

Voice Resources
HEWLET T PACKARD

T3 (45Mbs)
22.5Mbs Data pipe DATA Resources

22.5Mbs Data pipe DATA Resources

*Note: Application based on 32Kbps voice algorithm.

PSI Reference Documents

ADPCM-HCO Data sheet Application notes White papers

Product Information
Upon request, PSI will provide complete quotation for this product including: pricing, deliverables list, and licensing agreements.

Options core include:

Scalable encoding/decoding channel counts. Auto-channel Processing mode. Logic BIST Custom Interface options. FPGA specific targeting. Asynchronous bus interface. VHDL testbench. ITU-T G.727 support.

Pinpoint Solutions. Inc. 5171 Eldorado Springs Drive Boulder, CO 80303 Tel: 303.543.0050 Fax: 303.494.5769 HTTP:\\ www.asic-design.com
Product Information Requests:

mailto:IP-info@asic-design.com

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