NAME: _________ SID #: _________

EEE 333, ASU

Fall 2009, David R. Allee
Final
15 December 2009, 12: 10Plll to 2:00Plll
Open Book, Open Notes,
No Electronic Instruments

NAME: ________
(LAST) (FIRST)
SID#: ________________________________
Problem 1: (20) __________
Problem 2: (20) ______________
Problem 3: (20) __________
Total (60)
EEE 333: Fall 2009, Final
NAME: ___ ___ SID #: ___________
Problem 1: Delay Models (20 points): Sketch the timing waveforms for Sand Y for the following
snippets of VHDL code. Carefully label the time of any delays. Mark delta delays as 'delta'.
Assume B=O, C=1.
a) S = A XOR B
Y = SNANDC
Note: No delays have been specified for the gates in part a).
b) S <= A XOR B after 2ns
Y <= S NAND C after Ins
(;\A)- tt, I "s
A
(1r-lJ. S fUtA (.i ad s

c) Y = transport A after 3ns

l ,
o
EEE 333 Fall 2009, Final 2
NAME: ___ _ SID #: _ __________ _ __
Problem 2: Complete (write) the following VHDL code for the ALU described in the following
table and drawn as the following circuit. (20 pts)
S4 S3 S2 Sl SO Cin Operation
_._-
Block
0 0 0 0 0 0 Y<=A Arithmetic Unit
0 0 0 0 0 1 Y <= A + 1 Arithmetic Unit
0 0 0 0 1 0 Y<=A+B Arithmetic Unit
0 0 0 0 1 1 Y <= A + B + 1 Arithmetic Unit
0 0 0 1 0 0 Y <= A + Bbar Arithmetic Unit
0 0 0 1 0 1 Y <= A + Bbar + 1 Arithmetic Unit
0 0 0 1 1 0 Y <= A-I Arithmetic Unit
0 0 0 1 1 1 Y<=A Arithmetic Unit
0 0 1 0 0 0 Y<=AANDB Logic Unit
0 0 1 0 1 0 Y<=AORB Logic Unit
0 0 1 1 0 0 Y<=AXORB Logic Unit
0 0 1 1 1 0 Y <= Abar Logic Unit
0 0 0 0 0 0
0
Y<=A
Y <= shl A
Shifter Unit
0 1 0 0 0 Shifter Unit
1 0 0 0 0 0 Y <= shr A Shifter Unit
1 1 0 0 0 0 Y <=0 Shifter Unit

EEE 333: Fall 2009, Final 3
- -
NAME:. SID #: __ ___ ____________
library IEEE;
use IEEE.STD_LOGIC_1164.aU, IEEE.NUMERIC_STD.all;
entity ALU is
port (Sel: in unsigned( 4 downto 0);
CarryIn: in std _logic;
A , B: in unsigned(7 downto 0);
Y: out unsigned(7 downto 0));
end entity ALU;
architecture COND DATA FLOW of ALU is
begin
process(Sel, A, B, CarryIn)
variable SELO_1_Carry In: unsigned(2 downto 0);
signal LogicUnit, ArithUnit, ALU _NoShift: unsigned(7 downto 0);
begin
-- Logic Unit Use case statement!
[oklC_VAl /T : 0) i&
., '-AVI "00'" __ ....... J /I J.
vv Vl-"" .. ./ f-.- oJ' t:. l/fl j T c:::.. -= A e:. 0 ;
{fi h VI ""() , '1 = > I- i (1)n ;-} L -== A (),. 5 j
wh.tV) '" => LQj-;c..UYlit c(:: A
whpvt ,,' = > L(J 11 c.. Vn i I.e:... -= Y1 p of A ;
wh.evr o-#,.tr5 => L.jie-U,,;.J L:; ( 0 !Jurc:. => IX ');
.lVlJ. u!,e LOtrlC - VtJ IT
--Arithmetic Unit Use case statement!
EEE 333: Fa112009, Final 4
NAME:_________
SID #: _______ ___
SelO_ l_Carryln:=Sel(l downto 0) & Carryln;
A /21-r14 _ vN IT : co. 510-1- CN"(.,(T}'\
LAth It") => AyJ.h Vni1 L.. -=. A "' ODD If
"0",11 =-> ,4y;+k V(I;tL -=- 4:1-1;
0 J0" => At- tJnil- L -- A+" g j
\.tOil" =-7 v(
YI () => Ari -HtVY\ A vto+--
E
.:" <l
'" I 0 I => 411 t-f, l!",d.. A- 15j
1-1/1 D 1-1 -...> h ,-fit VYI if L -=- A- -/
-.i 111 r1 =) 4-i Jt. V
Y1
I.J- L:. A..;
Q./1tws --'> (f)fhu{,
IVI J ,ft211/1_ tiN )T '
-- Multiplexer Use if statement!
LA_!1u)(: ;f (z) +heY! /
ALiJ _ L. -::;. [OJ; c- (h,f,; cY
S
f
--Shift Operations Use case statement!
$ II 1';:'1: (lj cLw"J[) s) IS.
t:;/{ ,b Oil -::::"/' Y .It L U _ rJD 5.1t;.{r-/
EEE 333: FaJl2009, Final 5
- -
NAME: _ C;; ' _ _
SID#: ________________________
___ v __
end process ALU_AND_SHIFT;
end architecture COND_DATA_FLOW;
Problem 3: VHDL code for a linear feedback shift register (LFSR): (20 pts) LFSRs are very
interesting circuits used frequently in counters, pseudo random number generators, built in self
test for VLSI, date encryption and decryption and data compression. The following is VHDL
code for a generic N bit LFSR. For this problem, assume Width=3.
library IEEE;
use IEEE.STD_LOGIC_ 1164.all, IEEE.NUMERIC_STD.all;
entity LFSR_GENERIC_MOD is
generic (Width: integer);
port (Clock, Reset: std _logic;
Y: out unsigned(Width - 1 downto 0));
end entity LFSR_GENERIC_MOD;
architecture RTL of LFSR GENERIC MOD is
type TapsArrayType is array (2 to 32) of unsigned(31 downto 0);
constant TapsArray: TapsArrayType: =
(2 => (011 = ' 1 " others=>' O' ),
3 = (012 =>' 1', others=>'O') ,
4 => (013 = ' 1', others=>' O' ),
5 => (114 = ' 1', others=>'O'),
6 => (015 = ' 1' , others=>' O' ) ,
EEE 333: Fall 2009, Final 6
NAME: _______ _ _ _ _ SID #: ___________ _
7 => (016 =>' 1' , others=>'O' ),
8 => 01213 17 =>' 1', others= ' 0' ),
9 => (318 = ' l ' others=> '0') , ,
32 => (1 1516131 =>' 1 " others=>' O' ));
signal Taps : unsigned(Width-l downto 0);
begin
LFSR: process (Reset, Clock)
variable LFSR_Reg: unsigned(Width - 1 downto 0) ;
variable Feedback: std _logic;
begin
Taps <= TapsArray(Width)(Width-l downto 0);
if (Reset = '0' ) then
LFSR_Reg:= '001 '; ------customized for your 3 bit example
elsif rising_ edge(Clock) then
Feedback := LFSR_Reg(Width-1);
for N in Width - 1 to I loop
if (Taps(N -1)=' 1 ' ) then
LFSR_Reg(N) := LFSR_Reg(N-I) xor Feedback;
else
LFSR_Reg(N) := LFSR_Reg(N-l);
end if;
end loop;
LFSR_Reg(O) := Feedback;
end if;
Y <= LFSR _Reg;
end process;
end architecture RTL;
EEE 333: Fall 2009, Final 7
S;: DLwt _ _ NAME:___ __ , _
SID #: ____________
a) Draw the circuit that this code describes. Hint: It is just a few flip flopCs) and gate(s).


c.-(fz. _-L------'------+-
b) Either from the VHDL code or from your circuit, what is the sequence of pseudo-random
numbers that this circuit cycles through? It will repeat after a few numbers. That is: list the
sequence of binary numbers that the register holds starting with your Reset value in the code.
Go(
I
D
o
(9 ( ()
()
0 I
I () l>
D 0
I
1 I
(
()
I { D

t ".. (
0
(
10 ,
t J
r
,
0
\
I
C:>
o
01 o
v t1. f '000 I
c) What happens if you had Reset into the state 'OOO' ? X.J- w>/I
o 0 D
--:........ 0

d) For this circuit, would you be more concerned about setup time violations or hold time
violations? Circle one:
Setup time violations Hold time violations
EEE 333: Fall 2009, Final 8
I