Test questions of nVidia: 1. Some question on calculating the depth of FIFO in an interrupt based microcontroller based system.

The question was too long to read and had to be skipped initially. 2. Write a C program to: i). find the last instance of a character in a string. ii). determine how many bits are set in a given integer 3. Question on setup/hold time. A very good question. The circuit had two f/fs with a programmable tap (providing programmable delay in terms of n) in between the clock line of the two f/f. two conditions best case and worst case timing details (tclk-q, tsetup, thold and programmable delaymin )were given and accordingly the range of values of the n was to be calculated. Part ii) dealt with the jitter in the clock. Was asked to determine how the max clock frequency would change. 4. Write a pseudo-code to determine the union of two sets A and B. all the necessary functions were defined by them. One of easiest questions of the paper. 5. A problem of finding tag, offset index of cache. I did not try to read this question as I had no idea of cache memory then. 6. A pmos circuit interms of graph was given. Had to find the nmos part of it to make it a complete cmos circuit. Part ii) find the equation implemented by the cmos circuit. 7. Two blank nand gates (ie., no i/p were given) and only one i/p was present. Find two different implementations of an inverter using a NAND gate. Part ii). Which implementation was faster and why? Probably the easiest question of the lot. 8. A bridge fault was present between a 2i/p AND gate and OR gate (with all four different i/ps being unique). Find the number of i/p patterns required to determine the presence of a fault. Part ii). What is the number of patterns required now if the above gates are replaced with 3-i/p gates. 9. A 8bit vector is given to the 1s counter which counts the number of 1s. it is then given to a comparator which compares and sets a dbi indicator to high if the count is greater than 4. However this is a small mistake and dbi should be high if the count is greater than or equal to 4. Design the additional circuit that should be connected with the existing one so as to correct this mistake using minimum number of 2-i/p gates. Interview questions in nVidia: 1. There is a clock and a i/p. Design a circuit such that it filters out a single cycle positive and negative (if any) pulse and passes non-single cycle pulses with a one-clock delay. 2. There is a Unit A. i/p 32 bits and o/p 8 bits. Write operations happen on the i/p and Read operations happen on the o/p. write operations happen at 40MHz clock frequency and Read operations happen at 160 MHz clock frequency. Determine the size of memory to be allocated in Unit A such that no overflow occurs. Part ii) Change the Write clock frequency to 160Mhz. Hence find the same. 3. What is setup/hold time? Explain. Why have you not considered hold time while calculating the max clock frequency? Is hold time not important??? The test paper question on setup hold time was again asked with different parameter values and asked question on hold time. 4. What are the different aspects of Power dissipation in a cmos. What is dynamic power dissipation? Assume that I have a laptop running on a battery (charging off). What measures should the system take so as to have minimum power consumption? What is static power dissipation? How to minimize it? 5. Design a circuit that divides the clock frequency by 3. Some non-technical questions: where did you do your engineering from? What are you doing in BITS Goa if you are from BITS Hyd? Where are you from? Are you not interested in software as you have not solved programming questions well (except for the pseudo code question). There were no HR questions. HR lady was sitting with laptop and entering details as well as noting the body language of the interviewed person. --Abhijeet Chandratre M.E. Microelectronics BITS Pilani Hyderabad campus