Electric Power Systems Research 79 (2009) 12001208

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Electric Power Systems Research

journal homepage: www.elsevier.com/locate/epsr

Electronic power transformer with supercapacitors storage energy system

Haibo Liu, Chengxiong Mao, Jiming Lu , Dan Wang
Hubei Electric Power Security and High Efciency Key Lab, Department of Electrical Engineering, Huazhong University of Science and Technology (HUST), Wuhan 430074, PR China

a r t i c l e

i n f o

a b s t r a c t
An electronic power transformer (EPT) with supercapacitors storage energy system is proposed in this paper. The proposed system consists of an EPT, a supercapacitor bank and a bidirectional dcdc converter. The supercapacitor bank is connected to the dc link in EPT through the dcdc converter. The advantage of the proposed system over the EPT is to provide added ability to ride voltage momentary interruptions, as well as the voltage sags and voltage swells. Furthermore, the main circuit parameters design and controller design of proposed system are presented in detail. The performance of proposed system is analyzed using simulations based on MATLAB/SIMULINK, and the proposed system is also implemented in laboratory based on DSP TMS320F2812. Simulation and experimental results have veried the ability of the proposed system and the validity of the design. Crown Copyright 2009 Published by Elsevier B.V. All rights reserved.

Article history: Received 31 July 2008 Received in revised form 20 January 2009 Accepted 28 February 2009 Available online 3 April 2009 Keywords: Bidirectional dcdc converter Electronic power transformer (EPT) Medium frequency transformer (MFT) Storage energy Supercapacitors Voltage interruptions

1. Introduction Electronic power transformer (EPT) is a new intelligent power transformer enhancing the functions of the conventional power transformer and achieving the exible ac transmission systems (FACTS) by power electronic conversion and has attracted much attention from both academy and industry [15]. Most of the studies reported recently concentrated on its main circuit topology design, power quality improvement for customers, parallel operating control technology and mathematical model establishing [69] and the prototypes applied in the distribution system have been implemented [1,4]. These researches show that EPT is employed to not only realize the basic functions of traditional power transformer such as voltage transformation, isolation, power delivery, but also perform many additional features like reactive power compensation, preventing from the primary voltage sags, voltage swells, voltage ickers, harmonics and voltage unbalance infecting the output voltage etc.. However, EPT cannot compensate the voltage interruption because it has no energy storage in the dc link. Recently, supercapacitors (also known as ultracapacitors) are paid attention as a new energy storage element. The supercapacitors have a lot of advantages such as no maintenance, long lifetime and quick charge/discharge characteristics with large current and can operate effectively in diverse (hot, cold, and moist) environments [10]. At present, supercapacitors have seen much application in electric vehicles [11,12]. Near-term applications mostly use these

capacitors in power quality applications. For example, supercapacitors are added to the dc link of uninterruptible power supply (UPS) to enhance power supply reliability in case of grid failure [12]. Supercapacitors are added to the dc link of motor drives to improve ride-through times during voltage sags [13]. Supercapacitors are also added to a dynamic voltage restorer (DVR) or interfaced to the dc link of a distribution static compensator (DStatCom) [14,15]. However, UPS and DVR must try to synchronize their output voltage to the power grid voltage when the grid voltage is resumed to normal operation because UPS and DVR are connected in parallel with the grid [16]. We use the supercapacitors as an energy storage element of EPT. In this paper, a combined operation system of EPT and supercapacitors storage energy system, which is composed of a supercapacitor bank and a bidirectional dcdc converter, is proposed. The advantage of the proposed system over the EPT is to provide additional ability to ride voltage momentary interruptions, as well as the voltage sags and voltage swells. The advantage of the proposed system over the DVR and the UPS is to have no above-mentioned synchronization problem because EPT is connected in series with the grid. The operation of the proposed system was veried through computer simulations based on MATLAB/SIMULINK. The feasibility of hardware development was conrmed through experimental works.

2. System conguration
Corresponding author. Tel.: +86 27 87542669; fax: +86 27 87542669. E-mail address: lujiming@mail.hust.edu.cn (J. Lu).

Fig. 1(a) shows circuit diagram of EPT. As can be seen from the Fig. 1(a), this is a three-stage design that includes an input stage,

0378-7796/$ see front matter. Crown Copyright 2009 Published by Elsevier B.V. All rights reserved. doi:10.1016/j.epsr.2009.02.012

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Fig. 1. Circuit diagram of EPT and block diagram of the proposed system (a) circuit diagram of EPT, (b) block diagram of EPT with supercapacitor storage energy system and (c) bidirectional dcdc converter with supercapacitors.

an isolation stage and an output stage. In the input stage, there is a three-phase high frequency converter, which converts the input ac voltage to dc voltage. The isolation stage consists of H-bridge-1 and medium frequency transformer (MFT) and H-bridge-2. The dc voltage from the input stage is fed to the H-bridge-1 and is modulated to a medium frequency square wave. Then the square wave is provided to the MFT and is rectied as dc voltage by the H-bridge-2. In the output stage, there are three single-phase inverters, which convert the dc voltages from the isolation stage to three phase ac sinusoidal voltages. In Fig. 1(a), L1 is the input inductor, CDC1 is the dc capacitor of the input stage, Lf , Rf and Cf are the lter inductor, the lter resistor and the lter capacitor of the output stage respectively. The system conguration of EPT with energy storage element is shown in Fig. 1(b). Main circuit of the proposed system consists of an

EPT, a bidirectional dcdc converter and a supercapacitor bank. The simple equivalent circuit of the supercapacitor bank is also shown in Fig. 1(b), where R is the equivalent resistance, CSC is the equivalent capacitor. Here, the supercapacitor bank is connected to dc link through a bidirectional dcdc converter. The dcdc converter is used to control the charging current to the supercapacitors and also used to keep the dc link voltage constant for the discharge of the supercapacitors. Furthermore, the high voltage supercapacitors are not required because of the boost function of the dcdc converter, also there is a possibility to limit a charging current and accordingly to limit a starting current due to the inductor L comparing to the supercapacitors being directly connected to dc link. In normal situations, the electric power to the load is provided from power grid through EPT, the supercapacitors are charged with

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constant current. After the voltage becomes full, the voltage across the supercapacitors is kept constant by the dcdc converter. And the dc link voltage is also kept constant by the isolation stage of EPT. When power failure occurs, the power from the supercapacitors is provided to the load through the dcdc converter, and the dc link voltage is kept constant by the dcdc converter. When the power grid is resumed to normal operation, the proposed system has no synchronization problem because EPT is connected in series with the grid. Therefore, the proposed system can compensate not only the voltage sags but also the short-term power interruption. 3. Analysis and design of supercapacitors storage energy system 3.1. Supercapacitors Since several years, supercapacitors are paid attention as a new energy storage element. Supercapacitors have some advantages over batteries [10]: Rapid charge/recharge capability within minutes. High power density. Low degradation after 100,000 cycles. No maintenance, high reliability. Environment safety. Wider operating temperature range.

electrochemical devices with very high capacitance values, which allows reaching specic energy density of 4.5 Wh/kg and specic power density of about 3500 W/kg [17]. Using these new types of supercapacitors that are suitable for high power and low energy applications, it is possible to better exploit the energy reserve for applications such as EPT. Firstly, in power system, most of grid faults are very short (1 s) [18]. Therefore, high power and low energy storage devices should be employed, whereas supercapacitors have the characteristic of high power density and low energy density. Secondly, its ability of quick charge and discharge can provide compensation repeatedly even if short-term voltage sag or momentary interruption occurs again and again. Furthermore, the supercapacitors do not require replacement for about 10 years or longer because the electrodes show little deterioration. Finally, high price of the supercapacitors denes high total price of the EPT, but the cost of the supercapacitors is less important comparing to the cost of the EPT itself. Thus, it is reasonable to choose supercapacitor storage system in EPT. 3.2. Bidirectional dcdc converter Fig. 1(c) shows the bidirectional dcdc converter with supercapacitors, which includes an inductor L, some supercapacitors CSC , a dc link capacitor CDC , two insulated-gate bipolar transistors (IGBTs) S1 and S2, and two diodes D1 and D2. The converter has two operation modes: Buck and Boost. Buck operation consists of transferring energy from the power grid to the supercapacitors by triggering IGBT S1. Boost operation results from triggering IGBT S2, and energy is transferred from the supercapacitor to power terminals. 3.3. Design of inductance L The inductance L allows transient energy storage during the operation of the dcdc converter. Its design is also related with

In the terms of energy density, supercapacitors are between an ordinary capacitor and a battery. At rst sight it is not protable to use supercapacitors for energy storage in EPT because of their high price and low energy density. However recent developments in nanotechnology help to achieve a major breakthrough in the eld of supercapacitors. Nowadays supercapacitors represent an emerging technology of

Fig. 2. Linear model of the dcdc converter control scheme and Bode plots of the closed-loop transfer function G(s) (a) linear model of the dcdc converter control scheme and (b) bode plots of the closed-loop transfer function G(s).

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the current ripple amplitude, which is one of the variables that has to be minimized, because it produces undesirable electromagnetic interference, mechanical vibrations, and losses due to current induction on the surrounding conducting material. On the other hand, its weight, volume, and series resistance have to be as small as possible. The design of inductance L is a compromise between size, current ripple, and control performance. Neglecting the internal resistance of the inductance L and assuming a constant voltage VSC , the current ripple is given by I= VDC D(1 D) fPWM L (1)

However, the capacitor should be chosen small enough to achieve a good tracking to the dc link voltage. The right value depends on several factors, such as the sampling frequency of the voltage loop and the bandwidth of the current regulation. 3.5. Average feedback linearization control Fig. 2(a) shows a linear model of the dcdc converter control scheme. For simplicity, the half-bridge is modeled by a constant power transfer, hence neglecting the losses in the semiconductors. The model has a multiloop controller, which consists of an inner supercapacitors current feedback loop and an outer dc link voltage feedback loop. In Fig. 2(a), kp1 and ki1 are the proportional and integrated gains of the dc link voltage feedback loop, kp2 and ki2 are the proportional and integrated gains of the supercapacitors current feedback loop. In order to analyze the tracking performance and the disturbance rejection characteristic of the proposed control scheme, the closed loop transfer functions of the system are modeled. According to Fig. 1(c), the bilinear differential equations that describe the large-signal dynamic behavior of converter are presented as follows: L diSC = VPWM VSC dt d(VSC iSC R) = iSC dt dVDC = iPWM iDC dt (3a) (3b) (3c) (3d)

where VDC is the dc link capacitor voltage; fPWM is the switching frequency of IGBTs; D is the duty cycle of the pulsewidth modulation (PWM) applied (0 < D < 1). The maximal value occurs at a duty cycle of 50%. As seen from Eq. (1), its value is proportional to the dc link voltage and can be decreased by increasing the switching frequency and/or the inductance L. 3.4. Design of dc link capacitance CDC The right amount of dc link capacitance depends on the following factors: current ripple, allowable dc link voltage ripple and desired voltage-regulation bandwidth. The most important role of the capacitor is to provide reactive power to the switching, as, during each PWM cycle, the power ow to the capacitor is reversed twice. Enough capacitance is required to limit the ripple of the dc link voltage, which is veried by Eq. (2). UDC iSC = D(1 D) fPWM CDC (2)

CSC CDC

iPWM = D iSC

where iSC is the supercapacitors current. The dc link capacitors must be capable of carrying the current owing through the capacitors without overheating. This is the second of design criterion. Practice shows that this requirement is often more stringent than voltage ripple specications. Finally, the dc link capacitor is to be chosen large enough to allow for the desired disturbance rejection at the dc link voltage regulator.

where means average value over one switching cycle. According to nonlinear control and feedback linearization theory [8] and from Eqs.(3a), (3b), (3c) and (3d), the open-loop averaged dc link output voltage dynamics can be derived DCSC d VPWM d3 VDC d2 VDC d VDC = LCDC CSC RCDC CSC CDC dt dt dt dt LCSC d2 iDC d iDC RCSC iDC dt dt (4)

Fig. 3. Control diagram of input stage and output stage (a) control diagram of input stage and (b) control diagram of output stage.

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Fig. 4. Voltage interruption compensation (a) input voltage, (b) input current, (c) input stage dc voltage, (d) primary voltage of MFT, (e) secondary voltage of MFT, (f) output stage dc voltage, (g) supercapacitors voltage, (h) supercapacitors current, (i) load voltage and (j) load current.

According to Fig. 2(a), the control expression of the dc link output voltage can be derived VPWM = kp2 [kp1 (VDC VDC ) + ki1 D
[kp1 (VDC VDC ) + ki1 (VDC VDC )dt iDC ]

where G(s) is the voltage gain and Z(s) is the output impedance, as shown in Eqs. (7a) and (7b) G(s) = VDC VDC

iDC =0

k i2 D

(VDC VDC )dt iDC dt

= (5)

kp1 kp2 s2 + (kp1 ki2 + kp2 ki1 )s + ki1 ki2 LCDC s4 + RCDC s3 + (kp1 kp2 + CDC /CSC )s2 + (kp1 ki2 + kp2 ki1 )s + ki1 ki2 VDC iDC

(7a)

where VDC is the dc link voltage reference. By Eqs. (4) and (5), the closed-loop dc link output-voltage dynamic behavior takes the form VDC = G(s)VDC Z(s)iDC

Z(s) =

(6) =
Parameter R CSC ki1 ki2 Value 0.02 60 F 0.5 0.45

V =0
DC

Ls3 s4

+ (R + kp2 )s2 + (ki2 + 1/CSC )s

Table 1 The parameters of the storage energy system. Parameter L CDC kp1 kp2 Value 0.3 mH 0.05 F 5 19.5

LCDC + RCDC s3 + (kp1 kp2 + CDC /CSC )s2 + (kp1 ki2 + kp2 ki1 )s + ki1 ki2

(7b)

Fig. 2(b) shows the typical Bode plots of G(s). We set the parameters of the dcdc converter to the values listed in Table 1 according to the above-mentioned design principle and the proposed control scheme.

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4. EPT main circuit design Hereinafter, the main circuit parameters design of EPT is discussed and the corresponding control scheme is also proposed. Section 4.1 introduces the design of input stage, and the designs of isolation stage and output stage are presented in Section 4.2 and Section 4.3 respectively. 4.1. Design of input stage 4.1.1. Design of input inductor Design of the input inductance is related with not only the dynamic response and steady-state response of the current loop, but also the output power, the power factor and the dc voltage of three-phase high frequency converter. The main functions of the inductance are as follows: isolating the ac side voltage Va1 , Vb1 and Vc1 from the input voltage ea , eb and ec , eliminating the harmonic current of the ac side, making the converter have the boost voltage characteristic and achieving good damp characteristic. The input inductance should be chosen large enough to keep the input current sinusoidal. On the other hand, the input inductance should be chosen small enough to achieve a fast current tracking response. According to [19], its design should meet the inequality Eq. (8): (2VDC1 3Em )Em Ts 2VDC1 L1 3Im 2VDC1 imax (8)

small enough. However, in view of the disturbance rejection characteristic of the voltage loop control, the capacitor is to be chosen large enough. According to [19], its design may choose the following experience Eq. (9): CDC1 tr 0.74ReL (9)

where tr is the rising time, ReL is the equivalent load resistance. 4.1.3. Input stage control scheme Fig. 3(a) shows the input stage control diagram of EPT. The input stage of EPT described in this paper has two main functions. One is to keep the input currents ia1 , ib1 and ic1 sinusoidal and in phase with the input voltage to achieve unity input power factor and prevent harmonics from being injected to the grid. The other is to keep the dc side voltage of the input stage be a constant. In Fig. 3(a), is the synchronous angular velocity. As can be seen from Fig. 3(a), a dc voltage outer loop and an ac current inner loop are adopted to realize constant dc voltage control and keep the input current sinusoidal, and the reference for the reactive power i1q is set to zero in order to achieve unity input power factor. 4.2. Design of isolation stage The main functions of the isolation stage are as follows: voltage transformation, isolation and power delivery. To simplify the design of the control system, open loop PWM control is applied for the Hbridge-1 and H-bridge-2. In the H-bridge-2, the diode rectiers are adopted if only considering single-directional power ow. Therefore, neglecting the losses of MFT, the isolation stage can be treated as a proportional amplier. The simplied model of the isolation stage is presented as: VDC = 1 VDC1 k (10)

where Em is the peak value of the grid voltage, Ts is the equivalent switching frequency, imax is the maximum value of the input ripple current, Im is the amplitude of the input current, VDC1 is the dc side voltage of the input stage. 4.1.2. Design of dc capacitor of input stage The dc capacitor of input stage has two main functions. One is to keep the dc voltage be a constant. The other is to eliminate the dc side harmonic voltage. Generally, considering the tracking performance of the voltage loop control, the capacitor is to be chosen

where k is the transformation ratio, VDC1 and VDC denote the dc side voltages of the input stage and the output stage respectively. 4.3. Design of output stage 4.3.1. Design of lter inductor and lter capacitor The main function of the lter inductor and the lter capacitor is to reduce the output voltage harmonics, especially the low-order harmonics. In theory, if the lter inductor and the lter capacitor are selected large enough, the Total Harmonic Distortion factor (THD) of the output voltage will be well below the allowed value. However, too large lter inductor will aggravate the change of the load fundamental voltage, and too large lter capacitor will aggravate the change of the inverter output current. Thus, the design of the lter inductor and the lter capacitor is a compromise between the load fundamental voltage and the inverter output current. As we know, for the single-phase inverter adopting PWM control scheme, the output voltage harmonics mainly concentrate on the edge of the carrier frequency. Therefore, in order to reduce the output voltage harmonics and avoid the resonance, the resonance frequency should be far above the reference frequency, and should be far below the carrier frequency. The resonance frequency can be calculated by using Eq. (11). f = 1 2 Lf Cf (11)

Fig. 5. Voltage sag and swell compensation (a) input voltage, (b) load voltage and (c) Load current.

4.3.2. Output stage control scheme As described above, the output stage consists of three singlephase inverters, and the control of each inverter is independent.

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Each inverter is controlled as a single-phase sinusoidal voltage source to meet the requirement of the loads. Because the switching frequency is usually several orders higher than the fundamental frequency of the single-phase inverter, the switching dynamics of the inverter can be ignored. Thus, the output stage inverter can be modeled as a simple proportional gain block, as shown in Fig. 3 (b), where M is the proportional gain of the output stage inverter, (For the simplicity of analysis, we let M = 1.) kp3 and ki3 are the proportional and integrated gains of the output voltage feedback loop, kp4 and ki4 are the pro-

portional and integrated gains of the inductor current feedback loop. The model shown in Fig. 3(b) has a multiloop controller, which consists of an inner inductor current feedback loop, an outer output voltage feedback loop, and a reference voltage feedforward loop. An instantaneous value of the feedback signals is adopted to enhance the dynamic response in the control system, and the reference voltage feedforward loop is added to provide a high tracking accuracy and velocity to the reference on the basis of the conventional proportionalintegral (PI) control.

Fig. 6. Appearance of supercapacitor module, MFT and experimental results when EPT are in normal operation (a) appearance of supercapacitor module, (b) external view of MFT, (c) load voltage, (d) input current, (e) input stage dc voltage, (f) primary voltage of MFT, (g) output stage dc voltage and (h) secondary voltage of MFT.

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The control schemes are the same for the three phases. The only differences are the phase angles of the reference voltages Va , Vb and Vc , that is, the phase angle of phase A is set as 0 , phase B is +120 , and phase C is 120 . 5. Simulation results Some computer simulations with MATLAB/SIMULINK software were performed for the purpose of analyzing the operation of the proposed system and showing the validity of the design. The supercapacitor was modeled using a 60 F capacitor in series with a 0.02 resistor, and its nominal voltage is 200 V. The controller was modeled using the built-in control block in the MATLAB/SIMULINK software. The parameters of the storage energy system we designed are listed in Table 1. According to the above-mentioned EPT main circuit design principle, the EPT main parameters that were used in the simulation are as follows: the input inductor is 6 mH, the dc capacitor of input stage is 4700 uF, the lter inductor is 2 mH, the lter capacitor is 330 uF, the EPTs rated capacity is 500 kVA, the input voltage and the output voltage are 10 kV and 400 V respectively, the input voltage frequency is 50 Hz, the working frequency of MFT is 1 kHz, the transformation ration of MFT is 50, the load capacity is 500 kVA (power factor is 0.8). Fig. 4 shows the simulation results when the input voltage has a voltage interruption for 0.2 s from 0.3 s to 0.5 s. In view of the bidirectional power ow, when the voltage interruption happens, an isolation switch K shown in Fig. 1(b) preventing the energy of storage energy system owing the grid is required. Fig. 4(a), (i) and (j) shows the input voltage, the load voltage and the load current. The load voltage and current maintain a constant value by the support of the supercapacitors storage energy system. Fig. 4(b)(e) shows the input current, the input stage dc link voltage, the primary voltage and second voltage of MFT. Fig. 4(f)(h) shows output stage dc link voltage, the supercapacitors voltage and the supercapacitors current. Due to adopting the dcdc converter, although the supercapacitors are only charged to 200 V at the beginning, the dc link voltage is kept constant at about 400 V for the discharge of the supercapacitors. Fig. 5 shows the simulation results when the input voltage has a voltage sag for 0.1 s from 0.25 s to 0.35 s and has a voltage swell for 0.1 s from 0.45 s to 0.55 s. When the depth voltage sag or swell happens, the input stage constant dc link voltage control would not be obtained. So the input voltage should be switched off and the isolation switch must be turned off at the same time. Also, the simulation results are similar to that of voltage interruption. Thus, for simplicity, only the simulation waveforms of the input voltage, the load voltage and the load current are shown in Fig. 5(a)(c). The load voltage maintains a constant value as expected. These waveforms show that the proposed EPT can compensate the voltage interruption, as well as the voltage sags and voltage swells. From Figs Fig. 44(i and j) and Fig. 55 (b and c), we also can see that the load voltage and current are smooth and continuous when the input voltage is resumed to normal condition. The reason is that EPT is connected in series with the grid and the proposed system has no synchronization problem when the power grid is resumed to normal operation. 6. Experimental results An experimental system was built and tested to conrm the feasibility of actual hardware implementation. EPT has a structure as shown in Fig. 1(a) except that the diode rectiers are adopted in the H-bridge-2. The controller was implemented by means of a TMS320F2812, xed-point 150 MHz digital signal processor (DSP)

from Texas Instruments. In view of the voltage interruptions being more severe than the voltage sags, only experimental results based on the voltage interruptions are given in the following section. The following describes the supercapacitor module applied in the storage energy system. One supercapacitor unit has a capacity of 1200 F at 2.7 V, and twenty units are placed in series to make one module of 60 F at 50 V. The appearance of the module is shown in Fig. 6 (a). A module has dimensions of 145 mm wide 275 mm deep 220 mm high, with the weight being approximately 9 kg. Thus, its energy density reaches 2.3 Wh/kg. In addition, its price is about US $40. EPT has the following parameters: the input voltage equals 60 V, the output voltage equals 30 V, the working frequency of MFT as shown in Fig. 6 (b) is 1 kHz and its transformation ratio is 3. Although simulation and experiment systems are different, due to the working frequencies of power switch devices of the dcdc converter used in simulation and experiment being different, one is 16 kHz, and the other is 8 kHz. Also, the dc link voltages of the energy storage system are different, one is 400 V, and the other is 50 V. Thus, according to Eqs. (1) and (2), the inductance L and the dc link capacitance CDC of the energy storage system used in experiment can be designed similar to that used in simulation. The working frequencies of power switch devices, IGBT, used in EPT and the dcdc converter are 1.2 kHz and 8 kHz respectively. The load consists of three 20 resistors.

Fig. 7. Experimental results when voltage interruption occurs (a) load voltage and (b) dc link voltage, supercapacitors voltage and supercapacitors current.

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Fig. 6 also shows the experimental results when EPT is in normal operation with the proposed control scheme. Fig. 6(c) shows the load voltage. The load voltage maintains a constant value with the help of the inverters of the output stage. Fig. 6(d) and (e) shows the input current and the dc voltage of the input stage. The input current is kept sinusoidal and the dc voltage of the input stage is kept constant at 160 V. Fig. 6(g) shows the dc voltage of the output stage. Fig. 6(f) and (h) shows the primary voltage and the secondary voltage of MFT. All of these waveforms verify the validity of the design. Fig. 7(a) and (b) shows the experimental results when the input voltage has a voltage interruption for about 5 s. For the analysis of contrast, only the dc link of the output inverter of phase A is connected to supercapacitors module through a dcdc converter. Fig. 7(a) shows that the load voltage of phase A maintains a constant value because of using storage energy system, whereas the load voltages of phase B and phase C cannot maintain a constant value. Fig. 7(b) shows the dc link voltage, the supercapacitors voltage and the supercapacitors current. All of these experimental results are consistent with the simulation results. These waveforms also show that the proposed system provides added ability to ride voltage momentary interruptions. Considering the limit of experimental condition, the paper illustrates a fairly small EPT with a supercapacitor. In fact, neglecting the converters losses, the supercapacitor module adopted in this paper can supply to the used 45 W load for about 1666 s and the 75 kW load for about one second. For a 500 kVA load used in the simulation, the adopted modules are arrayed by four in parallel and by four in series to constitute a block of 60 F at 200 V, then the block can supply the 500 kVA load for about 2.4 s. According to the energy density and the price of the adopted module, the weight of the block is approximately 72 kg and the price of the block is about US $320 respectively. Comparing the size and the cost of EPT itself, the size and the cost of the block should be accepted. And there also is patented technology that allows createing a supercapacitor with energy density 1.6 MJ/kg [12]. In addition, it must be noted that supercapacitors undergo intensive development and become more and more size and cost available. Therefore, the utilization of the supercapacitors storage system in EPT has good prospects. 7. Conclusion This paper describes the analysis results of a combined operation of the EPT with supercapacitors storage energy system. The proposed system can compensate the voltage interruption because of the use of supercapacitors storage energy system. Compare to the DVR and the UPS, the proposed system has no synchronization problem when compensating voltage interruption because EPT is connected in series with the grid. Both simulation and experimental results have been reported to show the performance of the proposed system and the validity of the design. Acknowledgements This work was supported by Key Project of Ministry of Education of China (107128) and National Natural Science Foundation of China (50807020) and National Basic Research Program of China (2009CB219702) and Program for New Century Excellent Talents in University (NCET-04-0710).

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Rossi, A supercapacitor-based power conditioning system for power quality improvement and uninterruptible power supply, in: Proc. IEEE International Symposium Industrial Electronics, LAquila, Italy, vol. 4, 2002, pp. 12471252, July. [18] H. Spath, L.P. Becker, Short-time backup-power for mains-fed dc links by double layer capacitors, in: Proc. 35th Annu. IEEE Power Electronics Specialists Conf, Aachen, Germany, 2004, pp. 24752481. [19] C.W. Zhang, X. Zhang, PWM Rectier and its Control, Machine Press, Beijing, China, 2003, 141153. Haibo Liu was born in 1976. He is currently Working towards the Ph.D. degree in college of electric and electronics engineering (CEEE) of Huazhong Univ. of Sci. & Tech (HUST). His main interests are the applications of high power electronic technology to power system. Chengxiong Mao (M 1993) was born in Hubei, China, in 1964. He received his B.S., M.S. and Ph.D.degrees in electrical engineering, from Huazhong Univ. of Sci. & Tech. (HUST), in 1984, 1987 and 1991 respectively. He was a visiting scholar in University of Calgary, Canada, from Jan. 1989 to Jan. 1990 and in Queens University of Belfast from Dec. 1994 to Dec. 1995 respectively. He was doing researches in Technische Universitaet Berlin from April 1996 to April 1997 under the support of Humboldt Foundation. Presently, he is a professor of HUST. His elds of interest are power system operation and control, the excitation control of synchronous generator and the applications of high power electronic technology to power sytem Jiming Lu was born in Jiangsu, China, in 1956. He received his B.S. degree from Shanghai Jiaotong University, Shanghai, China, and received his M.S. degree from HUST. His research is focused on the excitation control based on microcomputer. Dan Wang was born in Jiangxi, China, in 1977. He received his B.S., M.S. and Ph. D. degrees in Department of Electrical Engineer, from Huazhong University of Science and Technology (HUST), Hubei, China, in 1999, 2002 and 2006 respectively. Presently, he is doing his postdoctoral researches in HUST. His interest is the applications of high power electronic technology to power system and excitation control of synchronous generator.