Traditional device simulators predict performance of devices built from semiconductor materials the properties of which of them are

known and exist as library files in the simulator. To develop a device simulator that could predict I-V and C-V characteristics of devices built with any emerging materials like Silicon or Germanium nanowires and simultaneously for any construction geometries of the device was the primary focus of my work. From there on, using the results from the device simulator for predicting the circuit behavior was targeted. Hence to develop a comprehensive physical model to seamlessly migrate from extracting the material properties provided by the band structure information file to modeling electronic response of the device and thereby predicting the circuit behavior was the aim of my work. IEEE-NMDC 2010: During the earlier stage, I considered Gate All Around (GAA) topology for the Field Effect Transistor with 3.1 nm diameter [110] axially aligned Silicon Nanowire (SiNW). It consists of an intrinsic SiNW, considered to be cylindrical and surrounded by 450 nm SiO 2 as the insulator, which in turn is surrounded by Al as the gate electrode. The source and drain regions are considered to be 50 nm long with a donar doping concentration of 10/cm, which corresponds to a bulk Si doping concentration of approximately 1014/cm3 . For modeling the electronic response of the device the standard lemma involves, with an initial guess of potential profile in the device and then solving self-consistently the Poisson solver for the electrostatics in the device and the charge transport equations like drift-diffusion for the new potential profile in the device unto a point where convergent solution is obtained after several iterations. At this stage I understand that further modeling accuracy can be aimed with equations describing the above processes involving in greater details of process description with effects like, carrier recombination and effect of interface traps and also Montecarlo methods for potentially more precise charge transport modeling. Still, the listed two (Poisson solver with Drift-diffusion) being fairly promising unto the nanoscale level are widely used for device modeling [1,2].

Fig 1. GAA device considered for the initial work reported at IEEE NMDC 2010

However given that the charge transport in these pseudo 1-D nanomaterials is essentially confined to a single dimension, solving one-dimensional drift-diffusion equation with multidimensional electrostatic equation for 3D structure becomes a challenging problem!!! One way to overcome the problem is using modified Poisson equation but hence limiting the precision of the simulator [3]. After careful analysis of the problem I have proposed using Gauss solver in lieu of the traditional Poisson solver. This allowed solving the Gauss Law in integral form for each cylinder (a finite element of the total channel region),
E .ds = Q total area

, where E is the electric field and Qtotal is

the total charge enclosed in the cylinder. For the ith grid point, the total charge becomes q (pi ni + Nd Na) l, pi, ni, Nd , and Na represent the hole, electron, donar, and acceptor concentrations, respectively, per unit length, while l is the length of the cylinder, and q is the electron charge. The integral in the above equation can be divided into three terms, corresponding to the two surfaces of the cylinder

perpendicular to the axis of the NW, while the third surface represents the Si-SiO 2 boundary. Therefore the integral for the ith grid becomes Si (Vi Vi 1 )ds + Si (Vi Vi + 1 )ds + SiO2 (Vi V gate )ds , where a constant normal electric field is assumed at the three surfaces, where the Al-Si work function difference is assumed to be applied to the gate voltage, V gate. This constant normal electric field is a characteristic limitation posed by the finite element methodology chosen for its accurate continuous scheme. With increase in number of elements, the model approaches continuous model at cost of computation. One has to make optimal-case decision about number of elements to be used, depending on both these criterion. Specifically the above integrals correspond to a bulk inversion of the channel, with no radial variation of the voltage at each point in the channel, as well as a constant electric field throughout the oxide in a radial direction. This dimension being too small in comparison to the chargefree oxide thickness and generally length of finite elemental section , the approximation made in the context is fairly acceptable. This proposed alternate approach is suitable for small structures under relatively low to moderate bias voltages. The finite element approach is utilized to solve the difference equations representing the above differential equations. The IEEE-NMDC 2010 paper described in detail the method of dividing the cylindrical device into grids for implementation of this FEM approach. It was observed that this method may also be extended to more complex nano-device structures, where for electrostatics in the charge-free oxide and nanowire is solved using a combination of Laplace equation and Gauss Law in integral form. The electronic response of the device was reported, and also a methodology of using an equivalent circuit model to represent the device as a circuit element to arrive at the entire circuit response was demonstrated, using SPICE circuit simulation. Hence a comprehensive physical model to seamlessly migrate from extracting the material properties provided by the band structure information file to modeling electronic response of the device and thereby predicting the circuit behavior was shown.

Fig 2. Equivalent circuit representation for GAA device with variable resistors and variable capacitors ladder

Matlab was chosen for building the simulator, because of the ease it offered from inbuilt functions in solving the processes defining differential equations based on Finite Element Methods and the ease in viewing the parameter behavior at any given stage, using the plotting techniques. IEEE-Nano 2011: Multi-gated and cubical block of device within which nanowire is surrounded by oxide layer is modeled. By including 3D Laplace solver to determine the potential profile within the charge-free oxide in conjunction with Gauss Law for SiNW channel, the electronic response of the device is determined by utilizing above mentioned finite element scheme for solving difference equations for transport and electrostatics self-consistently. The device simulation allows us to determine the distributed resistances and capacitances of the devices, for different source, drain, and gate voltages. In this paper (for IEEE Nano 2011), an inverter was simulated with device modeled as a combination of different voltage dependent resistors and capacitors, as seen like in Fig. 2. Lookup tables can be created for those resistance and capacitance

values, and used in HSPICE to simulate the response of the inverter, or any logic gate. In this paper, the electronic response of the device was reported with I-V curves and potential/charge profiles. Also a methodology of using an equivalent circuit model to represent the device as a circuit element to arrive at the entire inverter circuit response was demonstrated, using SPICE circuit simulation.

Fig 3. Dual-gate device geometry for SiNW FET

Sentauraus TCAD for device modeling: I have gained good understanding of underlying device processes and mechanisms especially in conjunction with diodes, BJTS and MOSFETs through EECE 306 (Semiconductor devices and Effects I), by Dr. Ron Schrimpf. During the coursework EECE 307 (Semiconductor devices and Effects II) I created 2D and 3D MOSFET, SOI, FinFET and MOS Capacitor device models on Sentauraus TCAD and matched the performance characteristics to the reference devices from which the models were built. In one instance, I have made a detailed report after designing SOI on TCAD for Steeper subthershold slopes and lower DIBL using a 50nm depleted substrate CMOS transistor by Robert Chau et. al. at Intel [4].

Fig 4. Screen shot of channel area of SOI device with mesh layout in TCAD References [1] S. Selberherr, Simulation of Semiconductor Devices and Processes, Springer Verlag. [2] K. Tomizawa, Numerical simulation of submicron semiconductor devices, Artech science materials house library. [3] F. G. Pikus and K. K. Likharev, Nanonoscale field effect transistors: An ultimate size analysis, Applied Physics Letters, vol. 71, no. 25, p. 3661, 1997 [4] Robert Chau et.al., A 50nm depleted-substrate CMOS transistor (DST), electron devices meeting, 2001. IEDM tech. digest intl. pages. 29.1.1 - 29.1.4.