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http://www.utdallas.edu/~tma051000/Labs
EE/CE 3120 Syllabus
 ______________________________________________________________________________  _________________________ 
Course Information
Term
Fall Semester 2011
Course Title
Digital Circuits Lab
Course Number 
 EE/CE 3120
Section DayTimeLocation TA
101Monday1:00 PM – 3:45PMECSN 3.112 & 3.114Sarah Ostadabbas 102Wednesday1:00 PM – 3:45PMECSN 3.118 & 3.120Rasoul Yousefi103Monday1:00 PM – 3:45PMECSN 3.118 & 3.120Rasoul Yousefi104Wednesday4:00 PM – 6:45PMECSN 3.112 & 3.114Sarah Ostadabbas 105Wednesday4:00 PM – 6:45PMECSN 3.118 & 3.120Sarah Ostadabbas
Instructor Contact Information
 Instructor 
 Tariq Ali, Ph.D.
 Email Address
tma051000@utdallas.edu
Office Location
ECSN 4.408
Office Hours
 By Appointment
TA Contact Information
NameEmailOffice Hours Office Location
Sarah Ostadabbas sarahostad@utdallas.eduTBDTBDRasoul Yousefir.yousefi@student.utdallas.eduTBDTBD
Course Pre-requisites, Co-requisites, and/or Other Restrictions
Pre-requisite: EE 2310Co-requisite: EE 3320
Course Description
Designing, assembling and testing of combinational and sequential logic circuits. Logic designs will be done using samplecomputer-aided design (CAD)tools and implemented using Field-Programmable Gate Arrays (FPGAs). In this laboratory digital circuits will be designedand implemented using the
 Foundation Series Tools
and
 FPGAs
from
.
Student Learning Objectives/Outcomes
1. Ability to design, assemble and test combinational logic design using FPGAs
 
2. Ability to design, assemble and test hierarchical combinational logic design using MSI macros.3. Ability to design, assemble and test sequential logic design flip-flops and registers.4. Ability to design, assemble and test sequential logic design using Verilog.5. Ability to design, assemble and test arithmetic and logic unit.
Required Textbooks and Materials
 Required Material 
Xilinx Spartan 3E, Basys 2 FPGA board, 250k gate:https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,790&Prod=BASYS2See suggested material: Palnitkar ebook highly recommended.
Suggested Course Materials
Suggested Texts
John Wakerly,
Digital Design Principles and Practice
, Third Edition, ISBN 0-13-769191-2, Prentice Hall, EnglewoodCliffs, New Jersey 07632.Samir Palnitkar,
Verilog® HDL: A Guide to Digital Design and Synthesis
, Second Edition (Available online atMcDermott Library, under ebooks).
Tentative Lab Schedule and Assignments
LabDateTopi
 Intro9/12 - 9/14Xilinx IntroductionVerilog Tutorial I19/19 - 9/21Lab1, Addendum 19/26 - 9/28Lab1 (contd.)2Verilog10/3 - 10/5
Lab2Verilog Tutorial II
210/10 - 10/12
Lab2 (contd.)
310/17 - 10/19Lab3,Hints 310/24 - 10/26
Lab3 (contd.)
410/31 - 11/2Lab4411/7 - 11/9
Lab4 (contd.)
511/14 - 11/16Lab5511/21 - 11/23
Lab5 (contd.)
In this laboratory you will work in teams of two. However, the Lab. reports will be written individually.
Please do not copy Lab. reports! You will only cheat yourself, if you do. Please read the UT Dallas policy onscholastic dishonesty in thissyllabus.
 
The final report for any lab experiment is due at the beginning of the next new lab experiment. Laboratory reportis due within first 30 minuteson the due date. Reports that are late by less than one week will be penalized 30%. No report will be accepted afterone week from the due date
Please use the following format for your Lab. reports:Lab Report Format Cover: Includes course number, topic of the assignment, names of team members and your section.Abstract: Brief introduction to the assignment and a summary of results.For the rest of the report please follow the instructions given in individual laboratory assignments.Each lab will equally contribute to the final grade.
Grading Policy
 Pre-lab Work 30% In-lab Performance 20% Laboratory Reports 50%Grades will be assigned as follows:90% - 100% A 80% - 89% B 70% - 79% C 60 - 69% D Below 60% F
Course Policies
Class Attendance
* Attendance will be taken by TAs. Arriving late, being absent or leaving without notice does not count as positiveattendance and will affect your grade.
Classroom Citizenship
Professional at all times.
Student Conduct & Discipline
The University of Texas System and The University of Texas at Dallas have rules and regulations for the orderly and efficient conduct of their  business. It is the responsibility of each student and each student organization to be knowledgeable about the rules and regulations which governstudent conduct and activities. General information on student conduct and discipline is contained in the UTD publication,
 A to Z Guide
, which is provided to all registered students each academic year.The University of Texas at Dallas administers student discipline within the procedures of recognized and established due process. Procedures aredefined and described in the
 Rules and Regulations, Board of Regents, The University of Texas System, Part 1, Chapter VI, Section 3
, and in TitleV, Rules on Student Services and Activities of the university’s
 Handbook of Operating Procedures
. Copies of these rules and regulations areavailable to students in the Office of the Dean of Students, where staff members are available to assist students in interpreting the rules andregulations (SU 1.602, 972/883-6391).A student at the university neither loses the rights nor escapes the responsibilities of citizenship. He or she is expected to obey federal, state, and

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