Fifo Code

Adv Digital Design
By Dr. Shoab Ahmed Khan

shoab@avaz.com
Design Example: 4 Entry FIFO
4-entry FIFO queue

Create a first-in, first-out (FIFO) queue that consists of four registers. The operations on the queue are INSERT and DELETE INSERT moves data from the INBUS to the tail of the queue. DELETE deletes the head of the queue. The head of the queue is always available on the OUTBUS Insertion into a full queue or deletion from an empty queue causes an ERROR condition. Assertion of INSERT and DELETE at the same time causes an ERROR condition
Adv. Digital Design By Dr. Shoab A. Khan
Fall 2002
Sequencing and Control

Engineering Education Trust Center for Advanced Studies in Engineering 5-A Constitution Avenue, Software Technology Park. Islamabad, Pakistan.
The art of algorithm to architecture mapping

Example: FIFO
FIFO Data Path
inbus
Ld0 R0 Ld1 R1 Ld2 R2 Ld3 R3
Sel 2
outbus
Sample Verilog Code

//Combinational part always @(current_state or delete_from_q or insert_in_q ) begin next_state=0; case(current_state) //===============================// `STATE0: begin if(!delete_from_q && insert_in_q) begin next_state=`STATE1; push_fifo=1'b1; error_flag=1'b0 ; sel = 0; end else if(delete_from_q) begin next_state=`STATE0; push_fifo=1'b0; error_flag=1'b1; sel=0; end else begin next_state=`STATE0; push_fifo=1'b0; error_flag=1'b0; sel=0; end end //===============================// //. //. //. default: begin next_state=`STATE0; push_fifo=1'b0; error_flag=1'b0; sel =0; end endcase end
Sample Verilog Code
//sequential part always @(posedge clk or negedge rst_n) if(!rst_n) current_sate <= #1 STATE0; else current_state <= #1 next_sate;
ASM Implementation
Example: Mealy Machine- State Diagram, ASM Representation

s 00 out = 0
in 0
Two general implementation methods:

Hardwired Microprogrammed
0/0 1/1
s3
0/0
s0
out = 1
1/0
s1
0/0
out = 0 0 out =
Two representation of Hardwired

State Diagram Algorithmic State Machine
1/0
s2
1/0
s1 s3
out = 0
01
0/0
out = 0 0
Two Types of State Machines

out = 0
Shortcut to VERIWELL.lnk
Mealy State Machine Moor State Machine
out = 0
s2
Example: Moore Machine ASM Representation (Cont.)

s
out =
Hardwired vs. Microprogrammed Control
Hardwired:
composed of combinatorial and sequential circuits that generate complete timing that corresponds with execution of each instruction. time-consuming and expensive to design difficult to modify but fast
i n
s1
1
out =
s2
i n
1
out =
s3
i n
1
out =
s4
i n
1
out = 1
Microprogrammed Control Unit
Substitution of combinational networks of FSM with Programmable Read Only Memory (PROM) The values of all control signals are read from an appropriate address location in PROM. During each clock period, the appropriate level control signals are read from ROM instead of being generated by logic circuitry.
PROM-based State Machine Implementation

INPUTS
X1 X2
Example: Counting Four ONEs

s
out = 1 in
A0 A1 Q A2 A3 A4 A5
OUTPUTS D0 D1 D2 D3 D4
Z1 Z2 Z3 Z4 Z5 0
00 out = 0
0
D
S0
D
State variable
S1
Q Q
S2
register
D D
S3
clk
D5 D6 D7 D8
NEXT STATE VALUE
out = 0
out =
s1 s3
out = 0
01
out = 0 0
Mealy machine: ROM address bits A0-A5 are function of Input x1 and x2 and current states S0-S3
out = 0
Micro-programmed Sate Machine Implementation

current_state input next_state out
Counter-based State Machine Implementation

rst_n Q0 Q1 A0 A1
00 00 01 01 10 10 11 11
0 1 0 1 0 1 0 1
0 0 0 1 1 1 0 0
0 1 1 0 0 1 0 1
0 0 0 0 0 0 0 1
clk
COUNTER
CLR
Qk
Ak
Machine useful only in generating sequence of control Signals without any input
out current_state
Address Lines
out = 0
s2
MICROPROGRAM MEMORY (ROM, PROM, EPROM or EEPROM)
CONTROL BITS (DATA Out) Dm-0
To Architecture
Example: Time shared FIR filter Complete Datapath Design
Design
h0 h1 h2 h3
MUX
xn (shift register)
Load (Shift x)
h
MUX
xn
sel
load_x
X
clk
Data path
rst_n
sel
+
clk
rst_n
Counter based microProgram Controller
yn
clk
Modifications to Counter-based Microcontrollers 1
Counter-based State Machine Implementation cont.

BRANCH VECTOR
COUNTER
Mechanism for changing count sequence begin another sequence under control of microprogram memory
Pk-0 ing eed r res tor nte c Cou put v e in RST_N CLK CLR
Q0 Q1 Qk
A0 A1 Ak
MICROPROGRAM MEMORY (ROM, PROM, EPROM or EEPROM)
Dm-0 LOAD OTHER
als gn l si th tro pa on data C r fo
LOAD
To Architecture
A new branch address is loaded in the counter if load is asserted

Adv. Digital Design By Dr. Shoab A. Khan Adv. Digital Design By Dr. Shoab A. Khan
Modifications to Control-based Microcontrollers 2
Counter-based ASM with Conditional Branching

RESET CLR Q0 Q1 Qk A0 A1
Introduction of decision-making capabilities to microcontroller implementation

Incorporating the branch address in the instruction The counter loads the branch address if the signal load is asserted
SYSCLK
COUNTER
MICROPROGRAM MEMORY
2
K+1
Ak
Words of m+1 bits
CONDITION BRANCH VECTOR
LOAD
Dm-0
BRANCH ADDRESS OTHER
Pk-0
To Architecture
When CONDITION =1 counter is reset with branch address value

Blocking Condition Testing
Counter-based ASM with Conditional Branching cont.

RESET SYSCLK CONDITION FALSE
0 Y
COUNTER
Mux select line controlled by microprogram memory

Example: 2-bit control allowing on selection of two conditional inputs and two signals true and false.
CLR
Q0 Q1 Qk
A0 A1
MICROPROGRAM MEMORY
2
K+1
Ak
Words of m+1 bits
LOAD
Dm-0
BRANCH ADDRESS LOAD SEL OTHER
COND 0 1 COND1
2 3
Pk-0 BRANCH VECTOR
TRUE
SEL
To Architecture
Conditional load
Pipelined Register
sel
00 01 10 11
load
FALSE
(never load branch address)
COND0
(load branch address if COND0 is TRUE)
COND1
(load branch address if COND1 is TRUE)
Often counters are replaced with an ALU based program counter register The critical path of the design is long as it goes from the counter to ROM to architecture to functional units generating COND0 and COND1 to conditional MUX. The critical path can be broken by inserting a pipeline register in the design
TRUE
(unconditional jump: always load branch address)
Counter-based ASM with Pipeline Register

RESET SYSCLK CONDITION FALSE
0
Counter-based System - Summary
CLR
COUNTER
Q0 Q1 Qk
A0 A1
MICROPROGRAM MEMORY
2
K+1
Ak
Words of m+1 bits
LOAD
Dm-0
BRANCH ADDRESS LOAD SEL OTHER
COND 0 1 M Y U COND1 TRUE

2 X 3 SEL
Pk-0 BRANCH VECTOR
PIPELINE SYSCLK REGISTERED
COUNTER
Qk
REGISTER
r t e nt u n me Co ace pl re
To Architecture CLR Q0 Q1 1
MUX sel LOAD
D0 D1 Dk
Q0 Q1 Qk
Faster as long propagation delay loop through counter and architecture is broken by registers Drawback: conditional branches require elaborated control logic to get right timing
LOAD P k-0
CLR
FULL ADDER k+1 bits
SYSCLK
Register-based Advanced Mictroprogrammed Controller 1
Register-based Register-based Controller

uPC REGISTER
Troubleshot counter divided into individual components: incrementer and register

Controllers named after register referred to as microprogram counter register, PC
Replacement for counter
FULL ADDER Incrementer n bits

MICROPROGRAM MEMORY 0 N. A 1 0 0
words
ADDRESS
PC register replaces state variables used to determine the next state (next address to read from microprogram memory
condition 1 condition 1
3 2 0
DATA Out
COND SEL BRANCH ADDRESS
1MUX
COND
OTHER
Selector Between PC and branchaddress

To Architecture
Register-based Advanced Mictroprogrammed Controller 2
Register-based AdvancedMictroprogrammed Controller 3
MUX added on path between next microprogram addresses coming form PC register and Branch
Elimination of problems with clocking scheme of branching
Path between output of PC register and it input (coming from incrementer) similar to parallel counter structure in counter-based
Value applied address lines microprogram memory always incremented and placed in PC register at the end of each clock cycle of
CCMUX controlled by COND SEL field of microinstruction determines which address source to use for the next address of microprogram memory (similarly to Load input to counter in counter-based controllers)
Modifications to Branch Modifications to Branch Address
Register-based SM with Virtual Address Multiplexer

uPC REGISTER
Branch address generated in Second Address Register

Output enable of this register coming trough tri stated buffers from dedicated field of address selection in pipelined register
If address select High, then Second Address Register selected by Next Address (N.A.) MUX If address select Low, then branch address field of pipelined register selected by Next Address (N.A.) MUX
SYSCLK

MICROPROGRAM MEMORY 0 N. A 1 0 0
words
Second Address Register 3 2 0
ADDRESS
DATA Out
COND SEL
BRANCH ADDRESS ADDR OTHER SEL
Benefits: possibility of inputting beginning branching address from external source as well as from the internal instructions in microprogram memory
Register loaded Either from external source
1 condition 1 condition
COND
1MUX
To Architecture
Or pipelined register
Modifications to Register-basedState Machine
Table for Next Address Table for Next Address Logic
Next Address Select field added to microprogram instruction field Determination of the next microprogram address among mPC register, branch address, second address register and next address select
Selection performed by modified NA and COND MUXEs Next address logic combinational circuit transforming codes from Next Address Select field of microinstruction and data from COND MUX into NA MUX select line
Register-based ASM withCondition Code Multiplexer

uPC REGISTER
SYSCLK
Subroutine Subroutine Execution

MICROPROGRAM MEMORY 0 N. 1 A 2
Temporary storage location added for the copy of contents of PC register

2
n
Second Address Register
words
Register referred to as Subroutine Return Address Register
ADDRESS
0 0 1 cond 1 cond
3 2 0
DATA Out
NEXT ADDRESS LOGIC NEXT ADDRESS SELECT BRANCH BRANCH COND OTHER ADDRESS SELECT
Address kept in register allows on returning to next address of microprogram execution after complete subroutine call
COND
1MUX
To Architecture
Register-based Controller with Subroutine Capability
Nested Subroutine Nested Subroutine Execution
Subroutine Return Address Register replaced by Subroutine Return Address Memory of stack structure
Possibility to store more than one return address necessity in implementing nested subroutine calls
Up/down counter (TOP OF STACK) added for stack pointer manipulations
10
Register-based Controller with Nested Subroutine Capability
Complete Microprogrammed Controller
Conclusions Conclusions
Various ways of implementing controllers Memory introduced to allow for microcode base controllers Counter-based microprogrammed controllers simplest but least versatile Register-based microprogrammed controllers allow on branching and subroutines implementations
Solutions to some problems introduced by counterbased controllers
11

Fifo Code

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Adv Digital Design

By Dr. Shoab Ahmed Khan

Design Example: 4 Entry FIFO

4-entry FIFO queue

Sequencing and Control

The art of algorithm to architecture mapping

FIFO Data Path

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Sample Verilog Code

Sample Verilog Code

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Example: Mealy Machine- State Diagram, ASM Representation

Two general implementation methods:

Two representation of Hardwired

Two Types of State Machines

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Mealy State Machine Moor State Machine

Example: Moore Machine ASM Representation (Cont.)

Hardwired vs. Microprogrammed Control

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Microprogrammed Control Unit

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

PROM-based State Machine Implementation

Example: Counting Four ONEs

NEXT STATE VALUE

Adv. Digital Design By Dr. Shoab A. Khan

Micro-programmed Sate Machine Implementation

Counter-based State Machine Implementation

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

MICROPROGRAM MEMORY (ROM, PROM, EPROM or EEPROM)

CONTROL BITS (DATA Out) Dm-0

Example: Time shared FIR filter Complete Datapath Design

Counter based microProgram Controller

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Modifications to Counter-based Microcontrollers 1

Counter-based State Machine Implementation cont.

MICROPROGRAM MEMORY (ROM, PROM, EPROM or EEPROM)

Dm-0 LOAD OTHER

als gn l si th tro pa on data C r fo

A new branch address is loaded in the counter if load is asserted

Modifications to Control-based Microcontrollers 2

Counter-based ASM with Conditional Branching

Introduction of decision-making capabilities to microcontroller implementation

Words of m+1 bits

CONDITION BRANCH VECTOR

When CONDITION =1 counter is reset with branch address value

Blocking Condition Testing

Counter-based ASM with Conditional Branching cont.

Mux select line controlled by microprogram memory

Words of m+1 bits

Pk-0 BRANCH VECTOR

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan

Adv. Digital Design By Dr. Shoab A. Khan