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FEATURES
Low on resistance (300 typical) Fast switching times tON 250 ns maximum tOFF 250 ns maximum Low power dissipation (3.3 mW maximum) Fault and overvoltage protection (40 V to +55 V) All switches off with power supply off Analog output of on channel clamped within power supplies if an overvoltage occurs Latch-up proof construction Break-before-make construction TTL and CMOS compatible inputs
ADG509F
S4B 1 OF 4 DECODER
00035-101
APPLICATIONS
Existing multiplexer applications (both fault-protected and nonfault-protected) New designs requiring multiplexer functions
A0 A1 A2 EN
A0 A1 EN
Figure 1.
GENERAL DESCRIPTION
The ADG508F, ADG509F, and ADG528F1 are CMOS analog multiplexers, with the ADG508F and ADG528F comprising eight single channels and the ADG509F comprising four differential channels. These multiplexers provide fault protection. Using a series n-channel, p-channel, n-channel MOSFET structure, both device and signal source protection is provided in the event of an overvoltage or power loss. The multiplexer can withstand continuous overvoltage inputs from 40 V to +55 V. During fault conditions, the multiplexer input (or output) appears as an open circuit and only a few nanoamperes of leakage current will flow. This protects not only the multiplexer and the circuitry driven by the multiplexer, but also protects the sensors or signal sources that drive the multiplexer. The ADG508F and ADG528F switch one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1, and A2. The ADG509F switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. The ADG528F has onchip address and control latches that facilitate microprocessor interfacing. An EN input on each device is used to enable or disable the device. When disabled, all channels are switched off.
PRODUCT HIGHLIGHTS
1. Fault Protection. The ADG508F/ADG509F/ADG528F can withstand continuous voltage inputs from 40 V to +55 V. When a fault occurs due to the power supplies being turned off, all the channels are turned off and only a leakage current of a few nanoamperes flows. On channel turns off while fault exists. Low RON. Fast switching times. Break-before-make switching. Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. Trench isolation eliminates latch-up. A dielectric trench separates the p and n-channel MOSFETs thereby preventing latch-up.
2. 3. 4. 5.
6.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 20012009 Analog Devices, Inc. All rights reserved.
REVISION HISTORY
7/09Rev. D: Rev. E Updated Format .................................................................. Universal Added TSSOP ..................................................................... Universal Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 18 4/01Data Sheet Changed from Rev. C to Rev. D. Changes to Ordering Guide ............................................................ 1 Changes to Specifications Table ...................................................... 2 Max Ratings Changed ...................................................................... 4 Deleted 16-Lead Cerdip from Outline Dimensions .................. 11 Deleted 18-Lead Cerdip from Outline Dimensions .................. 12
Rev. E | Page 2 of 20
ADG508F/ADG509F/ADG528F SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V 10%, VSS = 15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range RON +25C B Version 40C to +85C VSS + 3 VDD 1.5 350 400 RON Drift RON Match LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) ADG508F/ADG528F ADG509F Channel ON Leakage ID, IS (ON) ADG508F/ADG528F ADG509F FAULT Output Leakage Current (With Overvoltage) Input Leakage Current (With Overvoltage) Input Leakage Current (With Power Supplies OFF) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 1 tTRANSITION tOPEN tON (EN, WR) tOFF (EN, RS) tSETT, Settling Time 0.1% 0.01% ADG528F Only tW, Write Pulse Width tS, Address, Enable Setup Time tH, Address, Enable Hold Time tRS, Reset Pulse Width 0.6 5 0.02 1 0.04 1 1 0.04 1 1 0.02 2 0.005 2 0.001 2 Unit V min V max typ max %/C typ % max nA typ nA max nA typ nA max nA max nA typ nA max nA max nA typ A max A typ A max A typ A max V min V max A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max s typ s typ ns min ns min ns min ns min
Rev. E | Page 3 of 20
Test Conditions/Comments
300
10 V VS +10 V, IS = 1 mA; VDD = +15 V 10%, VSS = 15 V 10% 10 V VS +10 V, IS = 1 mA; VDD = +15 V 5%, VSS = 15 V 5% VS = 0 V, IS = 1 mA VS = 0 V, IS = 1 mA VD = 10 V, VS = +10 V; See Figure 22 VD = 10 V, VS = +10 V; See Figure 23 VS = VD = 10 V; See Figure 24
50 60 30 60 30
VS = 33 V, VD = 0 V, see Figure 23 VS = 25 V, VD = +10 V, see Figure 25 VS = 25 V, VD = VEN = A0, A1, A2 = 0 V See Figure 26
VIN = 0 or VDD
RL = 1 M, CL = 35 pF; VS1 = 10 V, VS8 = +10 V; see Figure 27 RL = 1 k, CL = 35 pF; VS = 5 V; see Figure 28 RL = 1 k, CL = 35 pF; VS = 5 V; see Figure 29 RL = 1 k, CL = 35 pF; VS = 5 V; see Figure 29 RL = 1 k, CL = 35 pF; VS = 5 V
100
ADG508F/ADG509F/ADG528F
Parameter Charge Injection OFF Isolation CS (OFF) CD (OFF) ADG508F/ADG528F ADG509F POWER REQUIREMENTS IDD ISS
1
Test Conditions/Comments VS = 0 V, RS = 0 ,CL= 1 nF; see Figure 32 RL = 1 k, CL = 15 pF, f = 100 kHz; VS = 7 V rms; see Figure 33
0.2 0.1
mA max mA max
VIN = 0 V or 5 V
TRUTH TABLES
Table 2. ADG508F Truth Table
A2 X 0 0 0 0 1 1 1 1
X = Dont Care
A1 X 0 0 1 1 0 0 1 1
A0 X 0 1 0 1 0 1 0 1
EN 0 1 1 1 1 1 1 1 1
ON Switch None 1 2 3 4 5 6 7 8
A0 X 0 1 0 1
EN 0 1 1 1 1
ADG508F/ADG509F/ADG528F
TIMING DIAGRAMS
Figure 2 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR.
3V WR 0V 50% 50%
tW tS tH
2V 0.8V
00035-002
3V A0, A1, A2 EN
0V . Figure 2. ADG528F Timing Sequence for Latching the Switch Address and Enable Inputs
Figure 3 shows the reset pulsewidth, tRS, and the reset turnoff time, tOFF (RS). Note that all digital input signals rise and fall times are measured from 10% to 90% of 3 V. tR = tF = 20 ns.
3V RS 0V 50% 50%
SWITCH OUTPUT 0V
0.8VO
Rev. E | Page 5 of 20
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. E | Page 6 of 20
WR 1 A0 2 EN 3 VSS 4 S1 5
00035-004
18 RS 17 A1 16 A2 15 GND
ADG508F
14 GND
ADG528F
S8
11 S7
NC
RS
20
A0
16 A1 15 GND
ADG509F
14 VDD
EN VSS S1 S2 S3
4 5 6 7 8 9
PIN 1 INDENTFIER
A1
19 18 17
A2 GND VDD S5 S6
ADG528F
TOP VIEW (Not to Scale)
16 15 14
10 S4B 9
DB
10
11
12
13
00035-007
S4
S8
NC = NO CONNECT
Rev. E | Page 7 of 20
NC
S7
RON ()
RON ()
1000 750
TA = 85C 500
TA = 125C
10
0 VD, VS (V)
10
15
15
OPERATING RANGE
OPERATING RANGE
10p 1p 50
10p 1p 50
40
30
20
40
50
60
40
30
20
30
40
50
60
Figure 9. Input Leakage Current as a Function of VS (Power Supplies Off) During Overvoltage Conditions
Figure 12. Input Leakage Current as a Function of VS (Power Supplies On) During Overvoltage Conditions
0.2
OPERATING RANGE
10p 1p 50
40
30
20
40
50
60
0.2 14
10
2 2 VS, VD (V)
10
14
Figure 10. Output Leakage Current as a Function of VS (Power Supplies On) During Overvoltage Conditions
Rev. E | Page 8 of 20
00035-011
250
ADG508F/ADG509F/ADG528F
100 VDD = +15V VSS = 15V VD = +10V VS = 10V
10
tON (EN)
1 IS (OFF)
tTRANSITION
0.1
ID (ON)
00035-014
125
100
25
45
65 85 TEMPERATURE (C)
105
125
tON (EN)
10
11
14
15
Rev. E | Page 9 of 20
00035-016
120
tOFF (EN)
ADG508F/ADG509F/ADG528F TERMINOLOGY
VDD Most Positive Power Supply Potential. VSS Most Negative Power Supply Potential. GND Ground (0 V) Reference. RON Ohmic Resistance between D and S. RON Drift Change in RON when temperature changes by one degree Celsius. RON Match Difference between the RON of any two channels. IS (OFF) Source leakage current when the switch is off. ID (OFF) Drain leakage current when the switch is off. ID, IS (ON) Channel leakage current when the switch is on. VD (VS) Analog Voltage on Terminals D, S. CS (OFF) Channel input capacitance for off condition. CD (OFF) Channel output capacitance for off condition. CD, CS (ON) On Switch Capacitance. CIN Digital Input Capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. tOPEN OFF time measured between 80% points of both switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. IDD Positive Supply Current. ISS Negative Supply Current.
Rev. E | Page 10 of 20
VSS
Q1
Q2
Q3
VDD
Q1
Q2
Q3
Q1
Q2
Q3
Rev. E | Page 11 of 20
00035-020
00035-019
00035-018
00035-017
V1
S1 S2 S8
ID (ON)
A
VD EN 2.4V
00035-025
S VS
D
VS
00035-021
RON = V1/IDS
VDD VDD
VSS
A
S1 S2 S8
IS (OFF)
A
S1 S2
VSS D
VS
EN
0.8V
00035-026
VS VD
S8 EN 0.8V
00035-022
0V VDD 0V A2 A1 A0
0V VSS S1
A
VDD VDD
VS
ADG528F*
S8 D WR
00035-027
S1 S2 S8
EN RS
VD EN 0.8V
00035-023
GND
VS
Rev. E | Page 12 of 20
ADG508F/ADG509F/ADG528F
VDD VDD A2 VIN 50 A1 A0 2.4V EN RS VSS VSS S1 S2 TO S7 S8 D WR RL 1M CL 35pF VS8 VOUT 90% VOUT 90% *SIMILAR CONNECTION FOR ADG508F/ADG509F. VS1 3V ADDRESS DRIVE (VIN) 50% 50%
ADG528F*
GND
tTRANSITION
tTRANSITION
VSS VSS S1 S2 TO S7 VS
ADG528F* S8
D WR RL 1k CL 35pF VOUT VOUT 80% 80%
2.4V
RS EN GND
VSS VSS S1 S2 TO S8 VS
ADG528F*
D WR RL 1k CL 35pF VOUT
tOFF (EN)
VO
OUTPUT 0V
00035-030 00035-031
0.9VO
tON (EN)
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
VSS VSS S1 S2 TO S8 VS
3V WR 0V 50%
ADG528F
D GND RL 1k CL 35pF VOUT
tON (WR)
VO
OUTPUT 0.2VO 0V
EN RS WR
VRS
VWR
Rev. E | Page 13 of 20
00035-029
tOPEN
00035-024
ADG508F/ADG509F/ADG528F
VDD VDD A2 A1 A0 2.4V EN RS VIN GND WR VSS VSS S1 S2 TO S8 VS 3V RS 0V 50% 50%
ADG528F*
D RL 1k CL 35pF VOUT
VO
SWITCH OUTPUT 0V
00035-032
VSS VSS RS 2.4V 3V LOGIC INPUT (VIN) 0V VOUT CL 1nF WR VOUT QINJ = CL VOUT VOUT
ADG528F*
D
ADG528F*
D VSS VSS RL 1k
VOUT
Rev. E | Page 14 of 20
00035-034
00035-033
0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.015 (0.38) MIN 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
COMPLIANT TO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 34. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-16) Dimensions shown in inches and (millimeters)
10.00 (0.3937) 9.80 (0.3858)
16 1 9 8
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
45
COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
060606-A
Figure 35. 16-Lead Standard Small Outline Package [SOIC-N] Narrow Body (R-16) Dimensions shown in millimeters and (inches)
Rev. E | Page 15 of 20
073106-B
ADG508F/ADG509F/ADG528F
10.50 (0.4134) 10.10 (0.3976)
16
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
45
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 36. 16-Lead Standard Small Outline Package [SOIC-W] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
0.920 (23.37) 0.900 (22.86) 0.880 (22.35)
18 1 10
0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.015 (0.38) MIN 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 37. 18-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-18) Dimensions shown in inches and (millimeters)
Rev. E | Page 16 of 20
070706-A
032707-B
ADG508F/ADG509F/ADG528F
0.048 (1.22 ) 0.042 (1.07)
3 19 18
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) MIN 0.021 (0.53) 0.013 (0.33) 0.020 (0.50) R
PIN 1 IDENTIFIER
TOP VIEW
(PINS DOWN) 8 14 9 13
0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.045 (1.14) R 0.025 (0.64) 0.120 (3.04) 0.090 (2.29)
BOTTOM VIEW
(PINS UP)
0.020 (0.51) R
COMPLIANT TO JEDEC STANDARDS MO-047-AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20) Dimensions shown in inches and (millimeters)
5.10 5.00 4.90
16
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
Figure 39. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
Rev. E | Page 17 of 20
ADG508F/ADG509F/ADG528F
ORDERING GUIDE
Model ADG508FBN ADG508FBNZ ADG508FBRN ADG508FBRNREEL7 ADG508FBRNZ ADG508FBRNZREEL7 ADG508FBRW ADG508FBRWZ ADG508FBRWZ-REEL ADG508FBRUZ ADG508FBRUZ-REEL7 ADG509FBN ADG509FBNZ ADG509FBRN ADG509FBRNREEL7 ADG509FBRNZ ADG509FBRNZREEL7 ADG509FBRW ADG509FBRW-REEL ADG509FBRWZ ADG509FBRWZ-REEL ADG509FBRUZ ADG509FBRUZ-REEL7 ADG528FBN ADG528FBNZ ADG528FBP ADG528FBP-REEL ADG528FBPZ Temperature Range 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C Package Description 16-Lead PDIP 16-Lead PDIP 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead TSSOP 16-Lead TSSOP 16-Lead PDIP 16-Lead PDIP 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead TSSOP 16-Lead TSSOP 18-Lead PDIP 18-Lead PDIP 20-Lead PLCC 20-Lead PLCC 20-Lead PLCC Package Option N-16 N-16 R-16 R-16 R-16 R-16 RW-16 RW-16 RW-16 RU-16 RU-16 N-16 N-16 R-16 R-16 R-16 R-16 RW-16 RW-16 RW-16 RW-16 RU-16 RU-16 N-18 N-18 P-20 P-20 P-20
Rev. E | Page 18 of 20
ADG508F/ADG509F/ADG528F NOTES
Rev. E | Page 19 of 20
ADG508F/ADG509F/ADG528F NOTES
20012009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00035-0-7/09(E)
Rev. E | Page 20 of 20