T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y

(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

1. BASIC STRUCTURE OF COMPUTERS

OBJECTIVE TYPE QUESTIONS: 1. Those attributes of the system which is visible to programmer is referred as: a. Computer organization b. Computer architecture c. Computer fundamental d. Computer manufacturing 2. ____ is to fetch the instruction stored in main memory. a. Output unit b. Input unit c. Memory unit d. Control unit 3. Which of the following is the best unit for performing the arithmetic operations? a. CPU b. ALU c. MMU d. PCU 4. Data and instructions are stored in _____. a. Memory unit

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

b. Control unit c. Input unit d. Output unit

5. ----------------- provide a path for moving data between system modules a. Data lines b. Address lines c. Control lines d. None of the above 6. What is the full form of PCI? a. Peripheral Computer Interface b. Personal Computer Interface c. Personal Computer Introduction d. Peripheral Component Interconnect 7. SCSI has given following numbers of Standards: a. 3 b. 2 c. 1 d. 6 SHORT ANSWER QUESTIONS: 1. What are the different generations of computer?

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

Ans: Generation 1: Vacuum tube Generation 2: Transistor Generation 3: Small- and medium-scale integration Generation 4: Large-scale integration Generation 5: Very-large-scale integration 2. Explain (I) ENIAC (II) UNIVAC. Ans: ENIAC(Electronic Numerical Integrator and Computer) was the worlds first general-purpose electronic digital computer. I was a decimal rather than a binary machine. Its memory consisted of 20 accumulators, capable of holding a 10-digit decimal number. A ring of 10 vacuum tubes represented each digit. Drawback of ENIAC: Had to be programmed manually by setting switches and plugging and unplugging cables. UNIVAC: UNIVAC I (Universal Automatic Computer) was commissioned by the Bureau of the Census for the 1950 calculations. Moreover, it was the first commercial computer. It was intended for both scientific and commercial applications. UNIVAC II was then delivered in the late 1950s and had greater memory capacity and higher performance than the UNIVAC I 3. State the difference between computer organization and computer Architecture Ans: Computer Architecture: Refers to those attributes of the system which is visible to programmer. Computer Organization: Refers to the operational units and their interconnections.

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

4. What are different types of computers? Ans: i. Micro computers ii. Mini computers iii. Desktop computers iv. Mainframes or enterprise systems v. Portable notebook computers vi. Workstations v. Servers vi. Supercomputers 5. Define a bus? Ans: A bus is a communication pathway connecting two or more devices. A key characteristic of a bus is that it is a shared transmission medium. Typically, a bus consists of multiple communication pathways, or lines. Each line is capable of transmitting signals representing binary 1 and binary 0 6. Differentiate synchronous and asynchronous bus. Ans: Synchronous bus: The occurrence of events on the bus is determined by a clock Asynchronous bus: The occurrence of one event on the bus follows and depends on the occurrence of a previous event. SUBJECTIVE QUESTIONS: 1. Write in detail the functional units of a computer? (Refer 1.2 of Computer Organization by Carl Hamacher, Zvonko Vranesic, Safwat Zaky(5th edition)) 2. Write detailed notes on bus interconnection scheme? (Refer 3.4 Computer organization & Architecture by William Stallings(6th edition)) 3. Draw and explain Von Neumann model? 4

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

(Refer The Von Neumann machine of section 2.1 in William Stallings) 4. Explain the PCI bus structure? (Refer 4.7.1 of Carl Hamacher) 5. Write a detailed note on SCSI? (Refer 4.7.2 of Carl Hamacher) 6. Explain why multiple-bus hierarchies are required. Explain traditional bus architecture? (Refer the topic Multiple-Bus Hierarchies of section 3.4 in William Stallings) 7. Write notes on a) serial port b) parallel port (Refer 4.6.1 & 4.6.2 of Carl Hamacher)

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

2. ARITHMETIC AND LOGIC UNIT

OBJECTIVE TYPE QUESTIONS: 1. The following is the representation for signed numbers: a. Sign-magnitude b. Sign extension c. 2s complement d. Both a and c 2. Find 2s two complement of (10100011) 2 a. 01100011 b. 10101100 c. 01010011 d. 01011101 3. What is the base of Hexadecimal system? a. 2 b. 16 c. 4 d. 8 4. What is the base of Decimal System? a. 10 b. 2 c. 4 d. 8 5. If a decimal no is positive, so what will be the sign digit no in binary 6

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

a. 1 b. 2 c. 3 d. 0 6. In which format, zero has a definite representation a. Mash format b. DE format c. Both one (above) d. IEEE format SHORT ANSWER QUESTIONS: 1. Define half adder and full adder Ans: Half adder: This is a logic circuit which performs the addition of two binary digits and produces a sum and a carry output. Full adder: This is a logic circuit which performs addition of three bits(two significant bits and a previous carry) and produces a sum and a carry output. 2. Define ripple carry adder? Ans: Ripple carry adder can be constructed using a number of full adder circuits connected in parallel. The carry output of each adder is connected to the carry output of the next higher-order adder. Either a half-adder can be used for the least significant position or the carry input of a full adder is made 0 because there is no carry into the least significant pos[ition. 3. State the principle of carry look ahead adder. Ans: This adder utilizes logic gates to look at the lower-order bits of the augend and addend to see if a higher-order carry is to be generated. It 7

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

uses two functions: carry generate and carry propagate which are as follows: P i= A i B i G i= A iB i Now the sum and carry can be expressed as S i= P i C i Ci+1= Gi + Pi Ci Gi is called a carry generate and it produces on carry when both A i and Bi are one, regardless of the input carry. P i is called carry propagate because it is associated with the propagation of the carry from C i to Ci+1 4. Define the algorithm used for signed multiplication Ans: A powerful algorithm for signed-number multiplication is Booths algorithm, which generates a 2n-bit product and treats both positive and negative numbers uniformly. This algorithm suggests that we can reduce the number of operations required for multiplication by representing multiplier as a difference between two numbers. 5. State the difference between restoring and non-restoring algorithm Ans: Restoring algorithm: -Does not need restoring of remainder -Slower algorithm Non-restoring algorithm: -Needs restoring of remainder if it is -ive -Faster algorithm 6. Give the normalized form of 1101.1000 Ans: 1.1011000 x 23 7. Define mantissa underflow and overflow? Ans: Mantissa underflow: In the process of aligning mantissa, digits may flow off the right end of the mantissa. In such case truncation methods are used. 8

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

Mantissa overflow: The addition of two mantissas of the same sign may result in a carryout of the most significant bit. If so, the mantissa is shifted right and the exponent is incremented. 8. Define exponent underflow and overflow? Ans: Exponent underflow: This occurs when a negative exponent exceeds the maximum possible exponent value. In such cases, the number is designated as zero. Exponent overflow: This occurs when a positive exponent exceeds the maximum possible exponent value. In some systems this may be designated as + or -. 9. Define Guard bits? Ans: These are extra bits provided in the intermediate steps of floatingpoint arithmetic calculations in order to get maximum accuracy in the final result. 10. What are the three commonly used methods of truncation? Ans: Chopping, Von Neumann rounding, Rounding. SUBJECTIVE QUESTIONS: 1. Explain Booths algorithm with flowchart and an example? (Refer the topic Twos complement multiplication in section 9.3 of William Stallings) 2. Explain restoring division method with an example? (Refer the topic Restoring Division in section 6.6 of Carl Hamacher) 3. Explain non-restoring division method with an example? (Refer the topic Non-restoring Division in section 6.6 of Carl Hamacher) 4. Explain the floating point representation IEEE standard 754? (Refer the topic IEEE standard for binary floating-point representation in section 9.4 of William Stallings) 9

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

5. Explain the algorithm for floating point addition and subtraction? (Refer the topic Addition and Subtraction in section 9.5 of William Stallings) 6. Explain the algorithm for floating point multiplication and division? (Refer the topic Multiplication and Division in section 9.5 of William Stallings) 7. Explain ripple carry adder and carry lookahead adder? (Refer the sections 6.1 & 6.2 of Carl Hamacher)

10

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

3. CENTRAL PROCESSING UNIT

OBJECTIVE TYPE QUESTIONS: 1. What is the correct definition of the term 'CISC'? a. Continual Input System Computer b. Control Independent System Computer c. Central Immediate Source Construct d. Complex Instruction Set Computers 2. Which of the following facts regarding the CISC and RISC architectures is NOT true? a. CISC processors generally have a much larger instruction set than their RISC equivalents b. RISC processors generally cost less to manufacture c. The CISC architecture does not allow variable code lengths d. The RISC architecture does not allow use of complex addressing modes 3. Which one of the following is the user-visible register a. Data Register b. Instruction Register c. Program Counter d. Memory Address Register

11

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

4. ---------------------- typically contains condition codes and other status information a. Program Counter b. Program Status Word c. Instruction Register d. Index Register 5. Micro-operations are described in symbolic notation known as: a. Assemby Language b. Microprogramming Language c. Machine Language d. High-Level Language

SHORT ANSWER QUESTIONS: 1. What is instruction set? Ans: The collection of machine instructions is known as instruction set. 2. What do you mean by addressing modes? Ans: This determines the way of addressing the operands in an instruction. (e.g. Intermediate mode, direct mode, indirect mode, register mode etc.) 3. What is branch target? Ans: This refers to the address to be referenced when the branch is taken. 12

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

4. What are the basic operations performed by processor? Ans: -Fetch instruction -Interpret instruction -Fetch data -Process data -Write data 5. What do you mean by register transfer? Ans: This is defined as the transfer of information between processor registers. For e.g. R3 [R1] + [R2]. Here the contents of registers R1 and R2 are added and the sum is placed into R3. 6. What is micro programming and microprogrammed control unit? Ans: The micro-operations are described in symbolic notations which looks like a programming language and that is known as micro programming language. When the control unit is implemented using this micro programming language it is known as microprogrammed control unit. 7. What are the basic tasks performed by a micro-programmed control unit? Ans: i) Microinstruction sequencing: Get the next instruction from the control memory ii) Microinstruction execution: Generate the control signals needed to execute the microinstruction SUBJECTIVE QUESTIONS: 1. Draw and explain the CPU architecture? (Refer section 12.1 of William Stallings) 2. Write a note on register organization of CPU? (Refer section 12.2 of William Stallings) 13

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

3. Explain the addressing modes supported by IA32? (Refer section 3.16.2 of Carl Hamacher) 4. Explain the IA32 instruction format? (Refer section 3.17.1 of Carl Hamacher) 5. Draw instruction cycle state diagram and explain in detail? (Refer section 12.3 of William Stallings) 6. Explain the characteristics of RISC and CISC? (Refer section 13.4 of William Stallings) 7. Explain hardwired control unit? (Refer section 16.3 of William Stallings) 8. Explain micro-programmed control unit? (Refer section 17.1 of William Stallings) 9. Explain the concepts of nanoprogramming? (Refer section 5.3.4 of Miles Murdocca Computer Arichitecture and Organization)

14

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

4. MEMORY ORGANIZATION
OBJECTIVE TYPE QUESTIONS: 1. In a computer _____ is capable to store single binary bit a. Capacitor b. Flip flop c. Register d. Inductor 2. A set of flip flops integrated together is called ____ a. Counter b. Adder c. Register d. None of the above 5. Separate Read/Write heads are required in which of these memory access schemes. a. Random Access b. Sequential Access c. Direct Access d. None of these 5. A register organized to allow moving left or right operations is called a _____________ a. Counter b. Loader c. Adder d. Shift register 15

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

6. Which of the following are the cheapest memory devices in terms of Cost/Bit? a. Semiconductor Memories b. Magnetic Disks c. Magnetic Tapes d. Compact Disks 7. Which of the following have the fastest access time? a. Semiconductor Memories b. Magnetic Disks c. Magnetic Tapes d. Compact Disks 8. ____is a semi conductor memory a. DRAM b. SRAM c. Bubble d. Both a & b 9. Which of the following is a read only memory storage device. a. Floppy disk b. Hard disk c. CDROM d. None of these SHORT ANSWER QUESTIONS: 1. What is Memory system? 16

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

Ans: Computer memory is capable of storing data and instructions. A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system (directly accessible by the processor) and some external (accessible by the processor via an I/O module) 2. Give classification of memory? Ans: Primary memory: RAM Secondary memory: Hard Disk 3. Define cache and what is its use? Ans: Cache acts as a memory between the processor and the main memory and it contains a copy of portions of main memory. Use: It gives memory speed approaching that of the fastest memories available, and at the same time provides a large memory size at the price of less expensive types of semiconductor memories. 4. Define Random Access Memory? Ans: Random access memory is organized such that each addressable location has a unique, physically wired-in addressing mechanism. The time to access a given location is independent of the sequence of prior accesses and is constant. Thus, any location can be selected at random and directly addressed and accessed. E.g. main memory, some cache systems. 5. What are PROMS? Ans: Like ROM, PROM(Programmable Read Only Memory) is nonvolatile and may be written into only once. The writing process is performed electrically and may be performed by a supplier or customer at a time later than the original chip fabrication. 6. Define Memory refreshing? 17

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

Ans: Memory refreshing is the process of restoring the capacitor charge to its full value. This is done in DRAMs since the charge in the capacitor can be maintained for only tens of milliseconds. 7. What is Volatile memory? Ans: Information stored in this type of memory is retained as long as there is electrical power. When power is switched off the stored information is lost. 8. Define data transfer or bandwidth? Ans: The number of bits or bytes that can be transferred in one second is referred to as bandwidth. 9. What is Flash memory? Ans: Flash memory is similar to EEPROM in which the flash cell is based on a single transistor controlled by trapped charge. The difference between flash memory and EEPROM is that in EEPROM it is possible to read and write the contents of a single cell, whereas in flash device it is possible to read the contents of a single cell, but it is only possible to write the entire block of cells. Flash memory consumes less power and it is used in hand-held computers, cell phones, digital cameras and MP3 music players. 10. What are multilevel memories? Ans: Multilevel memories are implemented in computer systems by equipping them with a hierarchy of memory subsystems, some internal to the system (directly accessible by the processor) and some external (accessible by the processor via an I/O module) 11. Define Seek time and rotational latency? Ans: Seek time is the time required to move the disk arm to the required track. Rotational delay or latency is defined as the time taken for the beginning of the sector to reach the read/write head. 18

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

12. What is DVD? Ans: DVD (Digital Versatile Disk) is a storage device which can store videos. It takes video into digital age by replacing the video tape used in video cassette recorders. It delivers movies with impressive picture quality, and it can be randomly accessed like audio CDs, which DVD machines can also play. Also DVD has huge storage capacity and vivid quality. 13. Define Magneto Optical Disk? Ans: A magneto-optical drive is a kind of optical disc drive capable of writing and rewriting data upon a magneto-optical disc. Both 130 mm (5.25 in) and 90 mm (3.5 in) form factors exist. The technology was introduced commercially in 1985. Although optical, they appear as hard disk drives to the operating system and do not require a special file system; they can be formatted as FAT, HPFS, NTFS, etc. Magneto optical drives are common in some countries such as Japan but have fallen into disuse in other countries like the United States. 14. Define Virtual Memory? Ans: Virtual memory is implemented by swapping in and swapping out of pages from main memory into hard disk. With virtual memory it is possible for a process to be larger than all of main memory 15. Distinguish between Static and Dynamic RAM? Ans: Static RAMs are capable of retaining their state as long as power is applied and there is no need for memory refreshing. But in the case of DRAMs the information stored in the form of charge on a capacitor can be maintained for only tens of milliseconds. Hence in DRAM memory refreshing is required. 16. Define the term LRU and LFU? 19

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

Ans: LRU (Least Recently Used) is a page replacement technique and here, the block which has been in the cache longest with no reference to it, is selected for the replacement. LFU (Least Frequently Used) is a page replacement technique and here, the block in the cache which has the fewest references is selected for the replacement. SUBJECTIVE QUESTIONS: 1. Write a note on the characteristics of memory system and its hierarchy? (Refer section 4.1 of William Stallings) 2. Explain the different types of ROM? (Refer section 5.3 of Carl Hamacher) 3. Explain the different types of RAM? (Refer section 5.2 of Carl Hamacher) 4. Write a note on cache organization? (Refer section 5.5 of Carl Hamacher) 5. Explain the different mapping techniques of cache memory? (Refer section 5.5.1 of Carl Hamacher) 6. Write a short note on a) Associative memory (Refer section 4.12.1 of Computer Organization & Architecture by A.P. Godse and D.A. Godse) b) Interleaved memory (Refer section 5.6.1 of Carl Hamacher) 7. Explain the replacement algorithms for cache memory? (Refer the topic Replacement algorithms in section 4.3 of William Stallings) 8. Explain the technique of page translation mechanism? (Refer the topic Paging in section 8.3 of William Stallings) 9. Explain TLB? 20

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

(Refer the topic Translation Lookaside Buffer in section 8.3 of William Stallings) 10. Explain RAID levels? (Refer section 6.2 of William Stallings) 11. Write a note on a) demand paging b) segmentation (Refer the topics Demand paging & Segmentation in section 8.3 of William Stallings)

21

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

5. I/O ORGANIZATION
OBJECTIVE TYPE QUESTIONS: 1. The input or output device attached to your computer is also called: a. Electromechanical devices b. Electromagnetic devices c. Peripheral devices d. Electronic devices 2. When the DMA takes control of the bus system, it communicates directly with the CPU: a. True b. False 3. Cycle stealing is the technique implemented by which of these components in the system. a. DMA b. Programmed I/O c. Interrupt driven I/O 4. Which of these is not a type of interrupt? a. Internal interrupt b. External interrupt c. Hardware interrupt d. Software interrupt

22

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

5. The I/O bus consists of: a. Data lines b. Address lines c. Control lines d. All of the above 6. Which of these flags appear in the processor register a. Zero flag b. Carry flag c. Sign flag d. Parity flag e. All of the above 7. Which of these interrupts are also called as traps? a. Internal interrupt b. Software interrupt c. External interrupt SHORT ANSWER QUESTIONS: 1. Mention the group of lines in the system bus. Ans: Address lines, Data lines, Control lines 2. What are bus master and slave? Ans: Bus master is the device which holds the bus and the devices to which the master initiates the data transfer are known as slaves. 3. What is bus arbitration? Ans: Bus arbitration is the process of granting access to the bus for a device when more than one device need control of the bus. 23

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

4. Mention types of bus arbitration. Ans: i) Centralized: In this scheme a single hardwire device referred to as a bus arbiter or controller is responsible for allocating time on the bus. The device may be separate module or part of the processor. ii) Distributed: In this scheme there is no central controller. Rather, each module contains access control logic and the modules act together to share the bus. 5. What is DMA? Ans: DMA (Direct Memory Access) is an I/O technique which involves an additional module on the system bus. The DMA module is capable of mimicking the processor and indeed, of taking over control of the system from the processor. It needs to do this to transfer data to and from memory over the system bus. 6. Why does the DMA gets priority over CPU when both request memory transfer? Ans: DMA gets more priority because it is capable of transferring large volumes of data, consuming less number of bus cycles. 7. List out the types of interrupts. Ans: Internal interrupt, External interrupt, Software interrupt. 8. What is the need for DMA transfer? Ans: To reduce the number of bus cycles by integrating the DMA and I/O functions. 9. What is memory-mapped I/O? Ans: With this addressing mechanism, there is a single address space for memory locations and I/O devices. The processor treats the status and data registers of I/O modules as memory locations 24

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

and uses the same machine instructions to access both memory and I/O devices. 10. List down the functions performed by an Input/Output module. Ans: -Control and Timing -Processor communication -Device communication -Data buffering -Error detection SUBJECTIVE QUESTIONS: 1. Write notes on i) Programmed I/O ii) Interrupt driven I/O (Refer sections 7.3 & 7.4 of William Stallings) 2. Explain DMA in detail? (Refer section 7.5 of William Stallings) 3. Explain USB in detail? (Refer 4.7.3 of Carl Hamacher) 4. Explain about I/O channels? (Refer section 7.6 of William Stallings)

25

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

6. MULTIPROCESSOR CONFIGURATION
OJECTIVE TYPE QUESTIONS: 1. What is the correct definition of the term 'SIMD'? a. Single Input, Multiple Destinations b. Single Integration, Multiple Dynamics c. Single Instruction, Multiple Data d. Single Interrupt, Multiple Distribution 2. Overlapping the independent stages of different instructions is known as: a) Vector processing b) Pipelining c) Array processing d) All of the above 3. Which one of the following is a technique to avoid data hazards? a) Operand forwarding b) Internal data forwarding c) Store-Load forwarding d) Load-Load forwarding 4. In which group of computers, there are more than one processor units having the ability to execute several programs simultaneously a) SISD b) MIMD

26

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

c) SIMD d) MISD 5. When two instructions contend for the same functional unit, the following occurs a) Data dependency b) Branch difficulties c) Resource conflicts d) All of the above 6. Which one of the following is an approach to deal with conditional branching a) Delayed branching b) Static branch prediction c) Dynamic branch prediction d) All of the above 7. Cache miss is an example for --------------------a) Data hazard b) Instruction hazard c) Structural hazard SHORT ANSWER QUESTIONS: 1. What is parallel processing? Ans: Parallel processing increases system performance by making use of multiple processors that can execute in parallel to support a given workload. 2. State the basic ways by which we can achieve parallelism? 27

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

Ans: Parallelism can be achieved by providing more functional units. Superscalar processors can be quoted as an example. 3. What is instruction pipeline? Ans: Instruction pipeling is overlapping the stages of instruction execution. The stages include fetch, decode, execute, write result. 4. What are pipeline hazards? Ans: The time wasted due to a stall in the pipeline is known as pipeline hazard. Stall is created due to data dependencies between instructions 5. What is branch penalty? Ans: Branch penalty defines the wastage of time due to wrong prediction of branch instructions. 6. What do you mean by branch prediction? Ans: Branch prediction is a technique to deal with conditional branches. It is the process of fetching both the next sequential instruction after a branch and speculatively fetching the branch target instruction. 7. What is instruction-level parallelism? Ans: The term instruction-level parallelism refers to the degree to which, on average, the instructions of a program can be executed in parallel. A combination of compiler-based optimization and hardware techniques can be used to maximize instruction-level parallelism. 8. What is register renaming? Ans: This is a technique to cope up with storage conflicts like antidependency and output dependency. Here, a new register is allocated for each newly created register value i.e. duplication of resources. 28

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

SUBJECTIVE QUESTIONS: 1. Explain Flynns Classification for parallel processing system? (Refer section 18.1 of William Stallings) 2. Draw and explain six-stage instruction pipeline? (Refer the topic Pipelining strategy in section 12.4 of William Stallings) 3. Write a note on pipeline hazards? (Refer sections 8.1.2, 8.2 & 8.3 of Carl Hamacher) 4. Explain the limitations of instruction-level parallelism? Five limitations are: -True data dependency -Procedural dependency -Resource conflicts -Output dependency -Antidependency (Refer sections 14.1 & 14.2 of William Stallings) 5. Explain the various superscalar instruction issue policies? (Refer the topic Instruction Issue Policy in section 14.2 of William Stallings)

29

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

7. SPARC
OBJECTIVE TYPE QUESTIONS: 1. ------------------- is an example of shared memory multiprocessor organization a. Symmetric multiprocessors b. Non-Uniform Memory Access c. Clusters d. Both a and b 2. Which of the following is an example for Fault Tolerant Computers a. The Tandem Nonstop b. The Tandem VLX c. The Tandem Himalaya d. All of the above 3. Interprocessor communication is achieved by a. Using handshake protocols b. Using shared variables c. Using message passing d. Both b and c 4. What is MESI a. Mutual Exclusive Shared Invalid b. Modified Exchange Shared Invalid c. Modified Exclusive Shared Invalid d. Mutual Exclusive Shared Input 30

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

SHORT ANSWER QUESTIONS: 1. What is data flow computer organization? Ans: In data flow computers, the instructions are executed according to the availability of data. Any instruction should be ready for execution whenever operands become available. Here, the instructions are not ordered in any way. So, no program counters are needed in these computers. 2. What is tightly coupled multiprocessor and loosely coupled multiprocessor? Ans: In tightly coupled multiprocessor individual data elements constitute the level of interaction, and there can be a high degree of cooperation between processes. In loosely coupled multiprocessors, the physical unit of interaction is usually a message or complete file. 3. What are the two policies of snoopy protocol? Ans: i) Write invalidate: Multiple readers but only one writer at a time. ii) Write update (or write broadcast): Multiple readers as well as multiple writers to a cache. 4. How interprocessor synchronization can be obtained? Ans: There are two ways by which interprocessor communication is achieved: i. Using shared variables ii. Using message passing 5. What is cache coherence? Ans: Cache coherence is defined as the consistency of data in different levels of caches in multiprocessor configuration. 31

T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

6. What is cache coherence protocol? Ans: Cache coherence protocol is a hardware-based solution for cache coherence problems existing in multiprocessor configurations. This solution provides dynamic recognition at run time of potential inconsistency conditions. SUBJECTIVE QUESTIONS: 1. Write a short note on: a) Static Data Flow design b) Dynamic data flow design (Refer sections 8.1.1 & 8.1.2 of Computer Organization & Architecture by A.P. Godse and D.A. Godse) 2. Explain about fault tolerant computers. (Refer section 8.3 of Computer Organization & Architecture by A.P. Godse and D.A. Godse) 3. Explain cache coherence protocols. (Refer section 18.3 of William Stallings) 4. Explain interprocessor communication and synchronization? (Refer section 8.6 of Computer Organization & Architecture by A.P. Godse and D.A. Godse) 5. Explain the shared memory multiprocessor configuration? (Refer sections 18.2 & 18.5 of William Stallings)

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T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

8. SYSTOLIC ARCHITECTURES
OBJECTIVE TYPE QUESTIONS: 1. Which mechanism controls wave front arrays a) Clock timing b) Handshaking c) Branching d) Pipelining 2. Name the processor organization which consists of a large number of uniform processors connected in an array topology controlled by a central clock a) Systolic processors b) Closely coupled multiprocessors c) Loosely coupled multiprocessors d) Parallel processors SHORT ANSWER QUESTIONS: 1. What is systolic architecture? Ans: Systolic architecture consists of a large number of uniform processors connected in an array topology, called systolic arrays. The individual processors take inputs from the top and left, perform a specified operation and output the results to the right and bottom. Processing or firing at each of the processors occurs simultaneously in synchronization with a central clock. The name comes from the fact that each processor fires on this heartbeat.

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T h a k u r C o lle g e o f E n g in e e r in g & T e c h n o lo g y
(A p p r o v e d b y A IC T E , G o v t. o f M a h a ra s h tr a & A ffilia te d to U n iv e r s ity o f M u m b a i) IS O 9 0 0 1 : 2 0 0 8 C e r tifie d S h y a m n a r a y a n T h a k u r M a r g , T h a k u r V i ll a g e , K a n d i v l i ( E ) , M u m b a i 4 0 0 1 0 1 . T e l: + 9 1 2 2 2 8 4 6 1 8 9 1 , 2 8 4 6 1 8 9 2 / T e le fa x : + 9 1 2 2 2 8 4 6 1 8 9 0 E m a i l: t c e t @ t h a k u r e d u c a t io n . o r g / W e b s it e : w w w . t h a k u r e d u c a t i o n . o r g

Z a g d u S in g h C h a r it a b l e T r u s t s ( R e g d .)

2. List the applications of systolic array. Ans: The systolic arrays are designed to implement various complex arithmetic operations such as: i. Convolution ii. Matrix multiplication iii. Solving linear equations 3. State the difference between systolic arrays and wave front arrays Ans: The operation of systolic arrays is controlled by a global clock whereas in wave front arrays it is done by asynchronous handshaking mechanism. SUBJECTIVE QUESTIONS: 1. Explain in detail about Systolic architecture? (Refer sections 9.1 & 9.2 of Computer Organization & Architecture by A.P. Godse and D.A. Godse) 2. Explain Wave front arrays? (Refer section 9.3 of Computer Organization & Architecture by A.P. Godse and D.A. Godse)

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