When does a system need terminating resistors?

According to Chapter 4, there are two

cases: the long reflection case and the short ringing case.
When a line is long, meaning the cable length exceeds one-sixth of the electrical
length of a rising edge, the cable needs terminators. Without terminators, reflections at either
end of a long cable render signal transmission impossible. Chapter 4, Section 4.3, shows how
to precisely determine the effect of signal reflection. Section 4.3.5 proposes a simple mathe-
matical test for determining the duration of reflections when a line is left not terminated.
When a line is short, it may still need terminators if it drives a capacitive load. Sec-
tion 4.1 analyzes highly inductive circuits which are capacitively loaded, showing the
effect of high-Q ringing. The ringing phenomenon in short lines has the same practical
effect as reflections in long lines.
Resistive terminators can cure problems with either reflections or ringing.
This chapter addresses three main topics:

Comparison of end versus series termination

Selection of appropriate terminating resistors
Crosstalk among terminating components

6.1 END TERMINATORS

When using end terminations, each driving gate connects directly to its transmission line,
with the terminator located at the receiving end (see Figure 6.1). End-terminated lines
have these properties:

(1) The driving waveform propagates at full intensity all the way down the cable.
(2) All reflections are damped by the terminating resistor.
(3) The received voltage is equal to the transmitted voltage.
 224 Terminations Chap. 6

Driving part -- + I < - R e c e ~ v ~ npga r t

-
of c ~ r c u i t of c ~ r c u i t
I

Fat l ~ n er e p r e s e n t s
+5 v p h y s ~ c a lt r a c e
I

Thin line r e p r e s r n t s ~ ~ d ~ 1 t P a~ r a s i t~~ cc a p~a c ~ t ,o rC ~ ~ t ~ ~ ~

deal e l e c t r ~ c r e s ~ s t a n c eof I r e p r e s e n t s load a t
connect~onto that 2, o h m s gate input
I
trace I

Figure 6.1 Calculating the rise time of an end terminator.

6.1 .IRise Time of an End Terminator

W e may deduce the signal rise time of an end-termination circuit by intuitive reasoning
or by more detailed mathematics. We shall attempt the intuitive approach first and then
double check using detailed math.
Our intuitive approach splits the circuit in Figure 6.1 into two parts. The left part,
or driving part, is composed of the driving gate, the transmission line, and the terminating
resistor. W e can model the Thevenin equivalent driving impedance for this part of the cir-
cuit as the impedance of a long transmission line Z,, in parallel with the terminating resis-
tor (also Z,). The net effect, for short-term events, is a drive impedance of Zd2Q.
The right part, o r receiving part, includes only the receiving gate, modeled in Figure
6.1 as a capacitor. This capacitive model is appropriate for most CMOS, TTL, or ECL sit-
uations. Recognizing this circuit as a simple RC filter, we know the RC time constant:

zo C
RC time constant = -
2
Using the formula from Section 3.1 for the 10-90% rise time of an RC filter,

Given an incoming signal with a rise time of T , , we combine it with the rise time of
the termination circuit Termto find the resulting actual rise time at point B:

When a line is long compared to a rising edge, the impedance of its output is effec-
tively Z,.If we shorten the length of a transmission l ~ n edown to a size comparable to the a

length of its rising edges, the impedance of that line, as seen at B, goes down. Eventually,
for very short lines, the driving impedance at B is just equal to the output impedance of
the driving gate and we get a faster rise time at point B.
i
Sec. 6.1 End Terminators 225

Next let's try a math-intensive method of estimating rise time. Recall that Equation
4.61 from Chapter 4 models the overall response of a transmission line:

If the length of the transmission line exceeds the length of a rising edge, we can
ignore any reflections that may bounce off the end terminator. This is reasonable because
end reflections will not have time to travel to the source, and then rebound back to the far
end again before the effects of the first rising edge have completed their course. We may
have late reflections, but they do not influence the shape of the initial rising edge. Mathe-
matically, to force zero reflections we set the reflection factor R , ( w ) in Equation 6.4 to
zero. We may then simplify Equation 6.4:

Our next simplification assumes the drive impedance is very low compared to the
transmission line characteristic impedance, and so A ( w ) is unity. Further assume the line
is not so long that it disperses the signal, so the magnitude of HX(w)is unity. Incorporat-
ing these simplifications, we have

Finally, rearranging the definition of R2(w) from Equation 4.53 and adding 1:

Next, model the characteristic impedance function Zo(w) as a constant resistance

having value Zo. Finally, note that Z,(w) is composed of the parallel combination of a ter-
minating resistor (also equal to Z,,) and a capacitor of value C. Combining the parallel
components,

And substituting into Equation 6.7,

Equation 6.10 is the response of a simple RC filter having a time constant of

( Z ( j 2 ) Cseconds. This corroborates our intuitive model.
 226 Terminations Chap. 6

The rise time of an end-teriminated circuit, when capacitively loaded, is half that of
a series-terminated line driving the same load (see Section 6.2.2).

6.1.2 DC Biasing of End Terminator

The termination circuit in Figure 6.1 rarely appears in TTL or CMOS circuits because of
the large drive current required in the HI state. When the driving gate in Figure 6.1
switches its output to Vcc, it must supply a current of VcclRl to the terminating resistor.
When the driving gate switches its output to ground, no output current flows. Assuming
we are using typical 65-R transmission lines, the current required for a 5-V drive signal is
5/65 = 76 mA. Very few drivers can source that much current.
Compare this drive requirement with the drive capabilities of TTL, which sources
much more current when driving LO than when driving HI, or CMOS which sources
equal amounts of current in both directions.
Figure 6.2 shows a popular terminating arrangement called the split termination. In
this arrangement, the parallel combination of Rl and R2 equals Zo, the characteristic
impedance of transmission line A. The ratio R,IR, controls the relative proportions of HI
and LO drive current. Figure 2.10 presents equations for converting this split termination
into a single resistor and Thevenin equivalent voltage source.

zo

Transmission 11ne @

R 1 in parallel w ~ t hRz Parasitic c a p a c ~ t o rC

equals Zo o h m s r e p r e s e n t s load a t
g a t e input

Figure 6.2 Split termination

If Rl equals R,, the HI and LO drive current requirements are the same. This setting
is appropriate for the HCMOS digital logic family.
If R, exceeds R l , the LO current requirement exceeds the HI current requirement.
This setting is appropriate for TTL and HCT families.
The selection of values for RI and R2 is best done graphically. The selection is con-
trolled by three constraints:

(1) The parallel combination of RI and R2 must equal Z,.

(2) We must not exceed I,, , ,, (maximum high-level output current).
(3) We must not exceed I,, ,,, (maximum low-level output current).
In this example, we use the following convention for output current: Current enter-
ing the driver (sink current) is positive, while current leaving the driver (source current)
Sec. 6.1 End Terminators 227

is negative. A TTL or CMOS gate sinks (positive) current in the low state and sources
(negative) current in its high state. An ECL gate sources (negative) current in both
states.
The first constraint is easily expressed in the admittance domain. Let the variables
Y, and Y2 stand for the admittances of resistors R I and R,, respectively:

We will solve for values of Y, and Y2 and then invert them to find Rl and R, as the
last step. The advantage of this approach is that it makes our constraint equations linear.
The first constraint is graphed in Figure 6.3:

Transform problem
y -'
- R'
to a d m i t t a n c e

10L constraint:
5.06 Y, - 0.44 Y 2 < 0.024

R e g ~ o n sat ~ s f y ~ n g
both current

100 n
ronstralnt
' I
l~ne 65-n c o n s t r a i n t d o e s
not satlsfy both c u r r e ~ > t
c o n s t r a ~ n t sa t a n y p o l n t

Figure 6.3 End-termination constraints.

 228 Terminations Chap. 6

This appears as a diagonal line on the constraint graph (Figure 6.3). All valid com-
binations of Y, and Y, lie on this line.
Derive an equation for the second constraint by noting that the current into the dri-
ver equals the current flowing in R2 minus the current flowing in R I . These two currents
depend on voltages vc, VEE,and the driver output voltage. For generality we use the
symbol Vcc- for the more positive power supply voltage and V, for the more negative
voltage. Often, one or the other of these voltages is zero.
Constraint (2) is calculated using the required HI state driving voltage:

(
C
' - 'OH )V - ('OH - ' E )'2 > IOH ma.x
The direction of the inequality in Equation 6.13 may appear backward, but it isn't.
We expect both sides of Equation 6.13 to be negative (the driver normally sources cur-
rent). Equation 6.13 asks that the actual drive current required be less negative (i.e., more
positive) than the maximum limit I,. The value of I,, ,,, should enter Equation 6.13 as
a negative number.
Constraint (3) is calculated using the LO state output voltage:

(VCC - VOL)Y, - (VOL - V E E ) '2 < IOL,ax [6.14]

The value of I,, ,,, is a positive number for TTL and CMOS. For ECL the value
for I,, ,,, is zero because ECL circuits cannot sink any current.
All three constraints appear in Figure 6.3, calculated for a 74HC 1 1000 NAND gate.
The output voltages and current limits are all evaluated at the maximum power supply
input voltage of 5.5 V (that is usually the worst case). Constraint (1) appears twice, once
for a characteristic impedance of 65 R and again for 100 R . The 100-R constraint line
passes into the good zone of both current constraints near the value (Y, = 0.05, Y2 = 0.05).
This corresponds to resistance values of R l = 200, R , = 200.
The 65-R constraint line does not intersect the region allowed by both current con-
straints. There is no combination of split terminating resistors that will work. The
74HC11000 cannot adequately drive a 65-52 end-terminated transmission line.
Sometimes an end terminator is made using only one resistor leading to a fixed
intermediate voltage provided solely for terminations. The above procedure for designing
split terminations also works for finding a good termination voltage.
First design a split terminating network. Then transform the split termination into a
Thevenin equivalent voltage source. The Thevenin equivalent source impedance will
always turn out to be Zo. The Thevenin equivalent source voltage will be

Use this value as the termination voltage.

6.1.3 Other Topologies Used with End Terminators

The bifurcated line in Figure 6.4 cannot be terminated properly. Regardless of where we place
terminators, signal energy from the driver still reflects off the juncture at A, causing ringing.