Embedded Systems

Lecture 1: Introduction to ARM based Embedded Systems Swagat Kumar Fall Semester, 2011-12 IIT Rajasthan

Books, Reference & Evaluation

Books: ARM Programming, William Hohl ARM System-on-chip Architecture, Steve Furber ARM System Developer's Guide, Sloss, Symes & Wright ARM Architecture Reference Manual Evaluation: 2 Midsems : 40% 1 Endsem : 40% 1 Project : 20% The Lab will have separate Evaluation

RISC Vs CISC
RISC : Reduced Instruction Set Computing o Reduce the complexity of instructions performed by the hardware because it is easier to provide greater flexibility and intelligence in software than in hardware. o Result is a Complex Compiler o Simpler hardware design for Processor CISC: Complex Instruction Set Computing o Relies more on hardware for instruction functionality CISC instructions are complicated o Complicated hardware design for Processor o Simpler Compiler However, at this moment of time the distinction between RISC and CISC has blurred as CISC processor have implemented many RISC concepts.

RISC Design Philosophy

RISC philosophy is implemented with four major design rules: Instructions: 1.Reduced number of instruction classes that provide simple operations that can each execute in a single cycle. Programmer / compiler synthesizes complicated operations (e.g. division) by combining several simple instructions. Each instruction is of fixed length to allow the pipeline to fetch future instructions. (CISC instructions are of variable size & require multiple cycles to execute)

RISC Design Philosophy Contd ...

Pipelines: o Processing of instructions is broken down into smaller units that can be executed in parallel by pipelines. Ideally the pipeline advances by one step on each cycle. (CISC instructions are executed by a miniprogram called microcode.) Registers: o RISC machines have a large general-purpose register set. o Any register can contain either data or address. o Registers act as fast local memory for all data processing operations. o CISC processor have dedicated registers for specific purposes.

RISC Design Philosophy Contd ...

Load-Store Architecture o Processor operates on data held in registers. o Separate Load and Store instructions transfer data between registers and external memory. o Memory accesses are costly, so separating memory access from data processing provides an advantage because you can use data items held in register bank multiple times without needing multiple memory accesses. o CISC data processing instructions can act on memory directly.

ARM Design Philosophy

1. Meant for portable embedded systems 2. ARM processors are designed to reduce power consumption & extend battery life 3. High Code Density - limited memory, physical size restrictions (form factor) 4. Embedded systems are price sensitive - thus use slow and low-cost memory devices 5. ARM incorporates hardware debug technology within the processor which provides greater visibility to the code execution process - reduced developmental cost & time to market 6. ARM Core is not a pure RISC architecture because of the constraints of its primary application - the embedded system.

Instruction Set for Embedded Systems

The ARM instruction set differs from the pure RISC definition in several ways that make the ARM instruction set suitable for embedded applications: Variable cycle execution for certain instructions o e.g. load-store-multiple instruction vary in the number of execution cycles depending on the number of registers being transferred. Inline barrel shifter leading to more complex instructions o inline barrel shifter is a hardware component that preprocesses one of the input registers before it is used by an instruction - improves code density and core performance.

Instruction Set for Embedded Systems

Thumb 16-bit instruction set: o ARM core can execute either 16-bit or 32-bit instructions o 16-bit instructions improve code density by about 30% over 32-bit fixed-length instructions Conditional Execution o An instruction is only executed when a specific condition has been satisfied. This feature improves performance & code density by reducing branch instructions. Enhanced Instructions o The enhanced DSP instructions were added to the standard ARM instruction set to support fast 16x16 multiplier operations and saturation.

Embedded System Hardware

ARM BUS Technology

For x86 PCs, the most common PC bus technology is Peripheral Component Interconnect (PCI) bus. This bus is external to the chip (off-chip) ARM uses an on-chip bus that is internal to the chip that allows different peripheral devices to be interconnected to an ARM Core. Two different classes of devices are attached to the bus: Bus Master - capable of initiating data transfer with another device ARM Processor Core Bus Slave - capable only of responding to a transfer request from a bus master device Peripherals BUS has two architecture level Physical Layer - electrical characteristics, bus width etc. Bus Protocol - logical rules that govern communication between a process & a peripheral

AMBA Bus Protocol

Advanced Micro-controller Bus Architecture
Introduced in 1996 ARM System Bus (ASB), ARM Peripheral Bus (APB) ARM High Performance Bus (AHB)
Centralized multiplexed bus scheme Higher throughput & runs at higher clock speed, supports width of 64 and 128 bits. AHB-Multi-layer suitable for multiple processors AHB-Lite

Memory

Memory Continued
Hierarchy
Cache
Located between main memory and the core Speeds up data transfer between the processor and main memory. Improves performance but with a loss of predictable execution time. Although cache improves general performance of the system, it does not help real-time response. Many smaller embedded systems do not require cache.

Main memory
large in size 256 KB to 256 MB stored in separate chips Load & store instructions access the main memory

Secondary storage is the largest and the slowest form of memory hard disk rive, CD-ROM

Memory Contd ...

Width
Memory width is the number of bits the memory returns on each access 8, 16, 32 or 64-bits. Memory width has a direct effect on the overall performance & cost ratio.

Memory Contd...
Types
ROM : least flexible can not be reprogrammed contains code that does not require update or correction eg. Boot code Flash ROM
R/W but slow access, low cost Used for storing data that needs to be preserved after power off. An alternative for mass storage or secondary storage.

Dynamic RAM (DRAM)

Currently most commonly used RAM Lowest Cost per MB (among RAMs) Requires frequent refreshing of electronic charge on each cells. Requires a DRAM controller Faster but requires more silicon area Higher Cost Does not require refreshing Access time for SRAM is shorter than equivalent DRAM because SRAM does not require a pause between data accesses. Synchronized with the processor clock Higher clock speed than the conventional memory.

Static RAM (SRAM)

Synchronous DRAM (SDRAM):

Peripherals
Needed for interacting with the outside world Performs input & output functions Peripherals are mostly off-chip All ARM peripherals are memory mapped programming interface is a set of memory-addressed registers. The address of these registers is an offset from a specific peripheral base address. Controllers are specialized peripherals that implement higher levels of functionality.
Memory controller Interrupt controller

Memory Controllers
Connects different type of memory to the processor bus. On power-up a memory controller is configured to allow certain memory devices to be active. These memory devices all the initialization code to be executed. Some memory devices must be set up by software eg. When using DRAM, you need to set up memory timings and refresh rates before it can be accessed.

Interrupt Controllers
When a peripheral needs attention, it raises an interrupt to the processor. An interrupt controller provides a programmable governing policy that allows software to determine which device can interrupt the processor at any specific time by setting appropriate bits in the ICR (interrupt controller register) Two types of Interrupt Controllers
Standard Interrupt Controllers (SIC) Vector Interrupt Controllers (VIC)

Interrupt Controllers contd ..

Standard interrupt controller (SIC)
SIC sends an interrupt signal to the rpocessor when an external devices requests servicing. It can be programmed to ignore or mask an individual device. Interrupt handler determines which device requires servicing by reading a device bitmap register in the interrupt controller.

Vector interrupt controller (VIC)

It prioritizes the interrupts and simplifies the determination of which device caused the interrupt. After associating a priority and a handler address with each interrupt, the VIC only asserts an interrupt signal to the core if the priority of the new interrupt is higher than the currently executing interrupt handler.

Embedded System Software

Four typical software components
Initialization Code: first code executed on the board
It sets up the minimum parts of the board handling control over to the operating system.

Operating System
Provides an infrastructure to control applications and manage hardware system resources.

Device Drivers
Provide software interface to the peripherals.

Applications
Performs one of the tasks required for a device

ROM code that is fixed on a device is called firmwire.

Initialization (BOOT) Code

Takes the processor from reset state to a state where the operating system can run. Prepares the hardware for an OS to take control. Performs following three kinds of administrative tasks:
Initial hardware configuration setting up the target platform memory reorganization Diagnostics fault identification & isolation Booting loading an image and handing control over to the image

Operating System
An OS organizes the styem resources: the peripherals, memory and processing time. It schedules applications to ensure optimal usage of available resources. Two important categories
Real-time operating System (RTOS)
Provides guaranteed response times to events. System running RTOS generally do not have secondary storage. Soft / hard RTOSs

Platform operating systems

Memory management unit to manage large, non real-time applications & tend to have secondary storage. Eg. Linux operating system

An application implements a processing task. The operating system controls the environment.

Summary
ARM uses modified RISC design philosophy suitable for embedded system applications good code density & low power consumption. ES = processor core + cache + memory + peripherals + buses Key points of RISC design philosophy are
Improve performance by reducing the complexity of instructions (simpler hardware) Speed of instruction processing by using a pipeline Provide large register set to store data near the core To use load-store architecture

ARM design philosophy includes several non-RISC ideas