Exercise Switched Networks

P(ulse)C(ode)M(odulation)-Hierarchy
starting with PCM 30 level interleaving 4 incoming channels bitwise frequency difference pseudo synchronous: Plesiochronous System Due to missing incoming bits stuffing bits are necessary

Dipl.-Math.K. Luck

Exercise Switched Networks

PCM-Hierarchy
Systems/channels PCM 30 PCM 120 PCM 480 PCM 1920 PCM 7680 Bitrate in MHz (Mbps) 2,048 8,448 34,368 139,264 564,992

Dipl.-Math.K. Luck

Exercise Switched Networks

Stuffing Bit (1)

systems sending out signals with the same (nominal) frequency are put together frequencies could differ in a permitted interval by multiplexing the incoming bits a displacement could happen stuffing bits are inserted to guarantee the right order of the multiplexed bits (reaching the destination the stuffing bits have to be removed)
Dipl.-Math.K. Luck

Exercise Switched Networks

Stuffing Bit (2)

TS

10

11

12

fTS f TM > fTS f TM

1 TM

10

11

12

fTS Frequency of the sending systems f TM Frequency of the multiplexers S Stuffing bit

Dipl.-Math.K. Luck

Exercise Switched Networks

Stuffing Bit (3)

channel plesiochronous synchronous Bit pattern Using a stuffing bit: Bit pattern channel
1 1 0 2 1 3 1 4 0 1 1 2 0 3 0 4 1 1 S 1 2 0 3 1 4 1 1 2 0 3 1 4 1 1 0 2 1 3 0 4 0 1 1 2 1 3 0 4 1

1 1

0 2

1 3

1 4

0 1

1 2

0 3

0 4

1 1

0 2

1 3

0 4

Dipl.-Math.K. Luck

Exercise Switched Networks

PCM 30 (1)
Combination of 30 ( speech) channels 64 Kbps 2 additional channels for administration RK frame marking channel, M messaging channel, Z bundeling channel Frequency of 2.048 (15010-6) MHz nominal Bitrate of 2.048 Mbps Frame duration: 125 s (due to 256 frame bits)
Dipl.-Math.K. Luck

Exercise Switched Networks

PCM 30 (2)
0 1 2 3 ...... 15 16 17 K15 Z K16 ^ 256 Bit = 125 s
X 0 0 1 1 0 1 1 X 1 D N Y Y Y Y

......

30 31

RK K1 K2 K3

K29 K30 M K1

RKK

0 0 0 0 0 DK NK 0 S1 S16 S2 S17

MK

. . .

. . .

S15

S30

Dipl.-Math.K. Luck

Exercise Switched Networks Stuffing Bit

systems sending out signals with the same (nominal) frequency are put together frequencies could differ in a permitted interval: A PCM 120 system allows a difference of 5010-6 2.048 MHz for each sending system. by multiplexing the incoming bits a displacement could happen stuffing bits are inserted to guarantee the right order of the multiplexed bits (reaching the destination the stuffing bits have to be removed)

Example
A PCM 30 frame consists of 256 bits and takes 125 s to be placed. If we consider two PCM 30 systems and a constant frequency departure of 10-5. So the frequencies differ by f = 10-5 2.048 106 Hz = 20.48 Hz. Hence 20.48 times per second the faster system sends one more bit. So after every 1000 ms / 20.48 = 48.83 ms the faster system has sent the same number of bits as the slower system PLUS one bit. Considering the frame duration of 125 s after 48.83 ms / 125 s per frame = 390 frames a bit deviation occurs. If these systems should be arranged without any loss of information, a stuffing bit should be inserted referring to the faster system.

PCM 120 System

^ 848Bit = 100,379 s block 2 block 3
4 St 208 4 St 208 4 St S 4

block 1
12 RK/M 200

block 4
208 RK/M

1 1 1 1 0 1 0 0 0 0 D N

1 2 3 4 1 2 3 4

......

1 2 3 4

RK/M of block1 is the frame identifier St of block 2 through 4 contains information about the stuffing bits S of block 4 contains the stuffing bits Although four PCM30 systems are interleaved by PCM120 system four PCM30 frames fit exactly into one PCM120 frame. The bits of the different PCM30 systems are interleaved disregarding the beginning and the end of the particular frames.

Dipl.-Math. K.Luck

Exercise Switched Networks Stuffing Bit Signalisation

St of block 2
1.1 1.2 1.3 1.4 2.1

St of block 3
2.2 2.3 2.4 3.1

St of block 4
3.2 3.3 3.4

With the knowledge about the St sections of each block we can get some information about the stuffing bits by having a look to the stuffing bit signalisation: stuffing bit signalisation for system 1: 1.1 2.1 3.1 stuffing bit signalisation for system 2: 1.2 2.2 3.2 stuffing bit signalisation for system 3: 1.3 2.3 3.3 stuffing bit signalisation for system 4: 1.4 2.4 3.4 (x.y represents a bit, x = 1,2,3, y = 1,2,3,4) With the following table we can decide whether a stuffing bit exits or not: stuffing bit inserted no stuffing bit inserted if if 111 000 110 001 101 010 011 100

Given is a frame for a PCM 120 system. The St sections are keeping the following bit combinations: - block 2: 0111 - block 3: 1101 - block 4: 0101. How are the bits in section S of block 4 are to be interpreted? The section S of block 4 contains no stuffing bit for the system 1 (stuffing bit signalisation is 010), a stuffing bit for system 2 (stuffing bit signalisation is 111), no stuffing bit for system 3 (stuffing bit signalisation is 100) and a stuffing bit for system 4 (stuffing bit signalisation is 111).

PCM 120 frame

100.379 s to transmit one frame 848 bits per frame 24 information bits (RK/M and St sections) 4 stuffing bits if necessary, otherwise data bits incoming data rate per system: 2 Mbit/s outgoing rate: 8448000 bit/s

A PCM 120 system is given, that means there exits an output rate of 8448000 bit/s. The four (multiplexed) systems have a output data rate of 2048000 bit/s. How many stuffing bits per second are sent in average?

Dipl.-Math. K.Luck