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128 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 16, NO.

3, MARCH 2006

A CMOS Single-Pole-Four-Throw Switch


Kwangchun Jung and Kenneth K. O, Member, IEEE

Abstract—An one-pole-four-throw switch that can be used to


switch between the band select filters of four cellular bands and a
single input programmable low noise amplifier has been demon-
strated in a 0.18- m complementary metal oxide seminconductor
process. Its insertion losses are 0.39, 0.61, 0.66, and 0.75 dB in
the GSM900, DCS1800, PCS1900, and wide-band code division
multiple access system bands. IIP3’s of the switch are 27 dBm
and isolations are greater than 22 dB.
Index Terms—Complementary metal oxide seminconductor
(CMOS) integrated circuits, metal oxide semiconductor field effect
transistor (MOSFET) switch, 1P4T switch, radio frequency (RF)
switch. Fig. 1. Interface between off-chip filters and a multiband LNA with a single
input.

I. INTRODUCTION

W ITH the evolution of wireless communication systems


to the third generation, the need for low cost multifre-
quency band and multistandard integrated transceiver concepts
has increased [1]. A high level of integration with a reduced
number of off-chip components is a key to low cost. Tradition-
ally, to support the multifrequency band operation, two or more
sets of key radio frequency (RF) blocks are integrated on a single
die [2]–[4]. However, these increase the die area, complexity of
test, and cost. As an approach to mitigate these, a multiband
programmable low noise amplifier (LNA) with a single input
is proposed [5]. The LNA can potentially handle global system
for mobile communication (GSM900), digital cellular system
(DCS1800), personal communication system (PCS1900), and
wide-band code division multiple access system (WCDMA).
For a radio using such an LNA, an RF switch is needed to con-
nect the required off-chip filter for a chosen frequency band to Fig. 2. Schematic of the 1P4T RF switch.
the LNA. As shown in Fig. 1, in order to support the four cellular
standards, an one-pole-four-throw switch (1P4T) is needed. The
sources in a single pole double throw switch, insertion losses
switch does not need to handle large power like a T/R switch,
of 1P4T switches are expected to be higher than those of the
which makes it ideally suited for implementation in comple-
previously reported 1P2T switches [6]–[8]. Dealing with these
mentary metal oxide seminconductors (CMOS). This letter re-
additional parasitic capacitances is a challenge for realizing low
ports such an 1P4T switch implemented in a 0.18- m CMOS
insertion loss 1P4T switches. The transistors, M1, M2, M3, and
process.
M4 perform the switching function. A dc voltage of 1.2 V is
applied at the sources and drains of transistors using bias-Ts
II. DESCRIPTION OF THE RF SWITCH to lower junction capacitance, which lowers insertion loss. Ap-
The 1P4T switch consists of four transistors and four gate plying the same dc voltage to all the sources and drains makes
resistors, and is shown in Fig. 2. The simplest topology (e.g., the dc power consumption almost zero. The gate bias resistors,
without shunt transistors for improving isolation) is employed in R1, R2, R3, and R4 are implemented using polysilicon resistors.
order to lower the parasitic capacitances at the input and output The resistors ac isolate the gates of transistors for improved lin-
nodes, which in turn lowers insertion loss. Despite this, because earity. The bias Ts could also be replaced with on-chip resis-
four sources are connected to the RFOUT node, instead of two tors like the gate bias resistors. The circuit requires no external
matching networks. The control voltages are switched between
Manuscript received September 27, 2005; revised November 22, 2005. 0.8 and 3.0 V.
The authors are with the Silicon Microwave Integrated Circuit and The channel resistance of transistor is one of the dominant
System Research Group (SiMICS), Department of Electrical and Computer factors determining insertion loss. Increasing the gate width of
Engineering, University of Florida, Gainesville, FL 32611 USA (e-mail:
kcjung91@tec.ufl.edu; kko@tec.ufl.edu). transistors reduces channel resistance. However, it increases the
Digital Object Identifier 10.1109/LMWC.2005.869857 drain-to-body and source-to-body junction capacitances. This
1531-1309/$20.00 © 2006 IEEE
JUNG AND O: CMOS SINGLE-POLE-FOUR-THROW SWITCH 129

Fig. 3. (a) Micrograph of the 1P4T RF switch and (b) photograph of PCB and
bonded switch chip.

increases the return loss and the loss through associated para-
sitic substrate resistances. Because of these, there are optimal
transistor widths for minimum insertion loss. The parasitic ca-
pacitances also degrade insertion loss of a transistor with fre-
quency as well as isolation [6], [7].
Since the transistors are intended for operation at dif-
ferent frequencies, their sizes must be accordingly chosen
(1 296 m, 2 378 m, 3 378 m, 4 422 m). Fig. 4. (a) Measured return loss and (b) insertion loss of 1P4T RF switch.
This is another unique requirement not to be considered for
the design of previously reported switches. In order to get
O [8] showed that RF switches with low substrate resistances
comparable insertion losses among four transistors, only M4
have better insertion loss and isolation. Therefore, all of the die
for WCDMA was chosen to have the optimum width while the
area except the four transistors, four resistors, and twelve pads,
other transistors were made narrower than the optimum. M1 for
are occupied by substrate contacts. The die size including the
GSM900 has the smallest width and M4 for WCDMA has the
bond pads is 0.3 mm . Fig. 3(b) shows a photograph of the
largest width. The minimum channel length of 180 nm is ex-
switch mounted on a printed circuit board (PCB).
clusively used to reduce the channel resistance. The multifinger
Fig. 4 shows the measured return loss and insertion loss
interdigitated transistor layout is used to reduce the junction
versus frequency at the four bands. The return losses for
capacitances. The parasitic interconnect capacitance between a
GSM 900, DCS 1800, PCS 1900, and WCDMA are 23 dB,
drain and a source is an important factor determining isolation
14 dB, 16 dB, and 18.5 dB, respectively, which are excellent.
and its effects become more critical as the transistor length
For GSM 900, the insertion loss varied between 0.37 dB
decreases. Hence, only the metal1 and metal2 are used for the
(935 MHz) and 0.39 dB (960 MHz). For DCS 1800 and
drain and source connections.
PCS 1900, the maximum insertion losses are 0.61 dB at
1880 MHz and 0.66 dB at 1990MHz, respectively. Last, for
III. EXPERIMENT RESULTS WCDMA, the maximum insertion loss is 0.75 dB at 2170 MHz.
A microphotograph of the 1P4T RF switch is shown in These should be adequate for cellular applications. Actually,
Fig. 3(a). To reduce the lengths for the interconnections be- the simulated insertion losses were all less than 0.5 dB. The
tween M3 and bond pad and between M4 and bond pad, the differences between simulation and measurement are attributed
transistors are located between the pads. R1-R4 resistors are to the fact that the actual bond-wire inductances ( 3 nH) on
chosen to be (\sim) 70 k to float the gate terminals. Li and the RF pats are 50% higher than that used for the design
130 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 16, NO. 3, MARCH 2006

further reduce the insertion loss by using a more scaled CMOS


process. Isolations in the GSM900, DCS1800, PCS1900, and
WCDMA bands are 29, 24, 23, and 22 dB, respectively.
The linearity requirement of the 1P4T RF switch in a receiver
chain is not stringent. Fig. 6 shows the input third-order inter-
cept points (IIP3) measured using two tones. IIP3s for all four
bands are 27 dBm. These are more than adequate since the
IIP3 specifications of four standards are less than 0 dBm.

IV. CONCLUSION
An one-pole-four-throw switch for a multiband receiver is
implemented using 1.8-V 0.18- m NMOS transistors. Its inser-
tion losses are 0.39, 0.61, 0.66, and 0.75 dB for the GSM900,
DCS1800, PCS1900, WCDMA bands, and its IIP3s of 27 dBm
should be sufficient for this application. The insertion losses
are lowered by eliminating the shunt transistors normally found
Fig. 5. Simulated insertion losses for varying bond wire inductances. in one-pole-two-throw switches. Different width transistors are
used in the four bands to balance the insertion loss.

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