IMPLEMENTATION OF AN EMBEDDED GPS RECEIVER IN SoC METHOD

A PROJECT REPORT

Submitted by RAJASEKHARAN.J REG NO: 101003604015

in the partial fulfillment for the award of the degree of MASTER OF ENGINEERING

in APPLIED ELECTRONICS

GNANAMANI COLLEGE OF TECHNOLOGY SALEM

ANNA UNIVERSITY: COIMBATORE

BONAFIDE CERTIFICATE Certified that this project report titled Implementation of an Embedded GPS Receiver in SoC method is the bonafide work of Mr.Rajasekharan.J (Reg.No:101003604015) who carried out the research work under my supervision. Certified further, that to the best of my knowledge the work reported herein does not form part of any other project report or dissertation on the basis of which a degree or award was conferred on an earlier occasion on this or any other candidate.

(Head of the Department) Dr. G Athisha., M.E.,PhD., Professor and HOD, Department of ECE, PSNA College of Engg and Tech, Dindigul-624 622

(Internal guide) Mrs. Meena alias Jayanthy, M.E., Assistant Professor, Department of ECE, PSNA College of Engg and Tech, Dindigul-624 622

Submitted to the viva-voce examination held on

INTERNAL EXAMINER

EXTERNAL EXAMINER

ACKNOWLEDGEMENT It is my bound duty and moral responsibility to express my praise and gratitude to the Lord Almighty, who has been my strength in time of weakness and hope in time of despair, making all things beautiful in him time. I thank my parents who have encouraged me with good spirit by their incessant prayers to complete this project. I would like to express my sincere thanks to the founder of our institution Late Thiru R.S.Kothandaraman and present chairperson

Tmt.K.Dhanalakshmi Ammal for providing me various formalities needed for successful completion of my project work. I express my sincere thanks to our beloved principal Dr.S.Sakthivel, B.E.,M.S(Engg).,Ph.D., for permitting me to do the project work. I would like to cordially thank our Head Of The Department, Dr.G.Athisha., M.E., PhD., for her kind co-operation and advice.

I take this opportunity to express my deepest gratitude to my guide, Mrs.C Meena alias Jayanthy M.E., for being a beacon in guiding me throughout the project. Her constructive criticism, experience and profound knowledge have been inspirational in taking up the project and completing it successfully.

ABSTRACT A Global Positioning System(GPS) receiver based on FIELD

Programmable Gate Array and MicroBlaze was developed. This kind of GPS receiver is made up of a RF Front-End and FPGA, with NemeriX NJ1006A and Xilinx FPGA as its core chips. The RadioFrequency Front-End chip NJ1006A receives the GPS signal and converts it to IF signal which is transfered to FPGA.The correlators array , C/A code generator,C/A codeDCO and carrier DCO were analyzed and designed with Verilog hardware description language on FPGA. The algorithm of acquisition and tracking of GPS signal were discussed and implemented with MicroBlaze soft processor core in fpga.Meanwhile, the MicroBlaze soft processor core is responsible for communicating with FPGA user logic via the interface named OPB Bus. A parallel correlator using three local replica C/A code was developed and implemented on this FPGA-based GPS receiver, which improved the acquiring efficiency and accuracy of the GPS receiver. The simulation and verification results of the algorithm of GPS receiver are provided. The existing methods, three chip, two chip,DSP/VLSI based,PC based are bulky and difficult to update the algorithm changes. So I implement the new technology System on Chip. Here entire algorithm implemented in a single FPGA and an inbuilt soft processor core. The advantage is system becomes portable : everything in a single chip Also the updated algorithms can be easily implemented so that changes can be easily updated. In future we can make the system in hand held systems. This is very economical

TABLE OF CONTENTS Chapter No: Title Page No iv vii ix

ABSTRACT LIST OF FIGURES LIST OF ABBREVIATIONS

INTRODUCTION 1.1 Preface 1.2 Global Positioning System Overview 1.3 Vlsi Design 1.4 Introduction to Gsm Wireless Modems 1.4.1 What Is A Gsm Modem 1.5 Technical Introduction to Gsm Modem Technology 1.5.1 Facts And Applications Of Gsm/Gprs Modem 1.6 Applications 1.7 What Are Fpgas 1.7 Project Overview 1.9 Existing System

1 1 1 5 7 7

14 21 21 23

SYSTEM STUDY AND ANALYSIS 2.1 Proposed System

2.2 System Design Scheme 2.3 Software Gps Receiver 2.4 Rf Front-End Design 2.5 Implementation Of Gps Digital Base-Band Channel 2.6 Verilog Implementation Of The Correlator 2.7 Local Carrier Generator And Carrier Dc 2.8 Microblaze Soft Processor Core 2.9 Software Used 3 4 RESULT AND DISCUSSIONS CONCLUSIONS

23 25 29 30 30 31 35 39 41 44

REFERENCES

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LIST OF FIGURES Table No 1.1 1.2 1.3 2.1 2.2 2.3 2.4 2.5 Title Detecting receiver by satellite GSM architecture FPGA architecture Transmitter and receiver GPS c/a code acquisition C/A code generator Verilog implementation of correlator Data simulation result of the carrier DCO for the correlator 2.6 3.1 Microblaze processor Accumulator & dump register simulation Result 3.2 3.3 3.4 Carrier DCO simulation result Data transmission between FPGA&MB Acquisition result using FFT approach 40 41 41 42 32 33 Page No 3 11 14 25 27 28 31

vii

LIST OF ABBREVIATIONS

GPS GSM FPGA VLSI VHDL

Global positioning system Global system for mobile communications Field programmable gate array Very large scale integration Very high speed integrated circuit hardware description language

EDK XPS MSS MHS

Embedded development kit Xilinx platform studio Microprocessor Software Specification Microprocessor Hardware Specification

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