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VSI VISION
The Periodical of the VLSI Society of India August 2005 Volume 1 Issue 1
Peer-reviewed articles reporting original, previously unpublished work carried out by contributing authors Invited articles from experts Survey articles from experts Reports of VLSI-related events taking place in India Debate a forum for discussing topics related to the Indian VLSI milieu Cool Vision - featuring crosswords, puzzles, quiz, and other fun items, all related to VLSI Book Reviews Letters to the Editor, providing feedback on VISION and/or the activities of the VSI
At present, the plan is to bring out two issues of VLSI VISION every year. The frequency will be increased if the number of submissions increases. Depending on the quality and quantity of paper submissions, VSI plans to have a more formal journal of the VSI in the line of IEEE Transactions. Submissions for all the above categories are invited. Submissions must be made online using the Docman system. Proposals are also invited for special issues that address a specific topic in VLSI these must be sent to the appropriate area editor.
Bobby Mitra President, VLSI Society of India Texas Instruments India 2005
Editorial
It is an immense pleasure to place in your hands the first issue of the periodical of the VLSI Society of India. In the past, VSI has published a newsletter; through the establishment of the periodical, the society has taken the next step. VSI has felt the need of the periodical that provides a forum for publication of papers originating from India. Today we have several Masters programs in the country in the area of VLSI and Embedded Systems. I understand that the number of Ph.D. students working in the area of VLSI has also gone up a welcome change! Almost every big name in the VLSI industry has its presence in India. We hope VSI VISION will provide an expression to the creativity for the large and growing number of VLSI professionals. We have fashioned the periodical in the style of a magazine and plan to include technical papers, news reports, announcements, and letters. If the number of high-quality paper submission goes up, VSI is committed to start a periodical in the style of IEEE transactions. I welcome the members of the Editorial Board who have agreed to contribute their valuable time towards VSI VISION. I thank them for their service to the VLSI community. I invite professionals to submit original research papers that have not been published in other forums. Please note that submissions are not restricted to authors from India alone. I also invite the readers to send letters to express their opinion on topics relevant to the Indian VLSI community. Submissions to the Cool Vision section are also welcome. Your feedback on this issue (and future issues) will go a long way in shaping the periodical. I hope you enjoy reading this issue of VSI VISION as much as we have enjoyed putting it together. With best wishes,
C.P.Ravikumar
Abstract The much-debated Moores law is expected to hold for another decade, and we have already seen the commercialization of 90 nm and 65 nanometer technologies. Designing chips in these sub-100 nanometer technologies has proven to be a challenge. Since the cost of manufacturing in these technologies is so hgih, only major semiconductor vendors appear to be geared to face the technological challenge. The smaller players in the field are looking for alternate solutions such as reconfigurable computing platforms. To push the technological limits and yet be economically viable, it is important to get the chips right-the-first-time. This article explores the challenges of semiconductor design technology that occupy todays design engineers and will continue to do so for some years to come.
I Introduction Ever since Jack Kilby made the first integrated circuit (IC) in 1958, nothing has remained the same except for the incredible rate at which the IC is shrinking in size. Todays engineers are designing ICs targeted for manufacture with 90 nanometer (nm) and 65 nm technologies. Work is already ongoing on the 45 nanometer node. There were prophecies about the end of the scaling at the turn of the century when it was believed that the wavelength of light was a limit on the feature size. Yet, the submicron and the sub-100 nm technology are now realities. As a consequence, it is now possible to build circuits which are less than one square centimeter in surface area and have more than 100 million transistors on them. With such huge capacity, the ICs that we design today are not component chips but systems-on-chip(SoC) where the complete functionality of a system is packed into a small piece of silicon. While the raw power of semiconductor manufacturing technology is impressive, it is only half the story. In todays IC business the key to success is to able to rapidly design a differentiated product and quickly bring it to the market place. However, this cannot be done without a sophisticated infrastructure of design components and software to support an efficient design process that ensures that we manufacture silicon that is right-the-first-time. This infrastructure that supports the design process is called: design technology. As we will elaborate in greater detail below, the progress of manufacturing technology into the sub-100 nanometer regime has thrown many new complexities into the design process thereby creating significant challenges in the field of design technology. Solving these design technology challenges is critical to achieving market success with sub-100 nanometer integrated circuits.
Gordon Moore, who cofounded Intel Corporation, is well known for his observation made in 1965 that the number of devices that can be placed on a chip doubles every year. He later revised this law and predicted that the number of devices will double every two years. He received a B.S. degree in Chemistry from the University of California, Berkeley in 1950 and a Ph.D. in Chemistry and Physics from the California Institute of Technology in 1954. He worked at Shockley Semiconductors, founded by William Shockley, the inventor of the transistor, during 1956. In 1957, he left the company along with 7 others (Julius Blank, Victor Grinich, Jean Hoerni, Gene Kleiner, Jay Last, Robert Noyce, and Sheldon Roberts) to form Fairchild Semiconductor. In 1968, Moore and Robert Noyce left Fairchild and founded Intel. In 2001, Moore and his wife Betty made an educational donation of $600 million to Caltech University. Moore is currently the Emeritus Chairman of Intel.
VSI VISION August 2005 II Semiconductor Manufacturing Technology Trends It would be an understatement to say that progress in semiconductor manufacturing technology has been phenomenal. A combination of evolutionary and revolutionary ideas have ensured that Moores law stays on track, as it has for the past three decades. Every time we thought fundamental limits were reached, scientists and engineers would make a breakthrough. As we progress towards very deep sub-micron feature sizes, the dawn of the nano-meter era, we are once again faced with new challenges - be it process, circuit design or design technology. Business needs drive technology. Reducing die sizes reduces costs. It also enables us to integrate multiple features in a single die more economically, leading to super-chips or what is known as System-on-Chip (SoC). Shrinking does not however come for free and is associated with both positives and negatives. Approximately every two years, device dimensions shrink by 30%, resulting in doubling the number of transistors in the same area. This is also accompanied by doubling clock frequencies and better performance and area. However, physical realities on silicon paint a different picture. Shrinking dimensions are accompanied with reliability and functional issues. The manufacturing process can be subdivided into two parts the Front end of line (FEOL) and the Backend of Line (BEOL). FEOL deals with the manufacture of Metal Oxide Semiconductor (MOS) transistors. These are basically switches. Shrinking of the transistor leads to electrical stresses, which cause transistors to leak such that they may never completely turn off. Reduced gate oxide thickness causes gate leakage which can be as significant as sub-threshold leakage. Ion implants are required to alter the threshold voltage (VT) of the transistor to ensure there is gate control. BEOL deals with the manufacture of the interconnects. While transistor scaling ensures we can pack more in the same area, however an efficient metal stack is required to wire all these transistors. If this were not to scale, we would not get our 50% area reduction every technology node. To offset this, metal width and pitch are reducing, and additional layers of metal are being added. The reduction of metal width causes increased resistance, which is compensated by vertical scaling. This leads to increased coupling capacitance which resuts in more crosstalk between signal lines. Yield is a metric of manufacturability, but is not limited to process defects. Today, yield can be impacted by crosstalk which could cause glitches on data or clock resulting in intermittent failures which can be impossible to debug if not caught early in the design. The role of design technology therefore, is to provide SoC designs with the right methodology and flow in order for them to maximally leverage the gains of technology shrink, while insulating them from the electrical challenges caused by scaling. III Design Technology At a high level, design technology can be viewed as having two separate but interacting parts, namely, Design Components and Design Flow. Design Components consists of the various building blocks that are necessary to create the design. At a minimum it includes a library of logic cells (also known as a standard cell library), input/output (I/O) cells which are needed to interface the chip to the outside world and memory blocks. Increasingly however, as we move to the SoC era design components are getting to be varied and complex and could even be a full-fledged processor. These complex design components are usually referred to as intellectual property (IP) and the ready availability of the right IP often differentiates winners and losers in the race to the market place. Building large complex chips is similar to constructing a building from a standard set of pre-fabricated bricks, doors, or perhaps even pre-fabricated walls. In the chip building business these blocks are made available in a standard cell library. As customers tastes differ, one needs to offer variants of the library to please every one. Traditionally, offerings have been high density or high performance. Today's libraries are very sophisticated due to the demands made on them. A library needs to meet customer requirements such as performance (MHz), active power dissipation (mW/MHz), density (K gates/mm^2) and standby leakage (nA/gate). These objectives are met through careful design of the building blocks so that they are both individually efficient, and collectively efficient when used on the chip. In the nanometer era, timing accuracy has moved into picoseconds, which requires greater accuracy of circuit simulation, and modeling. Since a transistor level circuit simulator would be very inefficient or perhaps impossible to run at the chip level, timing models of the library cells are created. These timing models are pre-characterized tables or equations which capture the input slews and output load seen by a logic gate. Selection of load and slew points is an art. Making this selection without knowing chip level issues, could lead to significant inaccuracies in timing. High speed clocking requires special care in the design of clock buffers so that insertion delays are reduced and cells produce balanced delays for both low to high, and high to low edges. Double data rate (DDR) applications puts further constraints on the duty cycle and correspondingly on the jitter budget. 6
VSI VISION August 2005 Complex library cells require detailed analysis using statistical simulation using statistical models of the transistors and passive components. Understanding the impact of process variation is needed to guarantee functionality under all process, temperature and voltage variations. At the chip level this is handled by accounting for on-chip variation (OCV) during the timing analysis phase. The reduced size of sequential elements, such as latches and flip-flops make them prone to Soft error rate (SER). Alpha particles from the environment, including the package and the lead solder balls can cause upset charge being held at a node, which could flip the state of a storage element. Robust circuit and layout styles are required to address such soft errors, which are not physically damaging but can corrupt data inside a chip. Embedded memory designers need to also tradeoff static noise margin (SNM) vs. bit cell density. As the threshold voltage drops, to accommodate voltage scaling of 30% per node, the leakage component of power increases. Transistor leakage which was once confined to pA/um is now in the upper nA/um, resulting in Amps of static leakage if power management techniques are not employed. Innovative process, circuit, and chip design technology is required to address such issues. The previous paragraphs have described the many challenges in ensuring that the right components are in place for the timely design of an SoC. A Design Flow provides the software infrastructure that makes it possible to assemble the SoC while meeting the speed, power and area targets for the design. The flow consists of many steps which the designers need to correctly use in order to meet the particular performance, area and power goals of the chip while ensuring that they deliver the final layout to manufacturing as per the planned schedule. In many modern IC design companies the design team is distributed all over the world and the design task is split into various parts which are handled by these geographically separate teams. Managing the correct transfer and assembly of data as the parts of the chip are being designed concurrently, is a major challenge that needs to be addressed by the flow and needs sophisticated software techniques. Flow support for such concurrent design is not a luxury but a necessity in order to leverage the best available talent anywhere in the world in order to get the chip designed right and designed fast. As previously mentioned, the design flow consists of many steps each one of which needs complex engineering. Since it is not possible for us in one article to do justice to the technical challenges in each of these areas, we have picked two key major sub-flows, namely, Physical Design Closure and Test. IV Physical Design Closure In the nanometer era, complex electrical effects are making the timely design of functional, reliable chips, a major challenge. These electrical effects are problems of the small, since they relate to phenomena that happen in the nanometer scale. The same technology also creates for us, problems of the large, since it makes possible the design of chips with hundreds of millions of transistors with a complex interconnection. To further compound the challenge, these effects must be controlled with a methodology and flow that delivers high-performance, low-power, low-cost chips under aggressive time-to-market constraints. In order to verify the integrity of the design in the presence of these electrical effects, until recently, design flows relied primarily on checkers that are run once the physical design is complete. While such checks are important and necessary in order to highlight the existence of a design integrity problem, the drawback of this approach is that not much help is provided to the designer in order for him/her to quickly solve the problem by modifying the chip layout, i.e., to quickly achieve physical design closure. This challenge is currently being very actively addressed by design technology specialists. The basic requirement of physical design closure is well understood: a large percentage of manufactured chips should be functionally correct at the required clock speed. However, the manufacturing technology trends that we described previously, have created two physical effects that have complicated this problem. These are the coupling capacitance between signal wires and the voltage drop (IR drop) on the power grid that distributes the power supply to all parts of the chip. In nanometer technologies, coupling capacitance dominate the total capacitance of a wire, thereby resulting in significant crosstalk between two signal wires that are in close proximity. As a consequence, two complications occur. First, the delay on a path varies significantly depending on the relative switching patterns of wires that are close to each other. Second, substantial glitching can occur for the same reason, resulting in significant reduction in the noise margin and a possible erroneous state in the flip-flop at the tail of the path. A proper analysis of the effect of coupling capacitors on delay and noise, requires detailed parasitic information which is best extracted after routing is complete. At this stage, the analysis is accurate, but the disadvantage is that the 7
VSI VISION August 2005 corresponding fix may not be easy since the layout is completely done and committed. In this scenario, the required routing changes may not be possible due to congestion, while buffer insertion and other netlist changes may trigger a complete re-layout of the chip, thereby delaying its release to manufacture. Thus, in state-of-the-art design flows, the approach that is being currently pursued is one of avoidance. Starting early in the physical design process the software tool used for layout attempts to automatically avoid situations that can result in significant crosstalk. Additionally, during the physical design process the effect of crosstalk is estimated and the layout modified to eliminate any potential problems. This is an active area of research and development with the goal of developing a design flow in which the layout is correct-by-construction and guaranteed to be free of crosstalk problems. The Power of VLSI Circuits There is no second word on the power of VLSI circuits they enable us to build powerful systems on a single chip. There is another way the VLSI chips are becoming powerful. As the device density is increasing and the frequency of operation is going up, the power consumption of the chips is also increasing dramatically. In addition to dynamic power, the leakage power in CMOS circuits has also become a big concern in nanometer technologies. The power density in the nano-chips has already reached that of an electric hot plate, going towards that of a nuclear reactor, of a rocket nozzle, and projected to reach the power density of the core of the Sun! IR drop is a current/metal-resistance driven phenomenon. The voltage applied at the pads drops as current flows along the power rails, due to the rail resistance. Therefore, the cells do not see the full voltage, which directly translates to higher cell delay. A badly designed power grid can cause a large voltage drop in parts of the chip. If this coincides with a critical path, it would result in functionality failure at the required speed. The safe way of avoiding IR drop problems is to make sure that the power routes are sufficiently wide and have adequate decoupling capacitance. However such an approach cannot be indiscriminately applied as it may use up too much routing space on the chip. Thus, an aggressive designer might want to minimize the IR drop for only those portions of the chip that are timing critical. However, a number of issues remain to be solved, before such an approach is routinely used. First, standard timing analysis tools available today do not adequately take care of the effect of varying IR drop on timing. Second, such an approach would ideally require a dynamic (time-dependent) IR drop calculation, which is a major computational and capacity challenge for todays design flows. Manufacturing in the nanometer area presents its own set of challenges. The features of the layout do not get transferred to silicon in an identical fashion. Thus, what you see (on the screen of the workstation) is not what you get (in silicon). For example, a metal line may actually be jagged. The size parameters such as the width and length of the transistor and interconnect, are therefore reduced to statistical quantities. Similarly, the threshold voltage and other parameters associated with the transistors may vary from one transistor to another due to the vagaries of the manufacturing processes. While this variation itself is not a new phenomenon, its impact is very significant when it come to nanometer technologies. Techniques such as optical phase correction (OPC) are used to counter the problem of inaccuracy in transferring feature sizes from layout to silicon. It is also necessary to do statistical characterization of timing to take into account the variation of parameters from one transistor to another. V Test Even though one can verify a design and be confident about its correctness, things can and do go wrong during manufacturing. A dust particle, a surface imperfection in the silicon wafer, or impurities in the silicon can cause a manufactured circuit to fail. A resistive contact can result in a timing failure. Therefore, every piece of silicon that is manufactured must be tested to ensure that quality products are reaching the customer. Testing is performed by applying pre-calculated input patterns to the manufactured circuit and measuring the outputs. Since the expected values are known from the simulation of a good circuit, these measurements can reveal faults in the manufactured circuit. Functional tests are applied to check if the behavior of the manufactured circuit matches its intended functionality. However, too many functional tests will be needed to get 100% confidence on the correctness of the circuit; therefore, test engineers generate structural tests for the design. Such a test targets a possible fault and generates an input pattern that can expose this fault. Generation of the smallest number of structural tests that can uncover the highest percentage of faults is a big challenge. At one end, the fault universe is expanding stuck-at faults, delay faults, bridge faults, reliability defects and at the other end, the test pattern volume must be kept low to avoid escalation of test cost. When the volume of test data increases, the application of test becomes slow. The test cost is directly proportional to the test application time. The IC 8
VSI VISION August 2005 testers used to test modern VLSI designs cost several million dollars and are expensive to maintain. In full volume production, several such testers will be required. The cost of testing is quoted in cents per chip per second of tester engagement time this value is going up due to escalation in tester costs. In fact, the test cost today is a significant percentage of the total cost of a chip, and is comparable to the design and manufacturing cost. One of the tough challenges test engineers face is to bring down test cost. The two ways to keep test cost under control are to bring down tester cost and to reduce test data volume. In either case, the design must be modified to make it testable. For example, the scan test approach eases structural testing by allowing full access to every storage cell in the design. This approach is also known as Design for Test (DFT). Similarly, built-in self-test (BIST) is a technique whereby test patterns are generated on-chip and the comparison of responses is also done on-chip. Since modern SoC devices have a large number of memories on them, BIST is the customary test methodology for memories. Logic BIST is used for testing the digital logic in the circuit; in this technique, random test patterns are generated on-chip and the circuit responses are compressed into a signature and compared with the signature of the good circuit. Insertion of test circuitry such as scan chains, logic BIST, and memory BIST is known as Test Synthesis. A major challenge in an SoC design flow is Test Closure, which aims to minimize the impact of test synthesis on the original design. The timing, area, and power dissipation of the original circuit can get altered due to the insertion of DFT and BIST. As a matter of fact, since several electronic design automation (EDA) tools are used to achieve test synthesis, even the functional behavior of the original design must be verified again after test synthesis. Formal verification becomes useful to establish that the behavior of the circuit remains same, before and after test synthesis. Test pattern generation tools assume gates and interconnects have zero delay and the input signals arrive with no delay. This of course, is far from reality. A tester which applies the patterns cannot ensure that all the inputs change in sync with the clock. A test application involves measurement of voltage after applying the test pattern, and the delay for the output signal to settle down will be important in ensuring correctness of the measurement. The measurement must be made within a time window to be confident that a decision based on the measurement is correct. The delays of gates and interconnects can be extracted after the layout is complete. The circuit is simulated using the test patterns, factoring the delays into account. Patterns that cannot guarantee safe measurement are dropped and the resulting fault coverage loss is made up using additional test patterns. Since chip-level timing simulations are very expensive, innovative methods are required to reduce the computational effort. Distributed computing is a way of cutting down the wall clock time required for these simulations. In sub-100nm technologies, the test engineer may have to deal with several unexpected roadblocks in arriving at a test plan. For example, at what frequency should the tests be run? Since test patterns exercise a chip in entirely different ways than functional patterns, the switching activity in the circuit can go up by several orders of magnitude in the test mode, causing dynamic power dissipation to go up. Similarly, it is important to keep the leakage current under control so that IDDQ testing can be meaningfully applied. IDDQ testing refers to current testing, where a test pattern is applied to a CMOS circuit and the power supply current is measured after all the switching activity has subsided and the circuit has entered a quiescent mode. In a CMOS circuit, the quiescent current is only due to leakage and if the measured current is unusually large, the circuit under test is very likely to be defective. IDDQ testing can reveal bridge faults and reliability problems in the circuit. However, in modern System-on-Chip designs with over 100 million transistors, the quiescent current of a good circuit can be quite high, making it a challenge to apply IDDQ tests. Signal integrity issues can also become a cause of concern during test pattern generation and validation. Test pattern generation must address signal crosstalk faults and IR drop problems. Similarly, since test patterns can cause excessive switching activity and resultant IR drop, there is a need to ensure that timing failures in test mode are due to genuine defects in the circuit and not due to the test patterns. When the term Design for Test was initially coined, the thought process was that logic design cannot be done independently of testability considerations. In the nanometer era, test cannot be separated from either logic design or physical design, making it a major challenge. VI Conclusions In this article we have outlined the progress of semiconductor manufacturing technology into the nanometer era. Business needs drive this continuous shrinking of the feature sizes, since it enables the fabrication of complex systems-on-chip (SoC). However as we have further described in some detail, it is not easy for designers to harness this technology and bring complex SoCs to the market in a timely manner, unless they use sophisticated design technology to create the SoC. We have highlighted some of the many challenges that are currently being addressed in order to provide SoC designers with state-of-the-art design components and design flow. With no immediate end in sight for CMOS technology scaling, the field of design technology will continue to be a challenging one for years to come. 9
S u r v e y R e su l t s - P G S t u d e n t s
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(b) How many PG students with specialization in Semiconductors/VLSI do you think will be needed (annually) by 2010? 82 responses were received and the results are shown in Figure 2. There seems to be a majority vote on > 3000 PG students per year by 2010. (c) What is the number of B.Tech students graduating today with some specialization in Semiconductors/VLSI to take up a profession in the VLSI area? We received 69 responses. The majority have felt that less than 1000 students graduating today have some specialization in VLSI. The details of the survey are shown in Figure 3. (d) What is the number of M.Tech students graduating today with specialization in Semiconductors/VLSI to take up a profession in VLSI? The survey elicited 65 responses. The results are shown in Figure 4. The majority have felt that less than 500 PG students graduating today have specialization in VLSI.
Current Situation - B.Tec h
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Do you agree or disagree with the survey? If you have not already done so, you can participate in the survey! You must be a member of the vdat mailing list to participate. Go to http://groups.yahoo.com/group/vdat/polls to take part in this esurvey.
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VSI VISION August 2005 2004 totaled $179 billion. These components supported a 2004 worldwide electronic end-equipment market of $1,186 billion. Such is the power of one idea to change the world. The Vacuum Tube Era For almost 50 years after the turn of the 20th century, the electronics industry had been dominated by vacuum tube technology. But vacuum tubes had inherent limitations. They were fragile, bulky, unreliable, power hungry, and produced considerable heat. It wasn't until 1947, with the invention of the transistor by Bell Telephone Laboratories, that the vacuum tube problem was solved. Transistors were miniscule in comparison, more reliable, longer lasting, produced less heat, and consumed less power. The transistor stimulated engineers to design ever more complex electronic circuits and equipment containing hundreds or thousands of discrete components such as transistors, diodes, rectifiers and capacitors. But the problem was that these components still had to be interconnected to form electronic circuits, and hand-soldering thousands of components to thousands of bits of wire was expensive and time-consuming. It was also unreliable; every soldered joint was a potential source of trouble. The challenge was to find cost-effective, reliable ways of producing these components and interconnecting them. One stab at a solution was the Micro-Module program, sponsored by the U.S. Army Signal Corps. The idea was to make all the components a uniform size and shape, with the wiring built into the components. The modules then could be snapped together to make circuits, eliminating the need for wiring the connections. Enter Kilby It was in a relatively deserted laboratory at TI's brand new Semiconductor Building where Jack Kilby first hit on the idea of the integrated circuit. In July 1958, when most employees left for the traditional two-week vacation period, Kilby -- as a new employee with no vacation -- stayed to man the shop. TI was working on the Micro-Module program when Kilby joined the company in 1958. Because of his work with Centralab in Milwaukee, Kilby was familiar with the problems in manufacturing electronic circuits. Kilby began searching for an alternative, and in the process decided the only thing a semiconductor house could make cost effectively was a semiconductor. "Further thought led me to the conclusion that semiconductors were all that were really required that resistors and capacitors [passive devices], in particular, could be made from the same material as the active devices [transistors]. I also realized that, since all of the components could be made of a single material, they could also be made in situ interconnected to form a complete circuit," Kilby wrote in a 1976 article titled Invention of the IC. Kilby began to write down and sketch out his ideas in July of 1958. By September, he was ready to demonstrate a working integrated circuit built on a piece of semiconductor material. Several executives, including former TI Chairman Mark Shepherd, gathered for the event on September 12, 1958. What they saw was a sliver of Germanium, with protruding wires, glued to a glass slide. It was a rough device, but when Kilby pressed the switch, an unending sine curve undulated across the oscilloscope screen. His invention worked he had solved the problem. Early Successes Kilby had made a big breakthrough. But while the U.S. Air Force showed some interest in TI's integrated circuit, industry reacted skeptically. Indeed the IC and its relative merits "provided much of the entertainment at major technical meetings over the next few years," Kilby wrote. The integrated circuit first won a place in the military market through programs such as the first computer using silicon chips for the Air Force in 1961 and the Minuteman Missile in 1962. Recognizing the need for a "demonstration product" to speed widespread use of the IC, Patrick E. Haggerty, former TI chairman, challenged Kilby to design a calculator as powerful as the large, electro-mechanical desktop models of the day, but small enough to fit in a coat pocket. The resulting electronic hand-held calculator, of which Kilby is a co-inventor, successfully commercialized the integrated circuit. Impact As every one of us knows, the impact of Kilby's tiny chip has been far-reaching. Many electronics products of today could not have been developed without it. The chip virtually created the modern computer industry, transforming yesterday's room-size machines into today's array of mainframes, minicomputers and personal computers. The chip restructured communications, fostering a host of new ways for instant exchanges of information between people, businesses and nations. Without the chip, man could not explore space or fly to the moon. The chip helps the deaf to hear and is the heartbeat of a myriad of medical diagnostic machines. The chip has touched education, transportation, manufacturing and entertainment. Since 1961, the worldwide electronics market has grown from $29 billion to nearly $1,150 billion. Projections indicate that it will become the world's single largest industry. This growth will depend on the continued development of newer and better technologies -- like those being developed at TI's new research and development center in Dallas. Little wonder that the research center is named after the inventor of the IC Jack Kilby.
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VSI VISION August 2005 Toward the Future With continuing advances in semiconductors, you can look forward to more new amazing encounters with electronic equipment. Imagine calling the baby-sitting center to check on your child, and seeing the smiling face of your child on the screen of your cell phone. Imagine turning on the oven from your car phone as you pull out of the parking lot of your office at the end of the day. Imagine setting your car on autopilot, and looking over notes for your next day's meeting on your commute home! All this sounds like stuff from science fiction, but these breakthroughs are only a short stride away, with the help of technologies being developed today. Thanks are due to Dr T.V. Gopal of Anna University for compiling this material from the website of Texas Instruments: See http://www.ti.com/corp/docs/kilbyctr/jackstclair.shtml for more material on Jack Kilby.
The Rule of 10 In the area of semiconductor testing, the Rule of 10 is as famous as Moores law. The Rule of 10 estimates the way the testing cost escalates when a fault is not detected at the earliest possible time. If it costs $1.00 to detect a fault at the chip level, it will cost $10.00 to detect the same thing at the board level. $100.00 to detect it in the finished product, and $1000.00 to detect it if the defective part goes to the customer. The cost of testing has grown at an alarming rate due to growing device density and the introduction of more fault models e.g. at-speed testing, bridge faults, and N-detect testing. Surveys have indicated that even in 2000, the semiconductor industry spent $5.00 billion towards testing. It is predicted that the cost of testing will overtake the cost of manufacture in 2012.
Hard facts about testing ATE Speeds grow at 12% per year, device speeds grow 30% per year. Inaccuracy of testing can result in a yield loss of up to 48% by 2012 yield loss refers to the loss in revenue due to rejection of good chips that are incorrectly classified as bad chips. A manufacturing test equipment costs in the order of a few million dollars about $8000 per pin of the device being tested. Several testers may be needed due to high volume of production, with semiconductor industry switching to 300 mm wafers.
Feedback
I have attended the Educational Workshop on VLSI Design organized by MNIT, Jaipur and VLSI Society of India from 8-12 March 2005. It was indeed a good experience to listen to various emerging topics in VLSI field. Ravi Sindal Lecturer, Devi Ahilya University, Indore I really appreciate your work in promoting VLSI research, development and education in India. The society has a very significant purpose that can usher in an era of technological revolution to our country. I wish you the greatest success Warm regards, Unni Chandran For a new membership or renewal, or to obtain information about VSI events, write to the VSI Secretariat at vsisecy@vlsi-india.net. Please include a descriptive subject line, such as Membership send application form (soft copy). When you request for hardcopy forms or brochures, please include your correct mailing address and phone number. Please feel free to forward the literature from VSI to your colleagues and friends.
Members
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Please watch out for further announcements on this course on the VSI mailing list. If you propose to conduct an event, you can find information about how to submit a proposal in this issue of VSI VISION.
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VSI VISION August 2005 18th International Conference on VLSI Design And 4th International Conference on Embedded Systems Theme: Power-aware Design of VLSI Systems Prof. Susmita Sur-Kolay, ISI, Kolkata ssk@isical.ac.in The 18th International Conference on VLSI Design was held at Hotel Taj Bengal from January 3 - 7, 2005. Like the past two years, this years conference was also a joint one with the 4th International Conference on Embedded Systems. Around 800 delegates, including over 200 fellows from premier academic institutions and fully supported by the Conference, attended the 5-day conference. The technical program of the Conference was held during January 3-5 while the tutorials were on January 6-7. The increasing popularity and importance of this conference around the globe has led to its recognition as a Sister Conference by the IEEE/ACM Design Automation Conference (DAC) Committee from this year. The degree of scaling in VLSI technology and ever increasing integration density have led to unprecedented levels of power dissipation in current day VLSI circuits, and possibly creating a barrier to further scaling and integration unless effective design techniques are developed to reduce power. The demand for power-aware designs is driven by the need for lower power mobile devices as well as high power systems where performance has to be traded with the cost of cooling. Aptly, the theme of the conference this year is Power-aware Design of VLSI Systems - a highly relevant topic for industry, consumers, and academia. Several papers address this problem at various levels of design abstraction from devices to circuits and architecture. For the first time, three tracks, namely Design Methods, Design Tools and Embedded Systems, were introduced to cover the wide range of topics. The technical program put together by the Program Chairs Prof. Kaushik Roy and Prof. Susmita Sur-Kolay included four keynote addresses, four invited plenary talks, two banquet speeches, and a panel discussion by eminent experts from the academia and industry. There were 97 regular papers, 16 short papers and 23 posters, along with 5 embedded tutorial presentations. On the fifth parallel track, an excellent industry forum program with vendor presentations and an embedded panel discussion was also very well appreciated. The tutorial program organized by Dr. Partha S. Dasgupta and Prof. Krishnendu Chakraborty had seven full-day tutorials and two half-day tutorials on emerging topics were found to be very beneficial by the 350 attendees. On the morning of January 3, Dr. Partha Pratim Das, Head of Engineering, Interra Systems and General Chair of the Conference welcomed the delegates. The Steering Committee Chair Prof. Vishwani D. Agrawal inaugurated the Conference. Sri Manab Mukherjee, Minister for Information Technology, Government of West Bengal graced the occasion as the Chief Guest and highlighted how Bengal is gearing up to the needs of the IT industry in general and to the technology industry like semiconductor in particular. This was followed by a visionary keynote The High Walls Have Crumpled by Prof. C. L. Liu of National Tsing Hua University, Taiwan. In his characteristic charismatic style, Prof. Liu analyzed the silent glasnost that has been bringing down the high walls between various technological alternates. Dr. Bobby Mitra, MD of Texas Instruments, India and President of VLSI Society of India (VSI) then inaugurated the exhibition. The banquet speech in the evening by Mr. Richard Sevcik, Executive Vice President, Xilinx was on Comparison of FPGAs and ASICs for SoC applications.
Figure 1: Mr. Manab Mukherjee delivering the Chief Guest's Address (L to R: Prof. Rana Duttagupta, Dr. Partha Pratim Das, Dr. Sandip Kundu, Prof. Vishwani D Agrawal, Prof. Susmita Sur-Kolay & Prof. Kausik Roy)
Figure 2: Dr. G D Gautama welcomes ISA to West Bengal (L to R: Dr. Pradip Datta, Mr. Rajendra Kumar Khare, Mr. Manab Mukherjee, Dr. Vinod Agarwal) 16
VSI VISION August 2005 The second day of the Conference started with two very exciting keynote speeches. Mr. Ted Vucurevich, Vice President and CTO of Cadence talked on 65nm Omnibudsman and Mr. Alan Naumann, President and CEO, of CoWare explained the visions of his company through his talk titled ESL The Next Leadership Opportunity For India? Both lectures received a lot of acclaim from the audience. On the same evening, an energized Panel Discussion was held on Next Generation Design: Is EDA the Weakest Link? A seven-member panel debated on the future of EDA through a session that ran over the slotted time on popular demand. Keeping with the tradition, the Conference held its Awards Ceremony in the evening. Awards, instituted after pioneers of electronics research from Bengal Prof. A K Chaudhury and Prof. N N Biswas were given away for Best Paper and Best Student Paper. The Conference also named its award for the Best Design Contest Entry after Prof B R Nag. In spite of many a hero for the evening, the limelight certainly was stolen by Prof. C L Liu who was conferred the Life Time Achievement Award by the Conference for his contributions to Algorithms. Prof. Sudhakar M Reddy, the first recipient of this award, did the honors. The evening ended with a visionary presentation Moore's Law is Unconstitutional by Dr. Walden Rhines, CEO of Mentor Graphics. In a special early morning session on the third day of the Conference, the Ministry of IT, Govt. of West Bengal and Webel joined hands to actively welcome the Indian Semiconductor Association (ISA) - the newly formed society for the promotion of Semiconductor Industry in India. ISA launched its Technovation Initiative in collaboration with the Govt. of West Bengal. Explaining this initiative, Mr. Rajendra Kumar Khare, MD of Broadcom and Chairman of ISA spoke about the charter, goals, vision, and the implementation plan of ISA. ISA also announced that they would create a Patent-Fabric that will help send innovative ideas from Universities to get filed as patents; institute various awards and research grants. To achieve this objective, ISA will collaborate with various institutions and Government agencies. Mr. Manab Mukherjee, Minister for IT and Dr. G D Gautama, Principal Secretary of IT shared the views of the Government and welcomed the initiatives by ISA. The Technnovation launch was followed by an innovation packed keynote presentation VLSI Design Challenges for Gigascale Integration by Mr. Shekhar Y. Borkar, Intel Fellow, Intel Corp. The plenary lectures during the three days were on Configurable Processor the building block for SOC (SystemOn-a-Chip) by Ms. Beatrice Fu, Senior VP, Tensilica, Modeling Usable and Reusable Transctors in System Verilog by Mr. Janick Bergeron, Synopsys, Optimizing SoC Manufacturability by Dr. Yervant Zorian, Virage Logic and Complex Processor Architectures - The Verification Challenge by Mr. Sunil Kakkar, Freescale Semiconductor India Ltd. The conference was supported by various institutions including VLSI Society of India (VSI); Indian Statistical Institute; Council of Scientific & Industrial Research; Dept. of IT, Govt. of WB, IEEE Circuits & Systems Society; IEEE Solid State Circuits Society; IEEE Electron Devices Society and ACM SIG on Design Automation. Many companies provided financial help with Xilinx-CMC as the Platinum Sponsor; Cadence, Intel, Mentor, Synopsys & Texas Instruments as Gold Sponsors; Agere, Centillium, Coware, Infineoon, Natsem and Tensilica as Silver Sponsors; and Alliance Semiconductor, Interra Systems, Open-Silicon, TranSwitch, Virage Logic and Zenasis as Bronze Sponsors. Besides, BSNL, Alumnus Software and Rahul Commerce supported through infrastructure help. A technical exhibition had 26 companies and CAD research laboratories of academic showcasing their products and technologies in the booths.
Soft Errors are making design harder to do! Soft errors are also known as Single-event Upsets (SEU) in the literature. They are attributed to radiation caused by neutrons generated from cosmic rays and alpha particles from impurities in the packaging material. Soft errors will result in transient failures, which are hard to reproduce and debug. In the past, soft errors have been of importance for space electronics. However, in technologies such as 90nm and below, soft errors are more frequent. Similarly, in the past, designers have worried about soft errors in memory cells. Now, designers worry about soft errors in logic circuits as well. Some protective mechanisms that can be put in the design against soft errors include error correction coding and redundancy.
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Workshop on Specification and Design Methodologies for Adaptive and Embedded Systems
Bangalore, January 11-14, 2005 Dr. Subramanian Pattamadai Sitaraman, Senior Consultant, Tata Consultancy Services A three day Workshop on Specification and Design Methodologies for Adaptive and Embedded Systems was held at the Indian Institute of Science, Bangalore during January 11-14,2005. It was jointly organized by the Computer Society of India (CSI), WG1.3 of TC1 of International Federation for Information Processing (IFIP) and Department of Computer Science and Automation of the Indian Institute of Science (IISc). The sponsors were Tata Consultancy Services, General Motors, Polyspace Software and VLSI Society of India. The theme of the workshop was based on the following observations: Computing systems of earlier decades were local and universal: Computer centres located in a fixed ambient serving a variety of users. Advances in Telecommunication and VLSI technologies have enabled the development of a new class of computing systems, which are Global and Embedded. Globality means that the same system may be required to operate in different ambient. This may require features of Adaptivity at the behavioral level and Reconfigurability at the architectural level. Embedded systems, on the other hand, have to operate under hard performance constraints. These features of current computing systems need a careful consideration of their associated Specifications and Design Methodologies.
Speakers at this Workshop were drawn from the practicing professionals and members of IFIP WG 1.3. The idea was to bring the industrial professionals and the academicians together for a better appreciation of the challenges in the industrial deployment of design and verification methodologies based on formal techniques. After in initial Overview and Goals of the Workshop by P.S. Subramanian (TCS) the Workshop featured talks and events in the following categories: Industrial Views Verification and Validation: The Industrial view N.H. Sathyaraja, GM R&D Verification aspects in VLSI Design Methodologies P. Venugopal, Texas Instruments India Adaptivity in Telecom P.S. Subramanian, TCS, Bangalore Performance Evaluation of Systems Pradeep Desai, Philips India Continuous Engineering of Automotive Systems Martin Grosse Rhode, Fraunhoffer Institute Design Methodologies Algebraic Specification techniques CASL Methodology Till Mossakowski, Lutz Schrder (University of Bremen) and Andrzej Tarlecki (Warsaw University) Interactive Verification of System Models with CafeOBJ Kokichi Futatsugi (JAIST) Design Notations Guidelines for understanding system requirements Christine Choppy (Universit Paris XIII) UML and OWL Pierre Yves Schobbens (University of Namur) Proof based Development Incremental proof-based development of systems and SoC verification Dominique Mery (Universit Henri Poincar) Talks on specific topics Formal Design of GALS Systems S.Ramesh (GM R&D Bangalore and IIT.Mumbai) Formal Methods for Smart Cards Bart Jacobs, (University of Nijmegen) Architectures for Distribution and Mobility Jose Luiz Fiadeiro (University of Leicester)
Panel Discussion Challenges in Industrial Deployment of Formal Methods Panelists: Sathyaraja, Ramesh (GM), Bart Jacobs (Univ. of Nijmegen), Martin Grosse Rhode (Franhaufer Inst) Moderator: P.S. Subramanian (TCS) The Workshop also featured a public talk on R&D at TCS by Prof. Mathai Joseph, TRDDC.
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Jayanta Lahiri, Alliance Semiconductor, speaking at the workshop The delegates interacted with the speakers in an informal environment. The CD, which includes the presentations made at the workshop, is available from VSI. For details, write to vsi_india@rediffmail.com
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The National Workshop on Challenges in VLSI (NWCV) 2005 was held on May 13 and 14 2005 at Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, Gujarat. Website: http://nwcv.da-iict.org/ The workshop was targeted at faculty and students of 4th year and above interested in VLSI. The workshop had two parallel themes: Day-1: Analog and Mixed Signal Design Design considerations for CMOS amplifiers by Dr. Dinesh Sharma, IIT Bombay Current research in D-to-A Converters by Dr. Chetan Parikh, DA-IICT Continuous Time Filter Design by Dr. Shanthi Pavan, IIT Madras Day01: Testing and Formal Verification Introduction to Formal Verification by Dr.P.P. Chakrabarti, IIT Kharagpur Mathematical Logic by Dr. Kalpesh Kapoor, DA-IICT Model Checking by Dr. Supratik Chakraborty,IIT Bombay Process Calculi for Concurrent Systems by Dr. Hemangee Kapoor, DA-IICT Formal Verification using the IITD-Concurrency Workbench by Dr. S. Arun Kumar, IIT Delhi Day-2: Analog and Mixed Signal Design Current Issues in Mixed-signal Design by Mr. Tapas Nandy, ST Microelectronics Current-mode Analog Design by Mr. Debashis Dutta, MCIT Substrate Noise Analysis for Mixed-Signal SOCs by Mr. S. Jairam, Texas Instruments India A-to-D Converters by Dr. G. Viswesaran, IITD Day-2: Testing and Formal Verification Testing of Digital System-on-Chip,SoC by Dr. Indranil Sengupta, IIT Kharagpur Formal Verification in Industry by Dr. Subir Roy, Texas Instruments Recent developments in Design-for-Test by Dr. C.P. Ravikumar, Texas Instruments India The Workshop concluded with a Panel Discussion: Future Challenges for VLSI Education and Research in India. The panelists included Dr. Dinesh Sharma (IIT Bombay), Dr. D. Nagchoudhuri (DA-IICT), Dr. C.P. Ravikumar (Texas Instruments), Dr. Indranil Sengupta (IIT Kharagpur), Dr. G.S. Visweswaran (IIT Delhi), and Dr. Tapan Dutta (ST Microelectronics). The vote of thanks was given by Prof. Ashok Amin, DA-IICT. The response to the workshop was extremely good. A total of 90 delegates attended the workshop, of whom 28 were faculty and 62 were students. According to the delegate feedback, 15 out of 16 speakers were rated by at least one delegate as one of the best two speakers. Dr. Chetan Parikh and Dr. Hemangee Kapoor were responsible for the technical planning and organization of the two sessions respectively. The organizing committee involved Prof. D. Nagchoudhuri (Chairman), Dr.Hemangee Kapoor (Secy), Prof Ashok Amin (Treas), Prof R.N. Biswas, Dr. Chetan Parikh, Dr. Amit Bhatt and Dr. Anil Roy. The external sponsors included VSI Society, IEEE Gujarat Section, Natsem, Intel, GUJCOST and GVFL.
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2nd VLSI Embedded Systems DSP Applications Seminar - VEDAS 2005: A Report
July 1-2, 2005, Sona College of Technology, Salem N.J.R. Muniraj, Sona College of Technology, Salem njrmuniraj@yahoo.com VSI was a co-sponsor for the second two-day Seminar on VLSI Embedded Systems DSP Applications (VEDAS 2005). The seminar was jointly sponsored by Sona VEDIC, Department of ECE, Sona College of Technology, Salem. The event was held in cooperation with the IEEE Circuits and Systems Society, Bangalore Chapter, IEEE Student Chapter, Sona College of Technology and IEEE TTTC (Asia South Pacific Region). Day - 1 Soft Errors in FPGA by Prof. V. Kamakoti, IIT Madras VLSI in Industry & Academia Bridging the Gap by Srinivasan Venkataraman, Synopsys Advanced VLSI Signal Processing by N.J.R. Muniraj, Sona College of Technology SOC Design with MEMS by Navkanta Bhat, IISc,Bangalore The last session included presentations of submitted papers. Day-2 Recent Advances in VLSI Test by C. P. Ravikumar, Texas Instruments Leakage Power in DSM VLSI - Sources and Solutions by Rahul Kumar, National Semiconductors Verification of Present Day SOCs by Vishal Dalal, Sasken DSP Architectures by Soujana Sarkar, Texas Instruments Trends and Opportunities in Semiconductor Disk Drives by V. Ranganathan, Sathyam, Chennai Embedded for Telecommunication, Automotive, Enterprise Server Computing Applications by Chandravel Sankarakumar, Sanmina, Bangalore The seminar concluded with a Valedictory Function. The event was attended by 120 participants, including faculty and students from Engineering colleges and industrial professionals. As can be expected, the majority of the participants came from Tamil Nadu. However, there were also several participants from Karnataka, Kerala, and West Bengal. The feedback from the participants was excellent.
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Name of the event: Type of the event: (Conference/ Symposium/ Workshop/ Tutorial/ Other [Please Specify] ) Is this a continuing event or a one-time event? Goals of the event: (If you have a website for the event, provide the URL) Expected number of participants: General Chair of the event: (Name and Affiliation) Contact Details for the General Chair: (Provide e-mail address, full mailing address, telephone and FAX) Program Chair and Program Committee: (Give the names of at least two members along with their contact details) Finance Chair with contact details: Budget (attach Excel Sheet): Percentage Sponsorship Expected from VSI (50% or higher) Do you need support for managing the technical program of the event? (Yes/No. If yes, provide the name and email contact of the event manager who will be responsible for the event. This person will have electronic access to all the documents submitted to the event.) Support Documents (Recommendations from Head of the Department/renowned persons in VLSI area, Feedback from past events, etc.) Any other information you would like to provide
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Cool Vision
Lateral Thinking
By C.P. Ravikumar If you are a fan of Dan Browns The Da Vinci Code, these puzzles will interest you. They say a picture is worth a thousand words. Look at each of the pictures below and guess what well known phrase they represent. I will solve a couple of them for you to get you started. Example 1: Example 2:
Since Sh is Shell in Unix, you might be able to decipher this as In a Nut Shell.
OK, now you are on your own! Have fun guessing the answers. Put your knowledge of Mathematic and Engineering to good use!!
Puzzle 1:
Puzzle 2:
B + B B + B
Puzzle 5: Puzzle 4:
Puzzle 3:
lim z0
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C S C A N I
CLUES ACROSS 3. A little push to the right, and you may be down by half? (5) 5. The natural form of silicon (4) 7. Grab the data and lock the door! (5) 8. Stop! the device cried, but its cry was truncated at the end! (8) 9. What a professor in a hurry would compress the circuits into? (4) 10. When you are going to get a bite, may be you should get 512! (4) 11. The Noble man who started it all for the IC industry! (4, 5) 12. The memory of a Hindu God? 14. How do you explain a signal not arriving when it is supposed to? (6,7) 15. A tiny attachment to mark something, including the price! (3) 16. Do this when the condition fails (4, 2) 20. A bus you take to get a management degree (4) 21. Pulse code modulation (3) 23. A place to hold the signature f a number of people? (4) 24. A lot of integrated circuits! (3) 26. Funny fellow - he offered a lot of resistance when I tried to give him a raise! (4,2) 27. The best part is, it can test itself! (4) 28. The input pin that shifts in test data (4,2) 1. 2.
CLUES DOWN The reason why the time piece began to shake? (5, 6) Why is this low-power circuit design style not moving? (6, 4) 5. What are these test channels doing in the cricket field? (6) 6. What Keats wrote for Princess Diana became a nonlinear device? (5) 8. The engagement gift that Ms. I.O. received? (2,4) 12. What did the logic synthesis expert do again to get the timing right? (6) 13. An activity common to birds and copper? (9) 17. Its strictly either you or me we cannot both say yes, we cannot both say no. (4) 18. What you might do to a signal thats feeling hot, may be? (6) 19. A clock generator? (4) 22. Some people say this is meaningless information from pushy salesmen who rattle off performance numbers for computers! (4) 23. Shows you the way to logic optimization, perhaps! (3) 25. An abbreviated stay to do analyze timing paths? (3) 26. A unit of time for writing a postscript? (2) 29. Number of states in tristate logic (5) 30. What is causing the delay in Mr. Input getting a raise? (4)
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Clues Across 1. DRAM feels a BIT better after this? (7, 5) 7. What most CAD tools search for (7) 8. A very big jolt in a very short interval of time? (7) 10. A listing of a program in small font can be called this? (9) 12. Real estate (4) 13. His famous rule has more to do with interconnect than with monthly payment to your landlord (4) 14. The microprocessor close to your hand, perhaps (3) 16. Turn this on to get data out (2) 20. In the race, data arrived later than clock (5,9) 22. After the bias reached this value, the diode opened its gate (5) 23. What has cooling of Aluminum got to do with optimization? (9) 24. The interface for the application programmer is all reversed (3) 25. Even the recipe for the CPU is not complete without the humble vegetable (3) 26. The question and answer rigmarole for the circuit? (4) 27. After this, you simply remember where you came from and go back (3) Answers to Lateral thinking: Puzzle 1: To be or not to be, thats the question Puzzle 2: Work under pressure Puzzle 3: Plug and Play Puzzle 4: Root Cause Puzzle 5: Sky is the limit
Clues Down 1. The very origin of the nasty four-sided figure (4,4,6) 2. Although touted as unipolar, this switch has three terminals! (3) 3. The point of origin of carriers (6) 4. Nor used world-wide (9,5) 5. The delayed Australian bird useful in verification (7) 6. What they call ground in diagrams (3) 9. What UV light can do to your memory? (5) 11. Multiply and accumulate in reversible logic? (3) 15. The Z in circuit theory (9) 17. The package that tasted a drink? (3) 18. A stubborn wire can act that way, causing problems (4,2) 19. Heed not what the value is (4,4) 21. What is the skinny male cow doing in my chip? (6)
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The draft must be made in the name of VLSI Society of India and must be sent along with a CD containing the advertisement material in WORD, PDF, or Coral Draw formats to the following address. Mr. Gopal Naidu Treasurer, VLSI Society of India Texas Instruments India Bagmane Tech Park, CV Raman Nagar, Bangalore 560093 Phone: 25099467
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VSI VISION August 2005 VLSI Society of India Registered Society under KSR Act 1960, Rule 1961 Website: http://vlsi-india.net/vsi E-mail: vsi_india@rediffmail.com Membership Form (For New membership and renewals) New Members to affix photograph.
1.
Your Name: Your Profession/ Designation: Your e-mail address: Your Contact address: Your Professional address (if different from above): Your Area of specialization: Would you like to review papers in events organized by VSI? : How many papers are you willing to review? : Your Brief bio-data: Attach separately How can you contribute to the activities of VSI? : What Activities would you like VSI to organize? : Details of Payment: Cash/ Credit Card DD no: Dated: Drawn on Bank: Amount: I agree to be a member of the VLSI Society of India and have read and understood the charter of the society. I will actively contribute towards the objectives of the society. Member Signature
Membership Rates: Yearly 5-yearly Student Member: Rs. 500/= N/A Non-student member: Rs. 1000/= Rs 4500/Corporate member: Rs. 10,000/= Rs 45000/The DD to be made out to: "VLSI Society of India" and payable at Bangalore. Mail the form along with the DD to: Mr. Gopal Naidu Texas Instruments (India) Pvt Ltd Bagmane Tech Park, Opposite LRDE, C.V.Raman Nagar Post, Bangalore: 560 093 (FAX: 91-80-25048213) Note: The photograph is for official records only and will not be imaged onto the membership card.
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Nomination for President: Dr. Biswadip Mitra Nomination for Secretary: Dr. C.P. Ravikumar
President:
Secretary:
___________ ___________
(Write-in) (Write-in)
Please put the ballot in the ballot box at the registration desk of VDAT 2005 Symposium if you plan to attend the event during Aug 10-13, 2005. Alternately, please mail the ballot in a sealed envelope to:
Mr. Gopal Naidu Treasurer, VLSI Society of India Texas Instruments, Bagmane Tech Park, C.V. Raman Nagar, Bangalore: 560 093
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