A4-R3: COMPUTER ORGANIZATION

NOTE:
1. There are TWO PARTS in this Module/paper. PART ONE contains FOUR questions and
PART TWO contains FOUR questions.

2. PART ONE is to be answered in the TEAR-OFFANSWER SHEET only, attached to the

question paper, as per the instructions contained therein. PART ONE is NOT to be
answered in the answer book.

3. Maximum time allotted for PART ONE is ONE HOUR. Answer book for PART TWO will be
supplied at the table when the answer sheet for PART ONE is returned. However,
candidates who complete PART ONE earlier than one hour, can collect the answer book for
PART TWO immediately after handing over the answer sheet for PART ONE.
TOTAL TIME: 3 HOURS TOTAL MARKS: 100
(PART ONE-40; PART TWO – 60)

PART ONE
(Answer all the questions)

1. Each question below gives a multiple choice of answers. Choose the most appropriate
one and enter in the “tear-off” answer sheet attached to the question paper, following
instructions therein. (1 x 10)

1.1 The minimum number of flip-flops required to implement a 16-bit ring counter is ____
A) 4
B) 8
C) 16
D) 65, 536

1.2 The minimum hardware required to construct a 3 to 8 decode is ____

A) two 2-to-4 decoders
B) two 2-to-4 decodes and a 1-to-2 decoder
C) three 2-to-4 decoders
D) depends on the technology (TTL, CMOS, etc.)

1.3 A CPU has a 16-bit program counter. This means that the CPU can address ____
A) 16K memory locations
B) 32K memory locations
C) 64K memory locations
D) 256K memory locations

1.4 CARRY, in a half adder, can be obtained by using ____

A) EX - OR gate
B) AND gate
C) OR gate
D) EX - NOR gate

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1.5 CPU gets the address of next instruction to be processed from
A) Instruction register
B) Memory address register
C) Index register
D) program counter

1.6 A bootstrap is ____

A) a memory device
B) a program to start a computer
C) Hardware of computer used to check memory
D) an assembler

1.7 When the value 37H is divide by 17H, the remainder is

A) 00 H
B) 03 H
C) 07 H
D) 09 H

1.8 A linker is a program which generates ____

A) the executable program from object programs
B) an object- program from an assembly language program
C) an assembly language program from a high level language program
D) the executable program from a high level language program

1.9 Cycle stealing refers to ____

A) reduction in the number of clock cycles for memory access in a cache memory
B) overlapping of the memory refresh operation and memory read operations in
dynamic memories
C) reduction in instruction cycle time through instruction pipelining
D) None of the above

1.10 A nano control memory is implemented to

A) improve the speed of execution
B) reduce the overall control memory size
C) reduce the complexity of hardware
D) None of the above

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2. Each statement below is either TRUE or FALSE. Choose the most appropriate one and
ENTER in the “tear-off” sheet attached to the question paper, following instructions
therein. (1 x 10)

2.1 A static RAM does not require a refresh input.

2.2 A tag directory is unnecessary in direct mapped caches.
2.3 The width of the program counter of a CPU, which can address 200 MB of main memory, is
at least 32 bits.
2.4 A dirty bit is associated with each block of a write back cache.
2.5 A page refers to the organization of address space, while a block refers to the organization of
memory space.
2.6 A programming error, such as forgetting to declare a label in the program, cannot be
detected by a single – pass assembler.
2.7 PUSH is a zero – address instruction.
2.8 Instruction register is not accessible to the assembly program of almost all computers.
2.9 Decoding of instruction takes place in several steps of the execution phase.
2.10 All vectored interrupts are hardware interrupts.

3. Match words and phrases in column X with the closest related meaning/
word(s)/phrases in column Y. Enter your selection in the “tear-off” answer sheet
attached to the question paper, following instructions therein. (1 x 10)

X Y
3.1 Asynchronous communication A. Second level of control memory
3.2 Scratch pad memory B. Separate Input & Output instructions
3.3 RISC C. PUSH and POP
3.4 Nibble D. A String of 4-bits
3.5 Stack addressing E. UART
3.6 Flip flop F. USART
3.7 I/O mapped I/O G. One instruction per clock cycle
3.8 Nano memory H. Digital signal processor TM S320 C30
3.9 Harvard architecture I. Astable multivibrator
3.10 Hard disc drive J. Bistable multivibrator
K. Secondary memory
L. Cache memory
M. Set of registers
N. Micro-controller
O. UNIX
P. Demultiplexer

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4. Each statement below has blank space to fit one of the word(s) or phrases in the list
below. Enter your choice in the “tear-off” answer sheet attached to the question
paper, following instructions therein. (1 x 10)

A. Faster B. Polling C. I/O Pins

D. 7 E. -128 F. AB + BC + CA
G. X H. Stack I. Replacement
J. -X K. More L. Update
M. Scheduling N. O O. I/O operations
P. -256 Q. Dirty R. Interleaving
S. T. Negative U. 6
+ +
A B C

V. ABC W. One's complement X. Logical AND

Y. Sign Extension Z. less AA. Slower
AB. -64 AC. +256

4.1 Y is the two’s complement of a number X. The two’s complement of Y will give us ______.

4.2 The ______ bit is used in a write back cache to avoid unnecessary updates o main memory
pages.

4.3 The smallest negative integer that can be represented in 8 bit two’s complement notation is
______.

4.4 A hardware control unit is ______, when compared to a micro programmed control unit.

4.5 First-in-first-out (FIFO) is a(n) ______ policy in a fully associative cache.

4.6 The minimum number of bits, required to represent the number –53 using 2’s complement
notation is, ______.

4.7 In early microprocessors, designers used the multiplexing of address and data lines, in order
to save the number of ______.

4.8 Taking the ______ of a number and adding 1, will give us the tow’s complement of the
original number.

4.9 The sum output in a full adder, with inputs A, B and C, is given by the Boolean expression
______.

4.10 The amount of storage required, in a horizontally organized microstore, is ______ than the
amount of storage required in a vertically organized microstore.

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 PART TWO
(Answer any four questions)

5.
a) Obtain the simplified Boolean function of the full Adder in sum of product form and draw the
logic diagram using NAND gate.
b) Simplify the Boolean function F (A, B, C) = Σ (0, 2, 6) having the don’t care condition
d (A, B, C) = Σ (1, 3, 5)
(6+9)

6.
a) Give the merits and demerits of the floating point and fixed-point representations for storing
real numbers.
b) What is the bootstrap loader and why must every computer have one? List 4 ways loading a
bootstrap routine into a computer.
c) Explain the concept of associative memory.
(4+6+5)

7.
a) Differentiate between cache memory and virtual memory.
b) Given 1287 x 8 RAM & 512 x 8 ROM chips
i) How many chips are needed to provide a memory capacity of 512 bytes of RAM &
512 bytes of ROM?
ii) How many lines of address bus must be used to access the above mentioned
memory address map?
iii) How will you differentiate between a RAM & ROM address?
(6+9)

8.
a) Explain the meanings of macro and subroutine. Compare between them.
b) When we write an assembly language program, what are the essential components that we
include in every line?
c) Write a note in brief on Ripple counters.
(5+7+3)

9.
a) What is meant by “interrupt priority”?
b) What is the role of an interrupt controller in a computer?
c) Describe the concurrency control and deadlock of an operating system.
(4+5+6)

A4-R3 Page 5 of 5 JANUARY, 2004

 A4-R3: COMPUTER ORGANIZATION

NOTE:
1. There are TWO PARTS in this Module/paper. PART ONE contains FOUR questions and
PART TWO contains FOUR questions.

2. PART ONE is to be answered in the TEAR-OFFANSWER SHEET only, attached to the

question paper, as per the instructions contained therein. PART ONE is NOT to be
answered in the answer book.

3. Maximum time allotted for PART ONE is ONE HOUR. Answer book for PART TWO will be
supplied at the table when the answer sheet for PART ONE is returned. However,
candidates who complete PART ONE earlier than one hour, can collect the answer book for
PART TWO immediately after handing over the answer sheet for PART ONE.
TOTAL TIME: 3 HOURS TOTAL MARKS: 100
(PART ONE-40; PART TWO – 60)

PART ONE
(Answer all the questions)

1. Each question below gives a multiple choice of answers. Choose the most appropriate
one and enter in the “tear-off” answer sheet attached to the question paper, following
instructions therein. (1 x 10)

1.1 One bit Full Adder can be designed using

A) Two Half Adders and one OR gate

B) Two Half Adders
C) One Ex-OR and two NAND gates
D) Two Ex-OR and four NAND gates

1.2 Octal number system is

A) A positional system with weights 0 to 9

B) A positional system with weights 0 to 8
C) A positional system with weights 0 to 7
D) A non positional system with weights 0 to 7

1.3 A 4 digit BCD number can be represented with the help of

A) 10 bits
B) 08 bits
C) 12 bits
D) 16 bits

1.4 A CPU consists of

A) ALU, Control Unit, and Registers

B) ALU, and Control Unit
C) ALU, Control Unit, and Hard Disk
D) ALU, Control Unit, and Key Board

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1.5 In the memory hierarchy the fastest memory is

A) SRAM
B) Cache
C) CPU registers
D) DRAM

1.6 For execution of an interrupt applied at INTR, number of states required by 8085
Microprocessor are

A) 4
B) 6
C) 12
D) 18

1.7 The Immediate addressing mode of instruction provides the operand in the memory location

A) Pointed by the PC
B) Next to that of OP code
C) Pointed by PC + 1
D) None of these

1.8 After execution of POP rp instruction in 8085

A) SP is decremented by one
B) SP is neither incremented nor decremented
C) SP is incremented by one
D) SP is incremented by two

1.9 ORG 100 is interpreted by an assembler as

A) CPU instruction
B) The subsequent instruction starts at 100 location in the memory
C) The subsequent instruction starts at 101 location in the memory
D) A directive to execute the subsequent instruction

1.10 Bi-directional buses use

A) Tri-state buffers
B) Two tri-state buffers in cascade
C) Two back to back connected tri-state buffers in parallel
D) Two back to back connected buffers

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2. Each statement below is either TRUE or FALSE. Choose the most appropriate one and
ENTER in the “tear-off” sheet attached to the question paper, following instructions
therein. (1 x 10)

2.1 A 4x1 multiplexer can be designed with the help of four 2 input AND gates and one 4 input
OR gate.
2.2 Booth’s algorithm is used to multiply negative numbers.
2.3 2’s complement of 101011002 is 010101002.
2.4 An IOP reduces performance of IO.
2.5 Static RAMs are used in Personal Computers as main memory.
2.6 Master slave J-K Flip Flop in configured from two J-K Flop Flops.
2.7 IN macros groups of instructions are not treated as single entities.
2.8 Horizontal microinstructions have little encoding.
2.9 A demultiplexer is required to make output of ALU as one of its operands.
2.10 In an IO mapped IO additional IO instructions are needed to communicate with the IO
device.

3. Match words and phrases in column X with the closest related meaning/
word(s)/phrases in column Y. Enter your selection in the “tear-off” answer sheet
attached to the question paper, following instructions therein. (1 x 10)

X Y
3.1 Hexadecimal A. DMA
3.2 Memory Hierarchy B. Seven segment display
3.3 PUSH C. Daisy Chaining
3.4 Cycle stealing D. Locality of Reference
3.5 Interrupt Priority E. Increment in Sp
3.6 James E. Robertson F. Virtual Memory
3.7 High Speed Adder G. Stealing of Instruction Cycle
3.8 Implicit Addressing Mode H. 2's complement multiplication
3.9 Assembler directives I. Carry-look ahead
3.10 Control Unit J. Address out side op code
K. Carry Propagation Adder
L. Address is inbuilt in instruction
M. Executable statements
N. Non executable statements
O. CPU
P. Decrement in stack pointer

A4-R3 Page 3 of 5 JULY, 2004

4. Each statement below has blank space to fit one of the word(s) or phrases in the list
below. Enter your choice in the “tear-off” answer sheet attached to the question
paper, following instructions therein. (1 x 10)

A. One B. Two C. State table

D. 64 bit data bus E. Indirect F. Three adjacent bits
G. Enable Interrupt H. 64 bit address I. User level
J. One of the two K. System level L. Data input
M. One clock N. Different clocks O. Both
P. Direct Q, Two adjacent bits R. Data output

4.1 A 64 bit microprocessor has _________.

4.2 It is desirable to make hit ratio is close to _________ as possible.
4.3 A Finite State Machine can be represented by _________.
4.4 Modified Booth algorithm examines _________ of the multiplier at a time.
4.5 CPU recognizes an interrupt if _________ instruction is executed.
4.6 In a register transfer instruction op code provides the address of _________ registers.
4.7 Assembler is a(n) _________ program, which translates assembly language program to
machine language
4.8 A decoder can function as demultiplexer with enable input used as _________.
4.9 Synchronous IO transfer schemes operate from _________.
4.10 A memory reference register contains the address for the _________ addressing.

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 PART TWO
(Answer any FOUR questions)

5. Show how can an eight input multiplexer be constructed from two input multiplexers. The two
input multiplexer has enable input in addition to select inputs. Draw diagram of the
constructed multiplexer with suitable labels.
(15)

6. Give an algorithm for nonrestoring division for unsigned numbers.

(15)

7. State two limitations of Programmed IO method of data transfer scheme. How are these
limitations eliminated in DMA? Explain this method with the help of basic diagram showing
CPU, Memory and DMA controller connectivity. The DMA block in the diagram is to be drawn
with its essential components.
(15)

8.
a) Calculate the average latency and the data-transfer rate of a moving-arm disk-storage device
that has 200 tracks per recording surface, 2400 rpm and 62,500 bits track storage capacity.
b) Construct a 1M x 16-bit memory having four memory banks with four-way address
interleaving. Identify the bank to which each of the following hex encoded addresses is
assigned.
i) 0123
ii) ABCDE
(7+8)

9. Write a assembly language program to add two 16-bit numbers on 8-bit processor, 8085
(say).
(15)

A4-R3 Page 5 of 5 JULY, 2004

 A4-R3: COMPUTER ORGANIZATION

NOTE:
1. There are TWO PARTS in this Module/paper. PART ONE contains FOUR questions
and PART TWO contains FOUR questions.

2. PART ONE is to be answered in the TEAR-OFFANSWER SHEET only, attached to

the question paper, as per the instructions contained therein. PART ONE is NOT to
be answered in the answer book.

3. Maximum time allotted for PART ONE is ONE HOUR. Answer book for PART TWO
will be supplied at the table when the answer sheet for PART ONE is returned.
However, candidates who complete PART ONE earlier than one hour, can collect
the answer book for PART TWO immediately after handing over the answer sheet
for PART ONE.
TOTAL TIME: 3 HOURS TOTAL
MARKS: 100
(PART ONE-40; PART
TWO – 60)

PART ONE
(Answer all the questions)

1. Each question below gives a multiple choice of answers. Choose the most
appropriate one and enter in the “tear-off” answer sheet attached to the
question paper, following instructions therein.
(1 x 10)

1.1 A Toggle flip-flop can be constructed using a JK flip-flop by connecting the

A) toggle input to J and the inverted from of toggle input to K.
B) the toggle input to J
C) inverted form of toggle input to K.
D) None of the above

1.2 The number of select input lines in an 8-to-1 multiplexer is

A) 1
B) 8
C) 256
D) None of the above

1.3 CARRY, in half adder, can be obtained using

A) EX - OR gate
B) AND gate
C) OR – gate
D) EX - NOR gate

1.4 Booth algorithm gives procedure for multiplying binary integers in

A) signed magnitude representation
B) unsigned representation
C) 2’s complement representation
D) None of the above

A4-R3 Page 6 of 5 JULY, 2004

1.5 a memory device, in which a bit is stored as a charge across the stray capacitance
A) SRAM
B) EPROM
C) DRAM
D) bubble memory

1.6 Fetch operations are not required in

A) Direct addressing
B) immediate addressing
C) indirect addressing
D) register addressing

1.7 A debugging tool is a program which

A) removes bugs from user program
B) removes viruses from the computer
C) helps the user find bugs in his program
D) displays the errors in a user program

1.8 A diamond-shaped box in a flow chard refers to

A) An assignment statement
B) printing of a file
C) an if – then – else decision
D) data input from a device

1.9 In the difference between a COMPARE instruction and a SUBTRACT instruction is

A) COMPARE instruction does not set any flags
B) SUBTRACT instruction does not set any flags
C) COMPARE leaves the registers unchanged
D) COMPARE instruction does not require the ALU

1.10 In the IEEE 754 floating point representation standard, the base is
A) 23
B) 127
C) 16
D) None of the above

A4-R3 Page 7 of 5 JULY, 2004

2. Each statement below is either TRUE or FALSE. Choose the most appropriate
one and ENTER in the “tear-off” sheet attached to the question paper,
following instructions therein.
(1 x 10)

2.1 When the multiplier is 01 (decimal), Booth’s multiplication algorithm requires one
addition and one subtraction.
2.2 A queue is a first –in first – out structure
2.3 When a right shift operation is performed on two’s complement numbers, zeros must
be shifted from the left.
2.4 A software interrupt is an instruction executed by the CPU.
2.5 An instruction cycle always consists of one memory read operation.
2.6 PUSH is a zero-address instruction.
2.7 In Boolean algebra Wx+ yx + Wy can be reduced to Wx+ yx.
2.8 Decoding on instruction takes place in several steps of the execution phase.
2.9 The set of microinstructions are stored in RAM.
2.10 An astable multivibrator can be used as flip-flop.

3. Match words and phrases in column X with the closest related meaning/
word(s)/phrases in column Y. Enter your selection in the “tear-off” answer
sheet attached to the question paper, following instructions therein.
(1 x 10)

X Y
3.1 Segment registers A. Immediate addressing
3.2 Cache memory B. Micro-controller
3.3 (ab)' = a' + b' C. NOP
3.4 A single chip computer D. Master/slave JK – Flip-flop
3.5 An instruction to provide small delays E. 8086 CPU
3.6 Hamming code F. Hard Copy
3.7 Seek time G. RAM
3.8 LRU H. Error detecting and correcting code

A4-R3 Page 8 of 5 JULY, 2004

3.9 Address is an operand I. Page replacement policy
3.10 Racing problems do not exist J. De-Morgan's theorem
K. Locality of reference
L. Hard disk reference

4. Each statement below has blank space to fit one of the word(s) or phrases in
the list below. Enter your choice in the “tear-off” answer sheet attached to the
question paper, following instructions therein.
(1 x 10)

A. Faster B. I/O Mapped I/O C. Harvard

D. X E. Assembly F. Dirty
G. -128 H. Hamming distance I. -256
J. Logical AND K. I/O Pins L. Hamiltonian distance
M. 16

4.1 Y is the two’s complement of a number X. The two complement of Y will give us
_______.

4.2 The smallest negative integer that can be represented in 8-bit two’s complement
notation is _______.

4.3 The _______ bit is used in a write back cache to avoid unnecessary updates of main
memory pages.

4.4 A hardwired control unit is _______, when compared to a micro-programmed control

unit.

4.5 Address lines and data lines are sometimes multiplexed in order to restrict the
_______.

4.6 The kernel of an operating system is likely to be written in _______ language of the
underlying processor in order to improve the performance.

A4-R3 Page 9 of 5 JULY, 2004

4.7 In a grey code sequence, the _______ between any two successive numbers is 1.

4.8 The number of 256 x 4 RAM chips required to contract a 2KB cache is _______.

4.9 When input/ output is performed, using instructions such as IN and OUT which are
meant for I/O devices, the mapping scheme used is called _______.

4.10 A digital computer, in which data memory is separated from instruction memory, is
said to have _______ architecture.

PART TWO
(Answer all questions)

5.
a) Show, how cache memory may be organized in a computer?
b) Explain the need of memory hierarchy. What is the main reason for not having a
large main memory for storing the totality of information in a computer system?
(6+9)

6.
a) When we write an assembly language program, what are the three essential columns
that we include in every line? Explain the significance of each of these.
b) Write and explain an assembly language program to subtract two numbers.
c) What is meant by a macro? Compare the relative merits and demerits of using
macros instead of subroutines in a program
(5+5+5)

7.
a) Explain the difference between combinational and sequential logic.
b) Explain how a JK flip-flop can be realized from a R-S flip-flop? What is Toggle flip-
flop?
c) What is the difference between zero – address, one – address and two address
instructions? Illustrate with the help of examples.
(4+4+7)

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8.
a) What is microinstruction? Distinguish between horizontal and vertical
microinstructions.
b) Explain the organization of control memory. How is control unit implemented using
control memory?
c) What is the difference between direct-address and indirect address mode? Explain
relative and base – register addressing.
(4+6+5)

A4-R3 Page 11 of 5 JULY, 2004