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A Low-Power Delay Buffer Using Gated Driver Tree

Po-Chun Hsieh, Jing-Siang Jhuang, Pei-Yun Tsai, Member, IEEE, and Tzi-Dar Chiueh, Senior Member, IEEE
AbstractThis paper presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) ip-ops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. Both simulation results and experimental results show great improvement in power consumption. A 256 8 delay buffer is fabricated and veried in 0.18 m CMOS technology and it dissipates only 2.56 mW when operating at 135 MHz from 1.8-V supply voltage. Index TermsC-element, delay buffer, rst-inrst-out (FIFO), gated-clock, ring-counter.

I. INTRODUCTION

ORTABLE multimedia and communication devices have experienced explosive growth recently. Longer battery life is one of the crucial factors in the widespread success of these products. As such, low-power circuit design for multimedia and wireless communication applications has become very important. In many such products, delay buffers (line buffers, delay lines) make up a signicant portion of their circuits [1][3]. Such serial access memory is needed in temporary storage of signals that are being processed, e.g., delay of one line of video signals, delay of signals within a fast Fourier transform (FFT) architectures [4], and delay of signals in a delay correlator [2]. Currently, most circuits adopt static random access memory (SRAM) plus some control/addressing logic to implement delay buffers. For smaller-length delay buffers, shift register can be used instead. The former approach is convenient since SRAM compilers are readily available and they are optimized to generate memory modules with low power consumption and high operation speed with a compact cell size. The latter approach is also convenient since shift register can be easily synthesized, though it may consume much power due to unnecessary data movement. Previously, a simplied and thus lower-power sequential addressing scheme for SRAM application in delay buffers is proposed in [5]. A ring counter is used to point to the target words
Manuscript received June 29, 2007; revised April 29, 2008. First published March 16, 2009; current version published August 19, 2009. This work was supported in part by the National Science Council, Taiwan, under Grant NSC-952219-E-002-020 and NSC-96-2220-E-002-020. P.-C. Hsieh, J.-S. Jhuang, and T.-D. Chiueh are with the Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan. P.-Y. Tsai was with the Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan. She is now with the Department of Electrical Engineering, National Central University, Jhong-Li 32001, Taiwan. Digital Object Identier 10.1109/TVLSI.2008.2004704

to be written-in and read-out. Since the ring counter is made up of an array of D-type ip-ops (DFFs) triggered by a global clock signal and all except one DFFs have a value of 0, it is possible to disable the clock signal to most DFFs. Such a gated-clock ring counter is implemented in [6] to compose a low-power rst-inrst-out (FIFO) memory. In this paper, we propose to use double-edge-triggered (DET) ip-ops instead of traditional DFFs in the ring counter to halve the operating clock frequency. A novel approach using the C-elements instead of the RS ip-ops in the control logic for generating the clock-gating signals is adopted to avoid increasing the loading of the global clock signal. In addition to gating the clock signal going to the DET ip-ops in the ring counter, we also proposed to gate the drivers in the clock tree. The technique will greatly decrease the loading on distribution network of the clock signal for the ring counter and thus the overall power consumption. The same technique is applied to the input driver and output driver of the memory part in the delay buffer. In a delay buffer based on the SRAM cell array such as the one in [6], the read/write circuitry is through the bit lines that work as data buses. In the proposed new delay buffer, we use a tree hierarchy for the read/write circuitry of the memory module. For the write circuitry, in each level of the driver tree, only one driver along the path leading to the addressed memory word is activated. Similarly, a tree of multiplexers and gated drivers comprise the read circuitry for the proposed delay buffer. Simulation results show the effectiveness of the above techniques in power reduction. As an example, a 256 8 delay buffer chip is designed and fabricated. Measured results indicate its much better power performance than the same-size delay buffer based on existing commercial SRAM. The rest of this paper is organized as follows. Section II rst introduces the conventional architecture for implementing delay buffers. Next, the proposed delay buffer using the new ring counter and gated driver trees for the read and write circuits of the memory module is described in Section III. Section IV then presents experimental results of the new delay buffer. Also, comparison in power and area of the new delay buffer with conventional SRAM-based delay buffers are given. Section V then concludes this paper. II. CONVENTIONAL DELAY BUFFERS The simplest way to implement a delay buffer is to use shift and the registers as shown in Fig. 1. If the buffer length is word-length is , then a total of DFFs are required, and it can be quite large if a standard cell for DFF is used. In addition, this approach can consume huge amount of power since on the binary signals make transitions in every clock average cycle. As a result, this implementation is usually used in short delay buffers, where area and power are of less concern.

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Fig. 1. Delay buffer implemented by shift registers.

Fig. 3. Ring counter with clock gated by RS ip-op.

III. PROPOSED DELAY BUFFER In the proposed delay buffer, several power reduction techniques are adopted. Mainly, these circuit techniques are designed with a view to decreasing the loading on high fan-out nets, e.g., clock and read/write ports. A. Gated-Clock Ring Counter
Fig. 2. Pointer-based delay buffer.

SRAM-based delay buffers are more popular in long delay buffers because of the compact SRAM cell size and small total area. Also, the power consumption is much less than shift registers because only two words are accessed in each clock cycle: one for write-in and the other for read-out. A binary counter can be used for address generation since the memory words are accessed sequentially. Though the SRAM-based delay buffers do away with many data transitions, there still can be considerable power consumption in the SRAM address decoder and the read/write circuits. In fact, since the memory words are accessed sequentially, we can use a ring counter with only one rotating active cell to point to the words for write-in and read-out. This method, known as the pointer-based scheme [5], is illustrated in Fig. 2. The bottom row of D-type ip-ops is initialized with only one 1 (the active cell) and all the other DFFs are kept at 0. When a clock edge triggers the DFFs, this 1 signal is propagated forward. Consequently, the traditional binary address decoder can be replaced by this unary-coded ring counter. Compared to the shift register delay buffers, this approach propagates only one -bit words. 1 in the ring counter instead of propagating Obviously, with much less data transitions, the pointer-based delay buffers can save a lot of power. By observing the fact that only one of the DFFs in the ring counter is activated, the gated-clock technique has then been proposed to be applied to the DFFs in [6]. In their approach, every eight DFFs in the ring counter are grouped into one block. Then, a gate signal is computed for each block to gate the frequently toggled clock signal when the block can be inactive so that unnecessary power wasted in clock signal transitions is saved. As shown in Fig. 3, when the input of the rst DFF in a block is asserted, it sets the output of the RS ip-op to 1 at the next clock edge. Thus, the incoming 1 can be trapped in that block and continue to propagate inside the block. On the other hand, the successful propagation of 1 to the rst DFF in the next block can henceforth shut down the unnecessary clock signal in the current block.

Although some power is indeed saved by gating the clock signal in inactive blocks, the extra RS ip-ops still serve as loading of the clock signal and demand more than necessary clock power. We propose to replace the RS ip-op by a C-element and to use tree-structured clock drivers with gating so as to greatly reduce the loading on active clock drivers. Additionally, DET ip-ops are used to reduce the clock rate to half and thus also reduce the power consumption on the clock signal. The proposed ring counter with hierarchical clock gating and the control logic is shown in Fig. 4. Each block contains one C-element to control the delivery of the local clock signal CLK to the DET ip-ops, and only the CKE signals along the path passing the global clock source to the local clock signal are active. The gate signal (CKE ) can also be derived from the output of the DET ip-ops in the ring counter. The C-element is an essential element in asynchronous circuits for handshaking. One of its implementation is shown in Fig. 5(a) [7]. The logic of the C-element is given by (1) where as well as are its two inputs and as well as are the next and current outputs. If , then the next output will be the same as . Otherwise, and remain unchanged. Since the output of C-element can only be changed , it can avoid the possibility of glitches, a cruwhen cial property for a clock gating signal. In order to reduce more power, we replace DFFs by double-edge-triggered ip-ops [8] [see Fig. 5(b)] and operate the ring counter at half speed . With such changes, the clock gating control mechanism in Fig. 4(a) is different from the one in Fig. 3. When the input of the last DET ip-op in the previous block changes to 1 making both two inputs of the C-element the same, the clock signal in the current block will be turned on. When the output of the rst DET ip-op in the current block is asserted, then both inputs of the C-element in the previous block go to 0 and the clock for the previous block is disabled. In order to further diminish the loading on the global clock signal (CLK), we propose to use a driver tree distribution network for the global clock and activate only those drivers along

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Fig. 4. (a) Ring counter with clock gated by C-elements, (b) tree-structured clock drivers with gating, and (c) control logic for clock enable signals.

Fig. 6. (a) Circuit of the clock enable signal for the gated-clock driver tree and (b) its timing diagram.

derived from the same clock gating signals of the blocks that they drive. Thus, in a quad-tree clock distribution network, the gate signal of the th gate driver at the th level (CKE ) should be asserted when the active DET ip-op (whose output is 1) in the ring counter is inside the group of blocks with to , where is the number index from of blocks. To be precise, every clock gating signal will be on for two more cases, when 1 is at the input of last DET ip-op in and when 1 is at the output of the rst DET block . In a quad-tree driver architecture ip-op of block with four times more drivers in each level, all drivers need be activated if no gating is applied and the number of active drivers is given by (2) On the other hand, only drivers are activated in the worst case for the proposed gated-clock tree when two drivers level. On the average, there are activated in each of the drivers that are turned on, are no more than where is the number of DET ip-ops in one block. . If the active An example is illustrated in Fig. 6 with 1 in the ring counter is propagated to the input of the last DET , then the clock enable signals, CKE and ip-op, Q CKE , are turned on. Subsequently, CLK and CLK can

Fig. 5. Circuit diagrams of (a) the C-element [7] and (b) the double-edge-triggered ip-op [8].

the path from the clock source to the blocks that need to be driven by the clock. The gate signal for those drivers can be

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TABLE I POWER CONSUMPTION OF THREE RING COUNTERS

be delivered to block 49. On the contrary, when Q rises, it and CKE . As will turn off the clock enable signals of CKE and CLK stop driving their loading blocks. a result, CLK The loading of the clock signal in the proposed scheme can be analyzed as follows. Assume that a quad tree is used for clock drivers, then for a length- ring counter constituted by a total blocks. of ip-ops partitioned in Loading of a traditional ring counter (3) Loading of [6] (4) Loading of the proposed ring counter (5) where , , and denote the loading of a D-type ip-op clock input, an AND gate input and an RS ip-op clock input, respectively. In Table I, we have simulated three different ring counter structures using 0.18- m CMOS technology and 1.8-V supply voltage at an operating frequency of is set to 1024, and 50 MHz. The length of the ring counter eight ip-ops are grouped in one block ( , ). , , and is If we assume that the ratio between 2 : 1 : 2, the estimated loading ratios of the three architectures are also listed in the table. The simulation results indeed reect the power consumption analysis in (3)(5). It also indicates that it consumes less than 5% of the power of a same-length RS ip-op-based ring counter [6] (Fig. 3). B. Gated-Driver Tree To save area, the memory module of a delay buffer is often in the form of an SRAM array with input/output data bus as in [6]. Special read/write circuitry, such as a sense amplier, is needed for fast and low-power operations. However, of all the memory cells, only two words will be activated: one is written by the input data and the other is read to the output. Driving the input signal all the way to all memory cells seems to be a waste of power. The same can be said for the read circuitry of the output port. In light of the previous gated-clock tree technique, we shall apply the same idea to the input driving/output sensing circuitry in the memory module of the delay buffer. The memory words are also grouped into blocks. Each memory block associates with one DET ip-op block in the proposed ring counter and one DET ip-op output addresses a corresponding memory word for read-out and at the same time addresses the word that was read one-clock earlier for write-in.

Fig. 7. (a) Gated-driver tree of input driving circuitry and (b) its timing diagram.

Fig. 7(a) depicts the tree-structured hierarchy of tri-state inverters used for delivering the input word to the addressed memory word. Note that only the driver tree for one input bit is shown. A -bit delay buffer needs sets of the circuitry in Fig. 7. The enable signal of the th tri-state inverter at the th ) should be asserted when the 1 is within one of level ( to index in the the blocks from index is the number of blocks and a quad tree ring counter, where is assumed. These signals are generated by a C-element and an inverter in a similar way as the circuit shown in Fig. 4(a) except that the input signal to the C-element from left (start-up) is the output of the rst DET ip-op in block and the signal from right (shut-off) is the output of the rst . The corresponding timing DET ip-op in block diagram of control and data signals is shown in Fig. 7(b). As , the output of the rst can be seen, the assertion of Q DET ip-op in block 49, activates , , and , and , , and The content simultaneously disables , (address 384), is of the memory word addressed by Q written by the input signal.

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TABLE II POWER CONSUMPTION OF THE INPUT DRIVER TREE WITH AND WITHOUT THE GATING STRATEGY

The loading of the input write circuitry can be estimated. Without gating strategy, it is (6) With gated driver tree, it is (7) where and are the loading of one latch and one tri-state buffer, respectively. In the estimation, a quad tree is assumed. We can see the logarithmical decrease in loading can dramatically reduce the power consumption. In Table II, we have simulated input driver tree structures with and without the gating strategy by using 0.18- m CMOS technology and 1.8-V supply voltage at an operating frequency of 50 MHz. Due to the driving capability, buffer sizing is considered in the simulation must be included in and equivalently extra loading of 12 . If the loading ratio between (6) and (7) for the case and is 1:2.8, the estimated power consumption ratio by (6) and (7) also matches very well with the simulated results. The output sensing circuit has the same structure as that in Fig. 7(a) except that the signal ow direction is reversed. Data in the addressed memory element pass through several levels of tri-state inverters that work as the multiplexer. The same set of enable signals (E ) can be used to control these output tri-state inverters. Note that the proposed techniques can also be applied to variable-length delay buffers. First of all, the proposed ring counter can be made variable-length by including alternative signal paths selected by multiplexers to bypass some DET ipops in the ring. Second, as all the control signals of the gatedclock/driver tree are derived from the ring counter, a complete delay buffer with variable length can be constructed quite easily by including the latches and gated I/O driver trees. Of course, in this variable-length delay buffer, hardware corresponding to the maximum length must be implemented. IV. EXPERIMENTAL RESULTS A. Physical Design A delay buffer based on the proposed techniques is designed and implemented in 0.18- m CMOS technology. The standard 6-T SRAM cell is used in the delay buffer. Eight DET ip-ops, eight memory words, and associated control logic are designed in a full-custom fashion and grouped as one block. We have simulated the proposed delay buffer with various lengths in 0.18 m CMOS technology. The word-length is set to 8 bits. The area

Fig. 8. Simulated results of (a) power and (b) area of various delay buffers versus different lengths.

and power consumption are estimated from post layout simulation. In addition, we compared the simulated results with the values provided by a commercial SRAM compiler in the same technology. Since in each clock cycle, one read and one write operations are necessary for the delay buffer of length , either one two-port SRAM with words or two one-port SRAMs each with words is required. Fig. 8(a) shows the simulated power consumption at 135-MHz operating frequency and 1.8-V supply voltage. Fig. 8(b) depicts their occupied area. From Fig. 8, we can see that the proposed delay buffer outperforms both the two-port and single-port SRAM-based delay buffers in terms of power consumption. In addition, the area of the proposed delay buffer is smaller than the SRAM-based delay buffers when the buffer length is shorter than 256. A 256 8 delay buffer is designed and fabricated. In this circuit, a wordlength of one byte is adopted for this size is quite common in communication and video applications. Since each output of the ring counter is to activate one word line of the

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TABLE III CHIP SUMMARY

Fig. 9. Die photo of the proposed delay buffer.

TABLE IV COMPARISON OF MEASUREMENT RESULTS WITH SRAM-BASED DELAY BUFFERS

ratio of the layout close to 1, the 256 8 delay buffer is folded into two 128 8 delay buffers. The core area of the 256 8 delay buffer is 0.232 m 0.519 m. It is packaged in a 28-pin package, including eight output pins and twelve input pins. B. Measurements The measurement results are depicted in Fig. 10, where the maximum achievable clock rate under different supply voltages and the power consumption versus different supply voltages at the maximum operating frequency are shown. The maximum operating frequency may decrease as the length of delay buffer increases due to the propagation of the global clock signal in the gated driver tree. Lower supply voltage worsens this critical path delay. The proposed chip dissipates only 2556 W at 135 MHz from a supply voltage of 1.8 V. When the supply voltage is lowered to 1.2 V, the chip consumes only 440 W at 58 MHz. Table III gives a brief summary of the low-power 256 8 delay buffer chip. Finally, Table IV lists the comparison between the proposed chip and the delay buffers using commercial single-port as well as two-port SRAM. The proposed chip has a power consumption of about 17% of the single-port SRAM-based delay buffer, or 13% of the two-port SRAM-based delay buffer. The effectiveness of the proposed techniques in lowering power consumption is quite obvious.
Fig. 10. Experimental results of (a) maximum clock rate and (b) power consumption at different supply voltage.

C. Simulations for Scalability To obtain a further insight about the scalability of the proposed delay buffer architecture in nanometer CMOS technology, we have run simulations of the proposed buffer with several different lengths in 90-nm and 65-nm CMOS technology. To alleviate the leakage power problem, dual-Vt MOS transistors are adopted in the 65-nm simulation while only

memory array, to achieve compact area and high-speed operation, the outputs of the ring counter must be pitch-matched to the memory array and the ring counter is placed as close as possible to the memory cell. As shown in Fig. 9, to make the aspect

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periority of the proposed circuit is still obvious in 90-nm technology in that the leakage power is almost negligible. Even in the more advanced 65-nm technology, the leakage power can be controlled to within an acceptable level for medium-length delay buffers with the dual-Vt approach. For longer-length delay buffers and for more advanced technology, other leakage reduction techniques such as the sleep transistors in SRAM (Latch) cells can help to reduce leakage power [9]. V. CONCLUSION In this paper, we presented a low-power delay buffer architecture which adopts several novel techniques to reduce power consumption. The ring counter with clock gated by the C-elements can effectively eliminate the excessive data transition without increasing loading on the global clock signal. The gated-driver tree technique used for the clock distribution networks can eliminate the power wasted on drivers that need not be activated. Another gated-demultiplexer tree and a gated-multiplexer tree are used for the input and output driving circuitry to decrease the loading of the input and output data bus. All gating signals are easily generated by a C-element taking inputs from some DET ip-op outputs of the ring counter. Measurement results indicate that the proposed architecture consumes only about 13% to 17% of the conventional SRAM-based delay buffers in 0.18- m CMOS technology. Further simulations also demonstrate its advantages in nanometer CMOS technology. We believe that with more experienced layout techniques the cell size of the proposed delay buffer can be further reduced, making it very useful in all kinds of multimedia/communication signal processing ICs. ACKNOWLEDGMENT The authors would like to thank the Chip Implementation Center (CIC) of the National Science Council, Taiwan, for chip fabrication. REFERENCES
[1] W. Eberle et al., 80-Mb/s QPSK and 72-Mb/s 64-QAM exible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band, IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 18291838, Nov. 2001. [2] M. L. Liou, P. H. Lin, C. J. Jan, S. C. Lin, and T. D. Chiueh, Design of an OFDM baseband receiver with space diversity, IEE Proc. Commun., vol. 153, no. 6, pp. 894900, Dec. 2006. [3] G. Pastuszak, A high-performance architecture for embedded block coding in JPEG 2000, IEEE Trans. Circuits Syst. Video Technol., vol. 15, no. 9, pp. 11821191, Sep. 2005. [4] W. Li and L. Wanhammar, A pipeline FFT processor, in Proc. Workshop Signal Process. Syst. Design Implement., 1999, pp. 654662. [5] E. K. Tsern and T. H. Meng, A low-power video-rate pyramid VQ decoder, IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 17891794, Nov. 1996. [6] N. Shibata, M. Watanabe, and Y. Tanabe, A current-sensed high-speed and low-power rst-in-rst-out memory using a wordline/bitline-swapped dual-port SRAM cell, IEEE J. Solid-State circuits, vol. 37, no. 6, pp. 735750, Jun. 2002. [7] E. Sutherland, Micropipelines, Commun. ACM, vol. 32, no. 6, pp. 720738, Jun. 1989. [8] R. Hosain, L. D. Wronshi, and A. albicki, Low power design using double edge triggered ip-op, IEEE Trans. Very Large Scale Integr. (VLSI ) Syst., vol. 2, no. 2, pp. 261265, Jun. 1994. [9] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction, IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 895901, Apr. 2005.

Fig. 11. Simulated power (with leakage power) of the proposed delay buffer architecture in (a) 90-nm CMOS technology and (b) 65-nm CMOS technology.

single-Vt MOS transistors are used in the 90-nm technology. The low Vt MOS transistors only exist in write-enable and read-enable pass gates between bit lines and memory cells to provide enough driving. The supply voltages are 1 V and 0.85 V in 90-nm and 65-nm cases, respectively, and the operating frequency is 200 MHz. Fig. 11 shows the total power consumption in normal operation mode and the leakage power consumption in idle (disabled clock) mode for 90-nm and 65-nm technology, respectively. Note that the total power consumption in normal operation mode is not logarithmically proportional to the length of the delay buffer. Instead, due to the quad tree structure for all have the driving circuitry, delay buffers of length and approximate dynamic power because basically these two cases activate the same number of drivers. We can see that the su-

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Po-Chun Hsieh was born in Kaohsiung, Taiwan, in 1977. He received the B.S. degree in electrical engineering and the M.S. degree in electronics engineering from National Taiwan University, Taipei, in 2002 and 2004, respectively. He is currently with Faraday Technology Corporation and participates on the DCDC Converter team. His research interests include low-power circuit design of communication systems and power management circuit design.

Jing-Siang Jhuang was born in Taipei, Taiwan in 1981. He received the B.S. degree in electrical engineering and the M.S. degree in electronics engineering from National Taiwan University, Taipei, in 2003 and 2005, respectively. His research interests include baseband signal processing of communication systems and related VLSI design.

Pei-Yun Tsai (S02M06) received the B.S., M.S., and Ph.D. degrees in electrical engineering from the National Taiwan University, Taipei, in 1994, 1996, and 2005, respectively. From 1996 to 2000, she was with ASUStek and participated on the optical storage systems team. She is now an Assistant Professor of electrical engineering at National Central University, Taoyuan, Taiwan. Prof. Tsai received the Acer Longtern Award, MXIC Golden Silicon Award, and the First Asian Solid-State Circuit Conference Student Design Contest Outstanding Award in 2005. Her research interests include baseband signal processing algorithms and VLSI design for digital communication systems.

Tzi-Dar Chiueh (S87M90SM03) received the B.S. and Ph.D. degrees in electrical engineering from National Taiwan University (NTU) and California Institute of Technology, Pasadena, in 1983 and 1989, respectively. He is currently a Professor of electrical engineering in the Graduate Institute of Electronics Engineering, National Taiwan University. His research interests include algorithm, architecture, and integrated circuits for baseband communication systems. Prof. Chiueh received the Acer Longtern Award 11 times and the Golden Silicon Award in 2002, 2005, and 2007. His teaching efforts were recognized ve times by the Teaching Excellence Award from NTU. He received the Outstanding Research Award from National Science Council, Taiwan, in 20042006 and was awarded the Himax Chair Professorship at NTU in 2006.

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