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Automated Implementation of Digital Circuits In Current-Mode FPGA Chips

Oleg Maslennikow, Przemyslaw Soltan
Abstracf In this paper, the automated, procedure to implementation of target digital circuits into current-mode FPGA chips liked to Xilinx FF'GAs is proposed. The paper purpose is the investigation of the possibility of designing and realization the whole programmable mixed analog-digital system

classical voltage-mode gates. Therefore, in the paper [SI, we use the approach to designing.current-mode digital circuits for synthesizing of the functional prototype of the hasic block of Xilinx FPGA cells the Spartan 11 FPGA's slice [3]. Results of VHDL-model simulations and results of experimental verification of the full-custom ASIC chip consisted of the current-mode slice, InOut block (IOB) and configuration memory block have shown the correct work of this circuit. This enables to construct the whole current-mode FPGA chip with the internal smcture and functional possibilities liked to Spartan-II FPGAs. However, because physical and logical properties of the current-mode gates as well as approaches to designing current-mode digital circuits are unknown to most designers. Therefore, in this paper, we propose the approach to automatic implementation of the target digital circuits in the currentmode FPGA chips. In this approach we assume, that currentmode FPGA chip is the functional prototype of an arbitrary

on a single die without substrate interference effect. Keywords Mixed analog-digital system, Field programmable gate array ( P G A ) , Current-mode gate, Computer-aided design, Mapping, placement and routing procedures.

I. INTRODUCTION
Modem application specific systems contain both digital and analog parts, where the first part usually is the specialized parallel processor, while the analog part is the preprocessing and interface unit between digital part and external world. Advances of the modem VLSl technology permit to implement such mixed systems on a single die. However, the problem of influence of digital part on the analog part of such a system-on-chip must be solved during system design. Switching transients (noise) of the digital part can perturb the analog part of a system owing to the coupling through the substrate [1,2]. Radical reduction of this noise is based on the implementation of the mixed system digital part with the current mode gates [4,5]. Due to the nearly constant value of the power supply current at the different gate states, the level of its noise is essentially lower in comparison with the classical voltage type gates. Moreover, based on the currentmode gates, several digital circuits were designed, which are characterized by smaller number of gates in comparison with their prototypes constructed with classical voltage CMOStype gates [ 5 ] . Note that physical and logical properties of the current-mode gates differ flom corresponding properties of Oleg Maslennikow, Przemyslaw Soltan - Electronics Depmment, Technical University ofKosralin, Partyzantow se.,17, Korzalin, 7541 1, POLAND, e-mails: olee~ie.hl.koszalin.DI, kerk@ie.tu.koszalin.pl

known FPGA chip, for example from Spartan or Virtex FPGA

families [3]. In this case, the proposed procedure consists of the following steps: design of the VHDL-model of the target circuit in the classical voltage technique and its verification using arbitrary taken VHDL simulator; synthesis ofthe verified model (mapping, placement and routing procedures) in the selected FPGA chip. n e result of this step is the . n d file and the .xdl file (when Xilinx Foundation environment is used). These files include information about used slices, IOBs, switches, etc. and their interconnections; analysis of the obtained .xdl file and its conversion to the corresponding file for selected current-mode FPGA chip based on currentmode blocks libmy. To realize it, the corresponding program-converter is used, which also

CADSM'2003, February 18-22,2003, Lviv-Slasko, Ukraine

allows generate the VHDL description of the target circuit in the current-mode technique. Ilis enables to simulate the obtained VDHL-model in the arbitrary VHDL simulator (for example, Active-HDL environment), in which current-mode table of resolution and current-mode gate libraries were included. The paper purpose is the investigation of the possibility of designing and realization the whole programmable mixed analog-digital system on a single die.

information about slices, IOBs, switches and others blocks, which have been used, and their interconnections. The fragment of the..xdl tile for the two-inputs AND function C=A and B is presented in the Fig. 2.
design ""U" xc2s1Scs144-6 "2.46
i

inst "a" "IOB"

, , ,

placed LRB K3

,
"i

cfg "PAD:a: 1NBUF:c-a: uNx::1

inst "b" "108"

inst " c " "108"

placed LR8 L1 ,
"i

cfg "PAD:b: 1NBUF:C-b: IMWX::l

placed LR8 K2
PAD:=: cMJX::O 0UTMUX::l;

11. PROCESS OF DESIGNING AND IMPLEMENTATION OF CURRENT-MODE VHDL PROJECT

In this designing process, we assume, that we have the current-mode FPGA chip, which is the functional prototype of an arbitrary Xilinx FPGA chip, for example from Spartan or Virtex families. In this case, the design of the VHDL-model of the target circuit in the standard classical voltage technique and its verification is performed in fust, using arbitrary taken VHDL simulator. Then the Xilinx Foundation environment is used for mapping, placement and routing of the target digital circuit in the selected FPGA chip. Fig. 1 illustrates the result

cfg "0mBUF:C-c:
inst "N-C"

"SLICE" , placed R8C1 CLB-R8Cl.S0,

cfg "YUSED::O G:C3:ILUT:D=(AZ*Al) - : : G " ;

net "N-a", outpin rtat'I, inpin "N-c" G Z ;

net "N-b", outpin "b" I, inpin "N-c" Gli

net "N-c", outpin "N-c" Y, inpin
'"E"

0;

Fig. 2. The fragment of the xdl tile for project of two-inputs AND function Each of used blocks from Fig. 1 is respectively configured. Information about FPGA cells is represented in the .xdl file as the text string, where keywords SLICE, IOB and PAD denote names of corresponding FPGA blocks, while keywords NET. OUTPIN and INPIN fmd the interconnections between used blocks (see Fig. 2). Keyword CFG denotes here the operation mode of the corresponding FPGA block. Fig. 3 illustrates the example of configuration and interconnections for the SLICE block, which have been used in the project of the two-inputs AND function. Next stage is analysis of the obtained .xdl file and its conversion to the corresponding file for selected current-mode FPGA chip based on current-mode blocks library. To realize it, the corresponding program-converter GEDEON was

of implementation of the two-inputs AND function C = A and

Bin the Spartan I1 FPGA

designed. For each used SLICE block this program defmes the logical function realized in the look-up-table blocks (LUTs) MATRIX OF SWITCKES and configuration data of all multiplexers. For each used IOB block program defines the configuration data of PAD and multiplexers blocks. Then program GEDEON transforms obtained data to the binary data stream, which are saved as the configuration file for the currentmode FPGA chip. In an order for this, the library of the current-mode gates is used.

Fig.1. Result of implementation ofthe two-inputs AND function in the SPARTAN II FPGA

The result of this stage is the .ncd file, which further should be transformed to the .xdl file format. The last file includes the

CADSM'2003, Fetiruary 18-22,2003. Lviv-Slasko; Ukraine

225

- A4 - A3
G 2 GI-

0x0
D

cfg "yUSED::O

G:C3:MLUT:D-(~*All

A2
AI

WS
I

DI
I

'

D=A2 and A1

=..... I1
-A2
. . . a A3

- ....

..
-

= a4 ......

.....

..... ... C 0.2 -.......

'FfO ............

a DIl

..

8AH

........

Configuration mode Fig. 3. The example of configuration and simulation for the SLICE block The proposed program also allows generate the V F L description of the target circuit in the current-mode technique. This enables to simulate'the obtained VDHL-model in the arbitrary VHDL simulator (for example, Active-HDL environment), in which current-mode table of resolution and current-mode gate libraries were included.

Work mode

REFERENCES
[I] R. Gonzalez, B.M. Gordon, M.A. Horowitz, "Supply and

Threshold Voltage Scaling for Low Power CMOS, IEEE

I. Solid-state Circuits, 1997, vol. 32, No. 8, pp. 12101215.

[2] M. Ingels, M.S.J. Steyaen, "Design strategies and de-

. 111. CONCLUSIONS
In this paper, the automated procedure to implementation of
target digital circuits into current-mode FPGA chips is

coupling techniques for reducing the effects of electrical interference in mixed-mode Ics", IEEE J. O Solid-state f Circuits, 1997, N7, pp. 1136-1 141. [3] "The Programmable Logic Data Book", X i l h , Inc., 2001.
[4] A. Guzinski, P. Pawlowski, D. Cnvyrow, J. Kaniewski, 0.

proposed. This procedure is suitable for currentmode FPGA chips, which are the functional prototypes of known FPGA chips of Spanan or Virtex families. Proposed procedure is based on the GEDEON prografn, which inalyses the input file ,. with information ahout slices, IOBs, switches, and others FPGA blocks, which have been used in the project, and theG interconnections. Then program transforms obtained data to the binary data stream, which are-saved as the configuration tile for the current-mode FPGA chip. In an order for this, the library of the currentmode gates is used. The paper purpose is the investigation of the possibility of designing and realization the whole programmable mixed analog-digital system on a single die without substrate interference effect.

Maslennikow, N. Maslennikowa, D. Rataj, "Design of Digital Circuits with Current-Mode Gates," Bulletin of the Polish Academy of Sciences, Technical Sciences, vol. 48,
. . .

no. I, pp.73-91,2000.

[SI 0. MaSkMikOW, "Approaches to Designing and Examples of Digital Circuits Based on the Current-Mode Gates,"
Data Recording, Storage & Processing, vol. 3, no. 2, pp.84-98,2001,
-

The work is supported by the grant KBN 7TI I B 004 20.

CADSM'2003, February 18-22,2003, Lviv-Slasko, Ukraine