Cap 6 - Amplificadores de Estágio Único em CI

ELT 085 Circuitos Eletrnicos Analgicos
Amplificadores de Estgio nico em Circuitos Integrados
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Sumrio
1. Comparao do MOSFET e BJT 2. Espelhos de Corrente 3. Resposta em Altas Frequncias 4. Amplificadores FC e EC com Carga Ativa 5. Amplificadores GC e BC com Carga Ativa 6. Amplificador Cascode
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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Sumrio
7. Amplificadores FC (EC) com resistor fonte (emissor) 8. Seguidor de Fonte e Seguidor de Emissor 9. Associaes de Transistores 10. Espelhos de Corrente Aprimorados
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Microelectronic Circuits - Fifth Edition Sedra/Smith
Copyright 2004 by Oxford University Press, Inc.
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Sumrio
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Restries:
Amplificadores com Acoplamento capacitivo
Resistores de valores elevados Grandes capacitores
Possibilidades: Fontes de corrente constante Pequenos capacitores Transistores casados

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Equaes bsicas do transistor MOS

vDS 1 W 2 ) iD = nCox (vGS Vt ) (1 + VA 2 L
Cox =
ox
tox
' VA = VA L
ox = permissividade do xido de silcio

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Parmetro tox(nm) Cox(fF/m2) (cm2/Vs) Cox(A/V2) Vto(V) VDD(V) VA(V/m) Cov(fF/m)
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Valres tpicos de Parmetros de CMOS

0,8m N 15 2,3 550 127 0,7 5 25 0,2 P 15 2,3 250 58 -0,7 5 20 0,2 N 9 3,8 500 190 0,7 3,3 20 0,4 0,5m P 9 3,8 180 68 -0,8 3,3 10 0,4 0.25m N 6 5,8 460 267 0,43 2,5 5 0,3 P 6 5,8 160 93 -0,62 2,5 6 0,3 N 4 8,6 450 387 0,48 1,8 5 0,37 0.18m P 4 8,6 100 86 -0,45 1,8 6 0,33 7
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Equaes Bsicas do BJT

iC = I S e
v BE VT
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Equaes Bsicas do BJT

n p (0) = n p 0 e
v BE VT
iC = I S e
v BE VT
AE qDn ni2 IS = WN A
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Parmetro AE (m2) IS (A) o (A/A) VA (V) VCEO (V) F (ns) Cje0 (pF) C0 (pF) rx ()
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Valres tpicos de Parmetros de BJTs

Processo Padro npn 500 5 x 10-15 200 130 50 0,35 1 0,3 200 pnp lateral 900 2 x 10-15 50 50 60 30 0,3 1 300 Advanced Low Voltage npn 2 6 x 10-18 100 35 8 10 x 10-3 5 x 10-3 5 x 10-3 400 pnp lateral 2 6 x 10-18 50 30 18 650 x 10-3 14 x 10-3 15 x 10-3 200 10
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Condies para operar na regio ativa
1 - Criar o canal:
1 Polarizar diretamente B-E:
vGS vt ,
Vt = 0,5 a 0 ,7V
vBE VBEon ,
VBEon 0,5V
vGS = Vt + vOV
2 Estrangular o canal no dreno:
2 Polarizar reversamente B-C:
vGD < Vt vDS VOV

Table 6.3
ou:
vBC < VBCon ,
VBCon 0,4V
VOV = 0.2 0.3 V
vCE 0,3V
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Caracterstica i x v na regio ativa

iC = I S e
vBE VT
vDS 1 W 2 ) iD = nCox (vGS Vt ) (1 + 2 L VA vDS 1 W 2 ) iD = nCox vOV (1 + 2 L VA iG = 0
vCE (1 + ) VA
iB =
iC
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Modelos em Baixas frequncias
Table 6.3
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Transcondutncia
ID
OV
gm = V
W g m = ( nCox )( )VOV L
IC gm = VT
W g m = 2( nCox ) I D L
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Resistncias de entrada e sada
Resistncia de sada:
' VA VA L = ro = ID ID
ro =
VA IC
Resistncia de entrada:
r =
gm
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Ganho intrnseco
A0 = V VA
OV
' 2VA L A0 = VOV
VA A0 = VT
A0 =
VA' 2 nCoxWL ID
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Modelos em Altas frequncias
Table 6.3
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Sumrio
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Espelho de corrente
1 ' W I D1 = k n ( )1 (vGS Vt ) 2 2 L I D1 = I REF VDD VGS = R
I D2 =
1 ' W k n ( ) 2 (vGS Vt ) 2 2 L
IO (W L ) 2 = (W L )1
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Figure 6.4 Circuit for a basic MOSFET constant-current source.
I REF
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Limite de operao
Vo VGS Vt
Figure 6.5 Basic MOSFET current mirror.
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Efeito da resistncia de sada
Vo VGS (W L ) 2 Io = I REF 1 + W ) VA2 ( L1
Figure 6.6 Output characteristic of the current source in Fig. 6.4 and the current mirror of Fig. 6.5 for the case Q2 is matched to Q1.
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Diviso de corrente
Figure 6.7 A current-steering circuit.
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Espelho de corrente a BJT
Io I REF
I S 2 rea da JBE de Q 2 = = I S 1 rea da JBE de Q1
Figure 6.8 The basic BJT current mirror.
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Dependncia de
Io I REF
1 1+ 2
Se I S 2 = mI S 1 ,
Figure 6.9 Analysis of the current mirror taking into account the finite of the BJTs.
Io I REF
= 1+
m m +1
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Projeto do Espelho de corrente
I REF =
VCC VBE R
Io =
V VBE I REF (1 + o ) 2 VA 1+
Figure 6.10 A simple BJT current source.
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Diviso de Corrente
Figure 6.11 Generation of a number of constant currents of various magnitudes.
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Sumrio
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Restries:
Amplificadores com Acoplamento capacitivo
Resistores de valores elevados Grandes capacitores
Possibilidades: Fontes de corrente constante Pequenos capacitores Transistores casados

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Amplificadores com acoplamento direto
Figure 6.12 Frequency response of a direct-coupled (dc) amplifier. Observe that the gain does not fall off at low frequencies, and the midband gain AM extends down to zero frequency.
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Funo de Transferncia
A( s) = AM FH ( s ) (1 + (1 +
s s
FH ( s ) =
wZ 1 wP 1
)(1 + )(1 +
s s
wZ 2 wP 2
)...(1 + )...(1 +
s s
wZn wPn
) )
Plo dominante: Um polo dominante existe se o plo de mais baixa frequncia est a pelo menos duas oitavas do plo ou zero mais prximo.
FH ( s )
1 1+
s w p1
wH wP1
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Clculo Aproximado de fH
wH 1 1 1 1 1 2 + 2 + ... 2 2 + 2 + ... w w wP 2 wZ 2 Z1 P1
Exemplo 6.5
A resposta em altas frequncias de um amplificador caracterizada por:
(1 + s105 ) FH ( s ) = (1 + s104 )(1 + s 4 x104 )

Determine a freqncia de -3dB
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Exemplo 6.5
Figure 6.13 Normalized high-frequency response of the amplifier in Example 6.5.
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Mtodo das constantes de tempo

1 + a1s + a2 s 2 + ... + an s n FH ( s ) = 1 + b1s + b2 s 2 + ... + bn s n
b1 = 1 1 1 + + ... + w p1 w p 2 w pn
n
b1 = Ci Rio (exato)
i =1
Rio = resistncia vista dos terminais de Ci com todos os outros capacitores iguais a zero e fontes de sinal anuladas.
1 b1 w p1
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1 wH = b1
1 Ci Rio
i
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Exemplo 6.6
Exemplo
Determine AM e fH para o amplificador, onde Rsig = 100 k, Rin = 420 k, Cgs = Cgd= 1pF, gm = 4mA/V e RL = 3,33k.
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Exemplo 6.6
Figure 6.14 Circuits for Example 6.6: (a) high-frequency equivalent circuit of a MOSFET amplifier; (b) the equivalent circuit at midband frequencies; (c) circuit for determining the resistance seen by Cgs; and (d) circuit for determining the resistance seen by Cgd.
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Teorema de Miller
Figure 6.15 The Miller equivalent circuit.
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Exemplo 6.7
Exemplo
Determine o circuito equivalente de Miller para Z = R = 1M e Z = C = 1pF. Em cada caso, determine Vo/Vsig.
Figure 6.16 Circuit for Example 6.7.
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Exemplo 6.7
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Sumrio
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Tabela 4.3
Definies:
Resistncia de entrada sem carga: Resistncia de entrada: Ganho de tenso em malha aberta:
vi Ri ii vi Rin ii
RL =
vo Avo vi
RL =
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Tabela 4.3
Definies:
Ganho de tenso:
vo Av vi io Ais ii Ai io ii
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Ganho de corrente em curto circuito: Ganho de corrente:
RL = 0
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Tabela 4.3
Definies:
Transcondutncia em curto circuito: Ganho de tenso total: Ganho de tenso total em circuito aberto:
io Gm vi vo Gv vsig
RL = 0
vo Gvo vsig
RL =
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Tabela 4.3 Definies:

Resistncia de sada prpria:
Ro
vx ix
vi = 0
Resistncia de sada:
Rout
vx ix
v sig = 0
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Tabela 4.3 Circuitos Equivalentes
vi Rin = vsig Rin + Rsig
RL Av = Avo RL + Ro
Rin RL Avo Gv = Rin + Rsig RL + Ro

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Avo = Gm Ro
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Ri Avo Gvo = Ri + Rsig
Gv = Gvo
RL RL + Rout
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Amplificador FC com Carga Ativa
Ri =
Avo = g m ro
Ro = ro
Figure 6.17 (a) Active-loaded common-source amplifier. (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit diagram and using the small-signal model explicitly.
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Carga ativa CMOS
Av = g m1 (ro1 // ro 2 )
Figure 6.18 The CMOS common-source amplifier; (a) circuit; (b) iv characteristic of the active-load Q2; (c) graphical construction to determine the transfer characteristic; and (d) transfer characteristic.
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Carga ativa CMOS
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Carga ativa CMOS
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Amplificador EC com Carga Ativa
Ri = r
Avo = g m ro
Ro = ro
Figure 6.19 (a) Active-loaded common-emitter amplifier. (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit and using the hybrid- model explicitly.
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Resposta em frequncia do FC e EC com carga ativa
Vsig e Rsig representam o equivalente de Thevenin da fonte de sinal e resistncias do circuito de entrada. RL representa a carga e o resistor da fonte de corrente constante de sada. CL representa as capacitncias de carga na sada.
Figure 6.20 High-frequency equivalent-circuit model of the common-source amplifier. For the common-emitter amplifier, the values of Vsig and Rsig are modified to include the effects of r and rx; Cgs is replaced by C, Vgs by V, and Cgd by C.
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Anlise pelo Teorema de Miller
Vo AM Vsig 1 + s wH
AM = g m R
' L
fH =
1 ' 2 [C gs + C gd (1 + g m RL )]Rsig
Figure 6.21 Approximate equivalent circuit obtained by applying Millers theorem while neglecting CL and the load current component supplied by Cgd. This model works reasonably well when Rsig is large and the amplifier high-frequency response is dominated by the pole formed by Rsig and Cin.
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Mtodo das Constantes de tempo
fH
1 2 H
' ' ' H = C gs Rsig + C gd [ Rsig (1 + g m RL ) + RL ] + C L RL

Figure 6.22 Application of the open-circuit time-constants method to the CS equivalent circuit of Fig. 6.20.
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Anlise exata
' g m RL [1 s (C gd / g m )] Vo = ' ' ' Vsig 1 + s{[C gs + C gd (1 + g m RL )]Rsig + (C L + C gd ) RL } + s 2 [(C L + C gd )C gs + C L C gd ]Rsig RL
Figure 6.23 Analysis of the CS high-frequency equivalent circuit.
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Anlise exata
1 1 s s s2 )(1 + ) = 1 + s( )+ D( s ) = (1 + + w p1 wp 2 w p1 w p 2 w p1w p 2
se w p 2 >> w p1
s s2 D( s) 1 + + w p1 w p1w p 2 1 w p1 = ' ' [C gs + C gd (1 + g m RL )]Rsig + (C L + C gd ) RL
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Anlise para o emissor comum
Figure 6.25 (a) High-frequency equivalent circuit of the common-emitter amplifier. (b) Equivalent circuit obtained after the Thvenin theorem is employed to simplify the resistive circuit at the input.
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Caso com Rsig = 0
Vo = Vsig
' g m RL [1 s (C gd / g m )] ' 1 + s (C L + C gd ) RL
fH =
1 ' 2 (C L + C gd ) RL
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Figure 6.26 (a) High-frequency equivalent circuit of a CS amplifier fed with a signal source having a very low (effectively zero) resistance. (b) The circuit with Vsig reduced to zero. (c) Bode plot for the gain of the circuit in (a).
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Caso com Rsig = 0

1 f t =| AM | f H = g m R ' 2 (C L + C gd ) RL
' L
Figure 6.26 (a) High-frequency equivalent circuit of a CS amplifier fed with a signal source having a very low (effectively zero) resistance. (b) The circuit with Vsig reduced to zero. (c) Bode plot for the gain of the circuit in (a).
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Sumrio
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Gate comum com Carga Ativa
Efeito body (substrato)
g mb = g m
= 0,1 a 0,2
Figure 6.27 (a) Active-loaded common-gate amplifier. (b) MOSFET equivalent circuit for the CG case in which the body and gate terminals are connected to ground. (c) Small-signal analysis performed directly on the circuit diagram with the T model of (b) used implicitly. (d) Operation with the output open-circuited.
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Gate comum com Carga Ativa Resistncia de entrada
ii = ( g m + g mb )vi + iro
iro =
vi vo vi ii RL = ro ro
vi ro + RL Rin = = ii 1 + ( g m + g mb )ro
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Gate comum com Carga Ativa - RL=

Se RL = Ri =
vo = iro + vi = ( g m + g mb )ro vi + vi
Av 0 = vo = 1 + ( g m + g mb )ro vi
ro + RL 1 RL + Rin = Avo g m + g mb A0
vo Gv 0 = = Avo = 1 + ( g m + g mb )ro vsig
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Gate comum com Carga Ativa Ganho de Tenso
vi = ii Rin vo = io RL = ii RL vo RL RL Av = = = Avo vi Rin RL + ro
vo = io RL = ii RL
vsig = ii ( RS + Rin ) Gv = vo RL RL = = Avo vsig RS + Rin RL + ro + Avo RS
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Gate comum com Carga Ativa Resistncia de sada
v = ix RS v x = [ix + ( g m + g mb )v]ro + v
Rout = ro + [1 + ( g m + g mb )ro ]RS = ro + Avo RS

Figure 6.28 (a) The output resistance Ro is found by setting vi 5 0. (b) The output resistance Rout is obtained by setting vsig 5 0.
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Buffer de corrente
Rout = ro + [1 + ( g m + g mb )ro ]RS = RS + [1 + ( g m + g mb ) RS ]ro Rout [1 + ( g m + g mb ) RS ]ro (1 + g m RS )ro
Figure 6.29 The impedance transformation property of the CG configuration.
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Resposta em frequencia do GC
f p1 = 1 1 2 C gs ( RS || ) g m + g mb
1 2 (C gd + C L )R L
f p2 =
Figure 6.31 (a) The common-gate amplifier with the transistor internal capacitances shown. A load capacitance CL is also included. (b) Equivalent circuit for the case in which ro is neglected.
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Resposta em frequencia do GC
Rgs = RS || Rin
Rgd = RL || Rout
1 fH = 2 [Cgs Rgs + (C gd + C L )R gd ]
Figure 6.32 Circuits for determining Rgs and Rgd.
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Amplificador Base Comum
Rin =
ro + RL ro RL 1+ + re ( + 1)re
Figure 6.33 (a) Active-loaded common-base amplifier. (b) Small-signal analysis performed directly on the circuit diagram with the BJT T model used implicitly. (c) Small-signal analysis with the output open-circuited.
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vo Avo = vi

= 1 + g m ro = 1 + A0
RL
Ri = r
vo Gvo = vsig
RL
Ri Avo = Ri + Re
Figure 6.33 (a) Active-loaded common-base amplifier. (b) Small-signal analysis performed directly on the circuit diagram with the BJT T model used implicitly. (c) Small-signal analysis with the output open-circuited.
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Ro = ro Rout = ro + (1 + g m ro ) Re' = Re' + (1 + g m Re' )ro Re' = Re || r
onde :
Figure 6.34 Analysis of the CB circuit to determine Rout. Observe that the current ix that enters the transistor must equal the sum of the two currents v/r and v/Re that leave the transistor, that is; ix 5 v/r 1 v/Re.
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Buffer de Corrente
Figure 6.35 Input and output resistances of the CB amplifier.
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Sumrio
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Amplificador Cascode
Rout = ro 2 + Avo 2 ro1 A0 ro1
Rin 2
RL 1 = + g m 2 + g mb 2 Avo 2
Avo 2 = 1 + ( g m 2 + g mb 2 )ro 2
Figure 6.36 (a) The MOS cascode amplifier. (b) The circuit prepared for small-signal analysis with various input and output resistances indicated. (c) The cascode with the output open-circuited.
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Avo 2 = 1 + ( g m 2 + g mb 2 )ro 2
vo = Avo 2 vo1 = Avo 2 ( g m1ro1 )vi
vo Avo = vi
( g m ro ) 2
RL
Figure 6.36 (a) The MOS cascode amplifier. (b) The circuit prepared for small-signal analysis with various input and output resistances indicated. (c) The cascode with the output open-circuited.
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RL Av = A RL + A0 ro
2 0
vo1 1 RL = g m [ro || ( + )] vi g m A0
Figure 6.37 (a and b) Two equivalent circuits for the output of the cascode amplifier. Either circuit can be used to determine the gain Av 5 vo/vi, which is equal to Gv because Rin 5 and thus vi 5 vsig. (c) Equivalent circuit for determining the voltage gain of the CS stage, Q1.
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com RL = A0 ro
1 Av = A 2
2 0
Av = A02
RL RL + A0 ro
vo1 g m ro 1 = = A0 vi 2 2
vo1 1 RL = g m [ro || ( + )] vi g m A0
com RL = ro
Av = A0
vo1 = 2 vi
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Resposta em Frequencia do Cascode MOS
= C gs1 Rsig + C gd 1[(1 + g m1 Rd 1 ) Rsig + Rd 1 ] = + (Cdb1 + C gs 2 ) Rd 1 + (C L + C gd 2 )( RL || Rout )

Figure 6.38 The cascode circuit with the various transistor capacitances indicated.
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Rsig = 0 e RL=A0ro
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Amplificador Cascode a BJT
Rout = (1 + g m Re' )ro

Re' = Re || r
(6.118)
Rout = (1 + g m 2 r 2 )ro 2 2 ro 2
Figure 6.40 (a) The BJT cascode amplifier. (b) The circuit prepared for small-signal analysis with various input and output resistances indicated. Note that rx is neglected. (c) The cascode with the output open-circuited.
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Amplificador Cascode a BJT
vo1 = g m1vi (ro1 || r 2 ) vi Avo 2 = 1 + g m 2 ro 2 A02 Avo = A02
Figure 6.40 (a) The BJT cascode amplifier. (b) The circuit prepared for small-signal analysis with various input and output resistances indicated. Note that rx is neglected. (c) The cascode with the output open-circuited.
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Amplificador Cascode a BJT Modelos Equivalentes
RL << ro RL = ro
vo1 = 1 vi
vo1 = vi 2
Figure 6.41 (a) Equivalent circuit for the cascode amplifier in terms of the open-circuit voltage gain Avo 5 A0. (b) Equivalent circuit in terms of the overall short-circuit transconductance Gm . gm. (c) Equivalent circuit for determining the gain of the CE stage, Q1.
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Amplificador Cascode a BJT Resposta em frequncia
Figure 6.42 Determining the frequency response of the BJT cascode amplifier. Note that in addition to the BJT capacitances C and C, the capacitance between the collector and the substrate Ccs for each transistor are also included.
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Fonte de Corrente Cascode
Transistor do espelho de corrente
Transistor em gate comum
RL = ( g m 2 ro 2 )ro1
Figure 6.43 A cascode current-source.
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Duplo cascode
Rout 3 = ( g m 2 ro 2 )( g m 3ro 3 )ro1 = A02 ro
Figure 6.44 Double cascoding.
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Cascode dobrado
I1 I 2
Figure 6.45 The folded cascode.
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Cascode BiCMOS
Rin infinita
Maior resistncia de sada (BJT>A0_FET e ro_BJT > ro_FET) Efeito Miller reduzido (Rin2_BJT<Rin2_FET)
Figure 6.46 BiCMOS cascodes.
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Cascode BiCMOS
Maior resistncia de sada com MOSFET Q3 pois com BJT ficaria limitada a ro
Figure 6.46 BiCMOS cascodes.
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Sumrio
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Fonte comum com resistor de fonte
v x Rs ix ix = g m Rs ix ro
Rout
= ro + RS + ( g m + g mb )ro RS ro [1 + ( g m + g mb ) RS ]
Rout aumenta com o aumento de RS

Figure 6.47 (a) A CS amplifier with a source-degeneration resistance Rs. (b) Circuit for small-signal analysis. (c) Circuit with the output open to determine Avo. (d) Output equivalent circuit. (e) Another output equivalent circuit in terms of Gm.
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vo = g m vi ro Avo = g m ro = A0
RS no afeta o ganho Avo
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RL Av = Avo RL + Rout
O ganho Av cai com o aumento de RS
gm | Avo | Gm = = Rout 1 + ( g m + g mb ) RS
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FC com resistor de fonte Resposta em frequncia
Figure 6.48 (a) The CS amplifier circuit, with a source resistance Rs, prepared for frequency-response analysis. (b) Determining the resistance Rgd seen by the capacitance Cgd.
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Figure 6.48 (a) The CS amplifier circuit, with a source resistance Rs, prepared for frequency-response analysis. (b) Determining the resistance Rgd seen by the capacitance Cgd.
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Melhora a linearidade do amplificador realimentao negativa - vgs apenas uma parcela de vi Aumenta a faixa de passagem do amplificador
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Emissor Comum com resistor de emissor
Figure 6.49 A CE amplifier with emitter degeneration: (a) circuit; (b) analysis to determine Rin; and (c) analysis to determine Avo.
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Emissor Comum com resistor de emissor
Figure 6.49 A CE amplifier with emitter degeneration: (a) circuit; (b) analysis to determine Rin; and (c) analysis to determine Avo.
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Sumrio
7. Amplificadores FC (EC) com resistor fonte (emissor) 7. Amplificadores FC (EC) com resistor fonte (emissor) 8. Seguidor de Fonte e Seguidor de Emissor 9. Associaes de Transistores 9. Associaes de Transistores 10. Espelhos de Corrente Aprimorados
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Seguidor de Fonte
vo = g m v gs R 'L v gs = vi vo
' vo g m RL Av = = ' vi 1 + g m RL
g m ro gm 1 = Avo = 1 + ( g m + g mb )ro g m + g mb 1 +
Figure 6.50 (a) An IC source follower. (b) Small-signal equivalent-circuit model of the source follower. (c) A simplified version of the equivalent circuit. (d) Determining the output resistance of the source follower.
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Seguidor de Fonte
Ro =
1 || ro g m + g mb
Figure 6.50 (a) An IC source follower. (b) Small-signal equivalent-circuit model of the source follower. (c) A simplified version of the equivalent circuit. (d) Determining the output resistance of the source follower.
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Seguidor de Fonte Resposta em frequncia
Rgd = Rsig
Rgd = RL || Ro
Figure 6.51 Analysis of the high-frequency response of the source follower: (a) Equivalent circuit; (b) simplified equivalent circuit; and (c) determining the resistance Rgs seen by Cgs.
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Seguidor de Fonte Resposta em frequncia
Rgs =
' Rsig + RL ' 1 + g m RL
Figure 6.51 Analysis of the high-frequency response of the source follower: (a) Equivalent circuit; (b) simplified equivalent circuit; and (c) determining the resistance Rgs seen by Cgs.
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Seguidor de emissor - Resposta em frequncia
Figure 6.52 (a) Emitter follower. (b) High-frequency equivalent circuit. (c) Simplified equivalent circuit.
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Seguidor de emissor - Resposta em frequncia
' ' R = Rsig || [r + ( + 1) RL ]
R =
' ' Rsig + RL ' RL 1+ + r re ' Rsig
Figure 6.52 (a) Emitter follower. (b) High-frequency equivalent circuit. (c) Simplified equivalent circuit.
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Sumrio
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DC-FC, CC-EC e DC-EC
Larga faixa de passagem Alta resistncia de entrada

Figure 6.53 (a) CDCS amplifier. (b) CCCE amplifier. (c) CDCE amplifier.
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Figure 6.54 Circuits for Example 6.13: (a) The CCCE circuit prepared for low-frequency small-signal analysis; (b) the circuit at high frequencies, with Vsig set to zero to enable determination of the open-circuit time constants; and (c) a CE amplifier for comparison.
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Configurao Darlington
Figure 6.55 (a) The Darlington configuration; (b) voltage follower using the Darlington configuration; and (c) the Darlington follower with a bias current I applied to Q1 to ensure that its remains high.
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CC-BC e DC-GC
Figure 6.56 (a) A CCCB amplifier. (b) Another version of the CCCB circuit with Q2 implemented using a pnp transistor. (c) The MOSFET version of the circuit in (a).
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CC-BC e DC-GC - Resposta em frequncia
Figure 6.57 (a) Equivalent circuit for the amplifier in Fig. 6.56(a). (b) Simplified equivalent circuit. Note that the equivalent circuits in (a) and (b) also apply to the circuit shown in Fig. 6.56(b). In addition, they can be easily adapted for the MOSFET circuit in Fig. 6.56(c), with 2r eliminated, C replaced with Cgs, C replaced with Cgd, and V replaced with Vgs.
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Sumrio
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Espelho Cascode MOS
Ro = ro 3 + [1 + ( g m 3 + g mb 3 )ro 3 ]ro 2
Figure 6.58 A cascode MOS current mirror.
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Espelho com compensao da corrente de base
Io I REF
1 1 + 2 /( 2 + )
1 1+ 2 / 2
Figure 6.59 A current mirror with base-current compensation.
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Fonte de Wilson
Io I REF
1 1+ 2 / 2
Figure 6.60 The Wilson bipolar current mirror: (a) circuit showing analysis to determine the current transfer ratio; and (b) determining the output resistance. Note that the current ix that enters Q3 must equal the sum of the currents that leave it, 2i.
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Fonte de Wilson
Ro =
ro
2
Figure 6.60 The Wilson bipolar current mirror: (a) circuit showing analysis to determine the current transfer ratio; and (b) determining the output resistance. Note that the current ix that enters Q3 must equal the sum of the currents that leave it, 2i.
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Fonte de Wilson MOS
Ro ro 3 ( g m 3 ro 2 + 2) g m 3 ro 3 ro 2
Figure 6.61 The Wilson MOS mirror: (a) circuit; (b) analysis to determine output resistance; and (c) modified circuit.
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Fonte de Wilson MOS
Figure 6.61 The Wilson MOS mirror: (a) circuit; (b) analysis to determine output resistance; and (c) modified circuit.
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Fonte de Corrente Widlar

I REF = I S e IO = I S e
v BE 1 vT
v BE 2 vT v BE 1 v BE 2 vT
I REF = ISe Io
VBE1 = VBE 2 + I o RE I REF I o RE = VT ln I o

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Figure 6.62 The Widlar current source.
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Exemplo 6.14
Projetar as fontes de corrente para Io = 10 A. Fazer Iref = 1mA na Fonte Widlar.
Figure 6.63 Circuits for Example 6.14.
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Figure 6.64 Capture schematic of the CS amplifier in Example 6.15.
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Figure 6.65 Transistor equivalency.
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Figure 6.66 (a) Voltage transfer characteristic of the CS amplifier in Example 6.15.
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Figure 6.66 (Continued) (b) Expanded view of the transfer characteristic in the high-gain region. Also shown are the transfer characteristics where process variations cause the width of transistor M1 to change by +15% and 15% from its nominal value of W1 = 12.5 m.
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Figure 6.67 Capture schematic of the CS amplifier in Example 6.16.
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Figure 6.68 Frequency response of (a) the CS amplifier and (b) the folded-cascode amplifier in Example 6.16, with Rsig = 100 and Rsig = 1 .
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Figure 6.69 Capture schematic of the folded-cascode amplifier in Example 6.16.
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6.9 Determine a resistncia incremental de cada diodo da figura abaixo. Assuma I = 0,1 mA. Para o Mosfet nCox = 200 A/V2 e W/L = 10.
Figure P6.9
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6.25 Determine Io em funo de IREF e (W/L) dos dispositivos.
Figure P6.25
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Figure P6.26
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Figure P6.28
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Figure P6.33
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Figure P6.34
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Figure P6.35
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Figure P6.37
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Figure P6.46
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Figure P6.54
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Figure P6.57
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Figure P6.61
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Figure P6.63
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Figure P6.65
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Figure P6.72
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Figure P6.73
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Figure P6.75
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Figure P6.76
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Figure P6.83
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Figure P6.84
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Figure P6.85
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Figure P6.93
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Figure P6.96
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Figure P6.98
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Figure P6.99
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Figure P6.107
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Figure P6.121
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Figure P6.122
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Figure P6.123
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Figure P6.124
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Figure P6.127
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Figure P6.130
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Figure P6.134
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Figure P6.143
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Figure P6.144
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Figure P6.145
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ELT 085 Circuitos Eletrnicos Analgicos

Amplificadores de Estgio nico em Circuitos Integrados

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Amplificadores com Acoplamento capacitivo

Resistores de valores elevados Grandes capacitores

Possibilidades: Fontes de corrente constante Pequenos capacitores Transistores casados

Equaes bsicas do transistor MOS

ox = permissividade do xido de silcio

Copyright 2004 by Oxford University Press, Inc.

Valres tpicos de Parmetros de CMOS

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Equaes Bsicas do BJT

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Equaes Bsicas do BJT

Valres tpicos de Parmetros de BJTs

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Condies para operar na regio ativa

1 Polarizar diretamente B-E:

2 Polarizar reversamente B-C:

vGD < Vt vDS VOV

vBC < VBCon ,

VOV = 0.2 0.3 V

Microelectronic Circuits - Fifth Edition Sedra/Smith

Caracterstica i x v na regio ativa

vDS 1 W 2 ) iD = nCox (vGS Vt ) (1 + 2 L VA vDS 1 W 2 ) iD = nCox vOV (1 + 2 L VA iG = 0

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Modelos em Baixas frequncias

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Resistncias de entrada e sada

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

' 2VA L A0 = VOV

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Modelos em Altas frequncias

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Figure 6.4 Circuit for a basic MOSFET constant-current source.

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Figure 6.5 Basic MOSFET current mirror.

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Efeito da resistncia de sada

Vo VGS (W L ) 2 Io = I REF 1 + W ) VA2 ( L1

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Figure 6.7 A current-steering circuit.

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.

Espelho de corrente a BJT

I S 2 rea da JBE de Q 2 = = I S 1 rea da JBE de Q1

Figure 6.8 The basic BJT current mirror.

Microelectronic Circuits - Fifth Edition Sedra/Smith

Copyright 2004 by Oxford University Press, Inc.