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W. Rhett Davis
NC State University
Slide 2
ECE 546
Fall 2011
Is this a positive or a negative latch? Does is work b l k by loop-breaking b ki or loop-forcing? How should you size the transistors?
CLK D CLK Q
How do you calculate the minimum clock-period for a design? What are the types of timing constraints? Which one is the most critical to satisfy? Using the skew definition from the last lecture, if the clock edge at the source register arrives BEFORE the clock edge at the destination register, is the skew positive or negative?
NC State University Slide 3 ECE 546 Fall 2011
W. Rhett Davis
Todays Lecture
W. Rhett Davis
NC State University
Slide 4
ECE 546
Fall 2011
Q CLK D
CLK
CLK
W. Rhett Davis
NC State University
Slide 5
ECE 546
Fall 2011
Dynamic Flip-Flop
What are the dynamic nodes? Rising-Edge or Falling Edge Triggered? Estimate tsu, thold, and tc-q based on the delays of the transmission gates and inverters.
NC State University Slide 6 ECE 546 Fall 2011
W. Rhett Davis
Clock-Overlap
Problem: Both latches are transparent Assume tsu and thold are relative to CLK What timing constraints are needed to ensure proper operation?
Falling-edge (ensure input doesnt propagate to slave) Rising-edge (ensure input doesnt propagate to master)
W. Rhett Davis
NC State University
Slide 7
ECE 546
Fall 2011
Clock-Overlap
Consider CLK later than CLK: Both latches are still transparent Assume tsu and thold are relative to CLK What timing constraints are needed to ensure proper operation?
Falling-edge (ensure input doesnt propagate to slave) Rising-edge (ensure input doesnt propagate to master)
W. Rhett Davis
NC State University
Slide 8
ECE 546
Fall 2011
CLK D CLK
M4 X M3 CL1
CLK
M8 Q CL2
CLK
M7
M1
M5
Master Stage
W. Rhett Davis NC State University
Slave Stage
Slide 9 ECE 546 Fall 2011
Insensitive to Clock-Overlap
VDD M2 0 D M4 X 0 VDD M6 M8 Q D 1 M1 (a) (0-0) overlap
VDD M2
VDD M6
Q 1 M7 M5
M5
W. Rhett Davis
Slide 10
Disadvantage to
VDD M2
2MOS C
VDD M6
CLK D CLK
M4 X M3 CL1
CLK
M8 Q CL2
CLK
M7
M1
M5
Master Stage
Slave Stage
Short-Circuit currents destroy charge stored at X and Q For correct operation, ensure that triseCLK < 5 tc q c-q
NC State University Slide 11 ECE 546 Fall 2011
W. Rhett Davis
Positive latch Negative latch (transparent (t a spa e t when C e CLK= 1) (transparent when C ) (t a spa e t e CLK= 0)
W. Rhett Davis NC State University Slide 12 ECE 546 Fall 2011
TSPC Register
Y X
_ Q
Negative-Edge T i N ti Ed Triggered d
W. Rhett Davis
TSPC Negative-Edge FF
V
time
W. Rhett Davis
TSPC Negative-Edge FF
V
time
W. Rhett Davis
Todays Lecture
W. Rhett Davis
NC State University
Slide 16
ECE 546
Fall 2011
Pipelining
RE EG
RE EG
REG
REG
REG
REG
CLK
CLK
RE EG
log
Out
b
CLK
log
Out
RE EG
CLK
CLK
CLK
CLK
CLK
Reference R f
Pipelined
W. Rhett Davis
NC State University
Slide 17
ECE 546
Fall 2011
Advantages of Pipelining
Latency increases, but so does Throughput (avg operations per second) (avg. Example: tc-q, tsu =1 / tadd, tabs= 2 / tlog = 3
B f Before Pipelining Pi li i
Tmin = tc-q + tadd + tabs + tlog + tsu = 9 Delay for 1 operation = Tmin = 9 i Delay for 5 operations = 5*Tmin = 45
After Pipelining
Tmin = tc-q + max(tadd, tabs, tlog) + tsu = 5 Delay for 1 operation = 3*Tmin = 15 D l f 5 operations = 7*Tmin = 35 Delay for ti
W. Rhett Davis NC State University Slide 18 ECE 546 Fall 2011
Advantages of Pipelining
Can be Lower-Energy due to Operand Isolation Can d C reduce glitching i complex l i networks lit hi in l logic t k
Before:
After:
W. Rhett Davis
NC State University
Slide 19
REG
ECE 546
Fall 2011
Latch-Based Pipeline
CLK CLK CLK In C1 F C2 G C3 Out
CLK CLK
Compute F
compute G
The lower tc-q and energy of latches makes th Th l d fl t h k them a good d choice for high-performance pipelines Recall that pipeline should alternate p pp pos. and neg. latches g Problem: Sensitive to clock overlap (race btw. In1 and In2)
NC State University Slide 20 ECE 546 Fall 2011
W. Rhett Davis
Solution: NORA-CMOS
Use C2MOS latches A C2MOS based pipeline is race free as long as all of the MOS-based logic functions between the latches are non-inverting Example: 0-0 Overlap p p
Inverting Logic: Falling-edge Falling edge at 1st latch can cause transition at 2nd latch
W. Rhett Davis NC State University
Non-Inverting Logic: Falling-edge Falling edge at 1st latch cannot affect at 2nd latch
Slide 21 ECE 546 Fall 2011
Non-Inverting Logic
Non-Inverting Logic is logic for which a positive edge on any input can produce only a positive edge at the output If an expression contains only AND and OR with no inversions, it is non-inverting Examples
Non-Inverting:
A BC D
Inverting:
A B C D A B AB AB
W. Rhett Davis NC State University Slide 22 ECE 546 Fall 2011
Example
Implement the function F=AB+BC+D as a two-stage two stage C2MOS Pipeline Use the following architecture:
f A, B, C , D A, B, C , D
g f A, B, C , D
f
A, B, C , D f A, B, C , D
g f A, B, C , D
positive non- negative nonpositive latches inverting latches inverting latches logic logic
W. Rhett Davis NC State University Slide 23 ECE 546 Fall 2011
Example
W. Rhett Davis
Example
Circuit Diagram:
F A B B C D
NOTE: NORA CMOS: Use Dynamic Domino-Gates NORA-CMOS: Domino Gates with this structure for very-high performance
W. Rhett Davis NC State University Slide 25 ECE 546 Fall 2011
Summary
Learned how to estimate setup- and hold-times using delays of inverters and transmission gates. Learned how to express timing constraints of a flip-flop to ensure proper operation during clock-overlap. p p p g p Learned how to make a flip-flop that is insensitive to p (C ) clock-overlap ( 2MOS) Learned how to make an edge-triggered flip-flop that does not require two clock-phases (TSPC) clock phases Learned how to build a very-high speed pipeline using C2MOS latches and non-inverting logic
NC State University Slide 26 ECE 546 Fall 2011
W. Rhett Davis