Validation Techniques for Integrated Circuit Layout

Manoj Sharma, Ankur Sangal and Bharat Singh

information can be reported which ultimately quantifies the decision while evaluating novelty of the IC Layout. Under this the design is checked at block level, RTL level, nwet-list level, schematic level and finally at layout level. The organization of paper is as follows: Second section describes the complexity involved in novelty checking of the IC Layout and the capabilities of the existing VLSI CAD tools wrt novelty check. Section three provides some thumb rules for validating the novelty of IC Layouts. Section four summarizes some practices that IC Layout design engineers can follow to protect their design against infringements. Section five concludes the paper. I. IC LAYOUT VALIDATION USING EXISTING TOOLS A. Complexity involved into novelty check The IC layout consists of polygons, spread in different layers. These polygons may be changed in uncountable manner to create a new IC layout which would look different from the existing one. Some of the changes that can be made are listed below: 1.Changing of layers. 2.Increasing or decreasing number of Layers. 3.Changing position of geometries. 4.Changing orientation of geometries. 5.Changing scaling of geometries 6.Inserting dummy geometries. 7. Interchanging geometries among layers. Hence while checking for novelty, it is needed that each geometry is to be analyzed. This analysis can be made only when the number of geometries is small. A simple inverter hasaround 55 geometries shown in Table-1 which have only two numbers of transistors and in todays world, chips have million of transistors, hence it is practically impossible to analyze the geometries for novelty in this way. So it can only be done using Computer Added Design (CAD) tools.
1T 2T Adder No. of 6 11 16 Layers No. of 11 55 1302 1443 geometries Table 1. Increase in complexity with increase in transistors 32 bit MUX 21

Abstract Integrated circuit (IC) layout novelty validation involves comparison of geometries present in different layers. The present paper highlights the importance of Integrated Circuit Layout validation for checking its novelty in terms of Intellectual Property Right. In the paper, we described the complexity involved in comparing the IC layouts and the capabilities of the CAD tools for comparing the layouts. The techniques which are used by designer to protect their designs against infringement are also discussed. Finally we have suggested thumb-rules, for IC Layout evaluation - in terms of their novelty, at four stages namely Specification, Prior-art database search, Computer added tools and visual inspection. The proposed thumb rules are applied on 58 LD for checking the common part in them, the results obtained are satisfactory. Keywords Integrated Circuit Layout, validation technique, Intellectual Property

Integrated Circuit Layout novelty validation involves comparison of geometries present in different layers. Integrated circuit layout also as called IC Layout, IC mask layout or masks design; represents the integrated circuit in terms of planar geometric shapes corresponding to the patterns of metal, oxide, semiconductor layers constituting the components of the integrated circuit, implementing the desired functionality. The IC layout comparison is done in industry using XOR operations on the geometries of the two involved IC layouts as shown in Fig.1 G1 XOR G2 G2
Figure 1: demonstration of XOR operation on two geometries G1 and G2 of rectangular shape. The yellow color shows absence of geometrical information

G1

Till recently the IC layout comparison application / area is limited to this level only, for which every industry have their own scripts to work on their own IC layout Electronic Data Base. But for validating the novelty of the IC Layout this simple process of comparison would never provide right solution as one can modify the layout in many ways which cannot be checked by this simple geometric comparison. Therefore, this opens another research area to address the needs of validating IC Layout novelty in terms of geometric shapes distribution. To address this, authors came-up with a strategic planned process involving different stages through which some useful

B. Availability of methods for IC layout novelty check and capabilities of existing tools The Engineering Computer Aided Design (ECAD) tools from Cadence, Synopsis, Mentor, Tanner shown in Table-2 provide features to compare the interconnectivity of the

Proceedings of ASCNT-2011, CDAC, Noida, India, pp

Manoj Sharma, Ankur Sangal, Bharat Singh components. They take the net-list file of the design as input and compare the component i.e. transistors, their connectors and properties. The input net-list of the design can be extracted either from schematic or layout. Tool/ Inpu Parame Algo Efficie Suite t/ ter imple ncy name form compar mente ats ed d Tann LVSSpic Connec Routin Less er edit e tion g flexibl [1] file No. of Match e [1] devices and [1] net Match ing algo Ment LVSLay Connec Routin Provid or calibe out tion g es r [2] :No. Match more GDS device. and flexibi II , Device net lity for SPI specific Match compa CE ations, ing ring Sch [2] algo mati c :SPI CE [2] Table 2. Tools with their capabilities So if the incoming design is intensely tailored (copied from existing one) with some changes in interconnection and/or introduction of some dummy layers/geometries, then this method would never be able to provide information about the novelty of the design. Hence the tools which exactly perform the matching of the geometries in the design are needed. This comparison is done using the Graphic Database System II (GDSII) file of the design. This is a binary file which is human un-readable format [3-6]. This contains information about geometries, their layers, text etc. The tools take two GDSII file as input and provide option to perform AND, OR, XOR, operations as shown in Table-3. Operator Operation AND Provides common geometries OR Provides all geometries XOR Provides uncommon geometries Table 3. Operators and their operations The 58 Layout designs (LD) were designed for establishing the novelty check using the proposed process. These designs incorporate the above mentioned modifications/changes in the layouts that can be made to infringe the original layout and all checks are performed to quantify the decision over novelty of the design. The different GDS files have been compared with different permutation and combination of features like mirror, rotate, shift, scale, window selection etc. The output GDS file provides the common/uncommon geometries between two GDSII files. The geometry can be the part of any useful circuits. In that case it is to be analyzed that this common geometry is meaningful to the logic and/or it may be intensely present (i.e. copied) and/or it may be unintensely present there. These tools help greatly in comparing geometries but still the method/process of comparing the IC layout is very complex because on the output GDSII file from the tool, an engineer has to perform manual checks on thousands of geometries in the outputted GDSII file to infer about the novelty of the design. We have suggested some steps for layout comparison in the next section. II. METHODS FOR PROTECTING THE LAYOUT DESIGN Beside the above mentioned methods for comparing the two layout designs, there are other methods to identify the original and pirated designs. Presently designers start the protection process with design in the implementation phase using constrained based protection techniques, which have basically three parts. [8- 12] Watermarking: In this method the designer adds signature to protect the IC Layout. Here, the IC Layouts are to be altered to embed a certain type of impression for watermarking as minute errors. The signature is encoded as additional constraints and is added to the problem specification. With given design specification, designer builds the watermarking engine which takes both- design and signature specification, as input returns the final design. The Fig.2 shows the traditional process and design process with watermarking. [8]

Figure 2: Constrain-based watermarking in system design process.

In full custom design the net-list level (which is derived from transistor level schematic), a watermark bit is embedded into a transistor/ transistors by changing the transistor width to fit the watermark value. The variation should be less than process variation. The watermark net-list is then imported to EDA tools for re-simulation, layout and other verifications.

Validation Techniques for Integrated Circuit Layout Fingerprinting: The aim of fingerprinting is to protect the misuse of design. To enable this, it becomes necessary to assign distinct copy of design to different users. This creates the problem of generating large amount of solution efficiently. To solve this problem, two types of fingerprinting techniques are used: iterative fingerprinting and constrained manipulation technique. The flow for both the techniques is shown Fig.3: with GDSII in database. While comparing following parameters are to be checked: i. Scaling of the design ii. Orientation of the design iii. Number of layer iv. Presence of dummy layers v. Number of transistors vi. Presence of dummy elements vii. Number of differences in the GDS file viii. Number of overlaps contributing to a certain logical element ix. Number of overlaps contributing to non-logical element x. Number of overlaps in the path interconnections xi. Number of overlaps in the transistors geometries Using Optical Visual Inspection- Here the fabricated LD is to be compared for matching patterns. Using a high resolution microscope the patterns of the fabricated unpacked chip can be seen up to 3-4 top layers. These patterns are compared with the top 3-4 layers of the LD. The analysis results from each of above four thumb rules are to be cumulatively accessed depending upon the set priority. These thumb rules illustrating different checks are to be carried out on the IC-LD increases the chances of catching the copied LD. B. Methodology for applying thumb rules The specifications of the LD are extracted in the first level (stage I) which are to be compared with the prior art database to find all the nearest LDs reported earlier (stage II). The softdatabase (tool-files of the design and GDSII file) of these LDs from prior art database is to be analyzed using CAD tools (stage III). The hard-database (de-mounted fabricated ICs and/or layered printout of the GDSII file) of the LDs from prior art database are to be analyzed using high-resolution microscope (stage IV). The Prior-art Data Search (PDS) is developed under the grant-in-aid -Department of IT (DIT) project Development of Database for Digital IC Layout Design, according to the requirements of the customer. It is an exhaustive data-base for digital IC Layout design by collecting information from various public domain/open access resources like books, patents office, International- National Journal, conferences, workshops, research organizations, academics, industries. PDS is generic in design and scalable for any application and is hardware independent. It can be ported easily and provides integrated environment for user to access data on any given topic by searching through the backend database with hyperlinked original documents, images and PDFs. This prior art database gives the information about nearest existing design which can be used as ready reference to compare the new layout design by searching in multiple fields. VLSI CAD tools, give detailed information about the

Figure 3: Fingerprinting in system design process Copy Detection: The aim of copy detection is to find out the hidden signature from the design or IPs. Using these techniques one has to verify the existence of marks/ signatures, which are embedded into the design as constrained. Most of these verification processes are hard in nature. However, fast detection can be done on the basis of arguments that the watermark/ fingerprint must be hidden behind certain parts of the problem with unique structure that are difficult to alter. By identifying these marks a suspicious copy of unauthorized LD/ IPs can be detected. III. SUGGESTED THUMB RULES FOR IC LAYOUT COMPARISON To compare the two layout designs, a systematic approach should be carried out at different levels from front-end to back-end of the design. A. Proposed Thumb rules Following proposed thumb rules perform validation at four stages: Specification level- Extract the functionality specification of the LD like current/voltage ratings, temperature range, power consumption, speed, area and LD design approach. Prior art database search- Compare above extracted features in the Prior-art Data Search (PDS) to search for the nearest LD available. The search should be made comprehensively with different set of keyword, technology, and other specification parameters to find all the nearest reported LDs. Using Computer Aided Design (CAD) tools- CAD tools are to be used for two processes: Net-list comparison: The number with properties of transistors and their interconnectivity are compared using tools. Geometry comparison: Compare the GDSII file of the LD

Manoj Sharma, Ankur Sangal, Bharat Singh similarities and differences of two layout designs at different level like GDSII, Layout, Schematic and net-list [1, 2, 7]. IV. CONCLUSION The paper highlights the new research area of novelty validation of IC Layouts and its complexity. The paper provides features in the existing Engineering Computer Aided Design (ECAD) tools, which can be used for novelty checks and summarizes the techniques which can be used for preventing IC Layout from infringement. The authors have proposed four thumb rules for validating the IC Layout. Fifty-eight layouts were designed keeping in reference, the aspects of orientation, transformations, transistors number and size. The thumb rules are applied on them for novelty check through which the authors are able to satisfactorily conclude the common and un-common part in the LDs. The need of automation in processing the post comparison GDSII files with new CAD tools can be taken as future work. ACKNOWLEDGMENT The authors are grateful to SICLDR, Department of IT, and Ministry of Information Technology for providing the opportunity to CDAC Noida to carry out the grant-in-aid project Development of Database for Digital IC Layout Design. The authors are thankful to the project team members Dr. Arti Noor, Ms. Sunita Prasad, Mr. Ayoub Khan, Mr. Ravi Payal, Ms Renuka Bansal and Mr. Sachin Bajaj for their contribution and suggestions. REFERENCES
[1] [2] [3] Products- Physical Layout-DataSheets http://www.tannereda.com/ , 12 Jan 2011, and tools installed Products -Calibre, IC Station http://www.mentor.com/ ,12 Jan 2011 , and tools installed GDSII Format http://boolean.klaasholwerda.nl/interface/bnf/gdsformat.html, 20 Dec 2010 Manoj Sharma, Member IEEE, M.Tech ( VLSI Design ) MBA ( Systems ), B.Tech ( Electrical and Electronics ) PGD ( GIS, Embedded System and VLSI Design ) has 5+ year of experience in tools customozation and electronics, VLSI. [4] The GDSII Stream Format http://www.buchanan1.net/stream_description.shtml, 20 Dec 2010 [5] SPIE Handbook of Microlithography, Micromachining and Microfabrication Data Preparation http://www.cnf.cornell.edu/cnf_spietoc.html, dated 20 Dec 2010 [6] Calma GDS II stream format (GDSII) http://www.iue.tuwien.ac.at/phd/minixhofer/node52.html, 20 Dec 2010 [7] EDA products- postlayout_eda_products http://www.softjin.com, 10 Dec 2010 [8] Gang Qu , Miodrag Potkonjak , Intellectual Property Protection in VLSI Design: Theory and Practice USA KLUWER ACADEMIC PUBLISHERS , 2004 [9] J lach, W H Mangions Smith, M Potkonjak, FPGA fingerprinting Techniques for protecting Intellectual Property, Proc of IEEE 1998 on Custom Integrated Circuit Conf.(CIICC), pp 299-302, May 1998 [10] LE Caldwell , H Choi, A B Kahng, S Mantik, M Potkonjak, G U and J L Wong, Effective Iterative Techniques for Fingerprinting Design If, 36th Proc. On Design Automation Conference, pp 843-848, 1999 [11] A B Kahng, J Lac, W H Magione Smith, S Mantik, I L Markov, A T Potkonjak, P Tucker, H Wang and G Wolfe. Watermarking Techniques for Intellectual Property Protection. 35th Proc. on Design Automation Conference, pp 776-781, 1998.

Ankur Sangal B.Sc (Electronics) , M.Sc (Electronics) M.tech (VLSI Design ) Has 1+ year experience in ASIC Desgn tools customozation and electronics, VLSI.

Bharat Singh B.Tech(Electronics & communication), M.Tech(VLSI Design) Has 1+ year experience in ASIC Desgn and electronics, VLSI.