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Square Topology for NoCs

M. Ghorbanian, R. Sabbaghi-Nadooshan, H. Doroud
Abstract In this paper different topologies are studied and their functions in networks are described. Ultimately, some novel topology are introduced and compared with existing ones in regard of factors such as power and delay. This paper proposes square topology as an efficienttopology for NetworkonChips (NoCs).Although the proposed topology imposes the cost near to that of the mesh topology, the proposed topology 1) provides lower diameter for NoC, 2) offers better performance under uniform and hotspot traffic pattern. Results of comparisons show that pro posedtopologyperformbetterthanMeshandSpidergontopology.

Index TermsSquare, Topology, NoCs, Performance evaluation, Power consumption

1 INTRODUCTION
etwork-on-Chip (NoC) is a promising communication paradigm for multiprocessor system-on-chips. This communication paradigm has been inspired from the packet-based communication networks and aims at overcoming the performance and scalability problems of the shared buses in multi-core SoCs (System on Chips) [1][2]. Although the concepts of NoC are inspired from the traditional interconnection networks, they have some special properties which are different from the traditional networks. Compared to traditional networks, power consumption is the first-order constraint in NoC design [3][4]. As a result, not only should the designer optimize the NoC for delay (for traditional networks), but also for power consumption. The choice of network topology is an important issue in designing a NoC. Different NoC topologies can dramatically affect the network characteristics, such as average inter-IP distance, total wire length, and communication flow distributions. These characteristics in turn, determine the power consumption and average packet latency of NoC architectures. In general, the topologies proposed for NoCs can be classified into two major classes, namely regular tilebased and application-specific. Compared to regular tilebased topologies, application-specific topologies are customized to give a higher performance for a specific application. Moreover, if the sizes of the IP cores of a NoC vary significantly, regular tile-based topologies may impose a high area overhead. On the other hand, this area overhead can be compensated by some advantages of regular tile-based architectures. Regular NoC architectures provide standard structured interconnects which ensures well-controlled electrical parameters. Moreover, usual

physical design problems like crosstalk, timing closure, and wire routing and architectural problems such as routing and switching strategies and network protocols can be designed and optimized for a regular NoC and be reused in several SoCs. In this paper, we propose a topology called square. Simulation has shown that our topology can achieve better performance than the mesh, and is more suitable for NoC with increase number of nodes.

The rest of this paper is organized as follows: section 2 introduces the square and spidergon topology. Section 3 studies the routing in square topology. Section 4 concludes the paper.

2 SQUARE TOPOLOGY
Considering the comparison between topologies we have defined a new topology called square topology. This topology almost inspired form spidergon topology, but its nodes distribute on square instead of circles. In this section we first describe spidergon topology, and then define square topology.

2.1 SPIDERGON TOPOLOGY

The spidergon NoC is a network which is proposed by ST Microelectronics [5]. Fig. 1 is an instance of spidergon topology with 16 nodes. The small circle with numbers stands for a node; every node is composed of a processing element (PE) and a router. The processing element can be memory, IP and so on; the router is used for routing packets from the local processing element to other routers. Each node connects to other nodes in three direc tions: clockwise, anticlockwise and cross-link. For exam M. Ghorbanian is with the IslamicAzad University Central Tehran Branch, ple, the node 0 connects to node 1 in clockwise, to node 15 Tehran, Iran. R. Sabbaghi-Nadooshan is with the Department of Electronic Engineering, in anticlockwise, and to node 8 in cross-link. The routing algorithm in the spidergon is quite simple [5]. IslamicAzad University Central Tehran Branch, Tehran, Iran.
H. Doroud is with the IslamicAzad University Central Tehran Branch, Tehran, Iran.

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3 ROUTING OF SQUARE TOPOLOGY

Routing of proposed square topology is very simple and each node is connected from each single side to other nodes. The corner nodes in inner squares are connected to corner of same square. Also we have routes in the front nodes, based on inner layer. For example routing of inner corner square which are connected to outer can be written as follows: 1 17 33 49

Fig. 1. The spidergon network with 16 nodes [5].

Note that we have some routed to reach from node zero to the destination node 48, however we choose the shortest route to reach destination node. The paths based on rings can be written as following: 1 1 2 2 5 5 5 9 6 8 7 3 4

2.2 Structure of Square Topology

Considering four square adjacent together which are connected through 16 nodes and each node of each square connected in each single direction also they are connected diagonally. The new topology has 64 nodes and the Fig. 2 represents square topology with 64 nodes. The degree of corner nodes in inner square are 6, however for corner nodes are 5. Also parallel side inner square node has degree of 4. However the outer square node has degree 3. The numbers of edges which are connected together are called degree of each node and the largest degree indicates the degree of network, therefore the degree of square topology is 6.

1 1 1 1

The average distance of each node is 3.49 imply routing algorithm compare to the mesh topology (3.64) is desirable. The networks are compared on Table 1.

Table I. The networks parameters

Network Square spidergon mesh

Nodes Number 2n 2n 2n

Diameter n+1 2n+4 2(2n/21)

Degree

n n/2 4

Fig. 2. The Squre network with 64 nodes

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4 SIMULATION
To evaluate the performance of Square architecture, we develop a discrete event simulator operating at flit level using xmulator [6]. We set the networks link width to 128 bits. Each link has the same bandwidth and one flit transmission is allowed on a link. The power is calculated based on a NoC with 90 nm technology whose routers operate at 2.5 GHz. Based on the core size information presented in [7], we set the width of the IP cores to 1 mm, and the length of each wire is set based on the number of cores it passes. The simulation results are obtained for 88 mesh NoCs with XY routing algorithm, and square NoCs using the routing algorithms described in the previous section. The message length is assumed to be 16, 32 and 64 flits and 1 virtual channel per physical channel are used. Messages are generated according to a Poisson distribution with rate . The traffic pattern can be Uniform and Hotspot [8]. With introducing this simulator and checking the advantages of this simulator for mesh and square topology the delay and power figures are the following: The x axis of these figures indicating the generation rate and y axis indicating power and delay our simulation. In Fig. 3, the average message latency is plotted as a function of message generation rate at each node for the mesh and square networks of 64 nodes using deterministic routing for different message sizes. As can be seen in the Fig. 3, the square has smaller average message latency with respect to the equivalent mesh network. The reason is that the average inter-node distance of the square network is lower than the equivalent mesh network. Fig. 4 compares the total network power in topology mesh and square of 64 nodes with different message lengths of 16, 32, and 64. Fig. 5 shows the average message latency in the 88 simple mesh and square for different traffic patterns with massage length of 16. As can be seen in the Fig. 5, the square NoC achieves a reduction in message latency with respect to the simple 2D mesh network for the full range of network load under various traffic patterns (especially in uniform traffic). For hotspot traffic load a hotspot rate of 14% is assumed (i.e. each node send 14% of messages to the hotspot node (node 36) and the rest of messages to other nodes uniformly). Note that increasing the network size causes earlier saturation in a simple 2D mesh. Fig. 6 demonstrates power consumption of the simple 2D mesh and square under deterministic routing scheme with various traffic patterns. It is again the square that shows a better behavior before reaching to the saturation point. Fig. 7 compares the average message latency in spidergon and square of 64 nodes with different massage lengths of 16, 32, and 64. As can be seen, the square has smaller average message latency with respect to the equivalent spidergon network. The obtained result of xmulator indicate the square topology relative to mesh topology go to the saturation later and can send more packages, therefore has more power also the average distance length of the square to-

pology is less than mesh topology. The results indicate that the power of square network is less for light to medium traffic loads. The main source of this reduction is the long wires which bypass some nodes and hence, save the power which is consumed in intermediate routers in an equivalent mesh topology. Although for low traffic loads the square network provides a better power consumption compared to the simple 2D mesh network, it begins to behave differently near heavy traffic regions. It is notable that a usual advice on using any networked system is not to take the network working near saturation region. Having considered this and also the fact that most of the networks rarely enter such traffic regions, we can conclude that the square network can outperform its equivalent mesh network when power consumption is considered.

Fig. 3. The average message latency in the 88 simple mesh and square for different message lengths.

Fig. 4. Total power in the 88 simple mesh and square for different message lengths.

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5 CONCLUSION
In this paper we proposed square topology for Networkon-Chips. In the simulation section the performance of square with mesh and spidergon has been compared. Simulation results show that by using this topology performance of network is improved. In future work, we are trying to increase the size and number of node square topology in order to simulate the power, delay and other specific parameter for topologies.

Fig. 5. The average message latency in the 88 simple mesh and square for different traffics patterns with message length of 16.

REFERENCES
[1] [2] [3] A. Jantsch, H. Tenhunen, Network on Chip, Kluwer Academic Publishers, 2003. T. Bjerregaard and S. Mahadevan, A Survey of Research and Practices of Network-on-Chip, ACM Computing Surveys, Vol. 38, March 2006. P. P. Pande, C. Grecu, M. Jones, A. Ivanov and R. Saleh, Performance Evaluation and Design Trade-Offs for Networkon-Chip Interconnection Architectures, IEEE Transactions on Computers, Vol. 54, No. 8, August 2005. J. Hu and R. Marculescu, Energy-performance aware mapping for regular NoC architectures, IEEE TCAD, 2005. M. Coppola et al. Spidergon: a novel on chip communication network, proc. Intl Symposium on System on Chip 2004, Tampere, Finland, Nov. 2004. A. Nayebi, S. Meraji, A. Shamaei, H. Sarbazi-Azad, Xmulator: A listener-Based Integrated Simulation Platform for Interconnection Networks, Proc. of Asian Int. Con. on Mod. Sim., pp. 128-132, 2007. R. Mullins, A. West and S. Moore, The Design and Implementation of a Low-Latency On-Chip Network, Asia and South Pacific Design Automation Conference, pp. 164-169, 2006. J. Duato, S. Yalamanchili, L. M. Ni, Interconnection Networks, Morgan Kaufman, 2003.

[4] [5] [6]

[7] [8]

Fig. 6. Totat network power in the 88 simple mesh and square for different traffics patterns with message length of 16.

M. Ghorbanian is MS candidate in electronic engineering from Central Tehran Branch of Islamic Azad University. Her research interest includes interconnection networks, Networks-on-Chips. R. Sabbaghi-Nadooshan received the B.S. and M.S. degree in electrical engineering from the Science and Technology University, Tehran, Iran, in 1991 and 1994 and the Ph.D. degree in electrical engineering from the Science and Research Branch, Islamic Azad University, Tehran, Iran in 2010. From 1998 he became faculty member of Department of Electronics in Central Tehran branch, Islamic Azad University, Tehran, Iran. His research interests include interconnection networks, Networks-on-Chips, and embedded systems. H. Doroud received the B.S.degree in electronic engineering from Central Tehran Branch of Islamic Azad University. His research interest includes interconnection networks, Networks-on-Chips.

Fig. 7. The average message latency in the 64 nodes spidergon and square with different message lengths.