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Logic Gates Combinational Logic Boolean Identities and De Morgans Laws Karnaugh Map Programmable Logic Devices Seven Segment Decoder / Driver Binary Decoder 4-bit Magnitude comparator

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Logic Gates
A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. An output of one logic gate can connect to the input of one or more other logic gates. Two outputs cannot be connected together. Logic gates comes in packages called Integrated circuit (IC) or common used term (non technical) Chip as shown below. Logic gates uses only two logic values; 0 (0V) and 1 (5V). Logic 0 (0V) can be: false, off, low, no, open switch. Logic 1 (5V) can be: true, on, high, yes, closed switch.

The 7400 IC, containing four NAND logic gates. The two additional contacts are supply power (+5 V) and the ground (0V).

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AND Gate The Boolean expression for the AND operation is X = A B . This is read as X equals A and B. X = 1 (5V) when A = 1 (5V) and B = 1 (5V). Truth table and circuit symbol for a two input AND gate are shown.

OR Gate The Boolean expression for the OR operation is X = A + B . This is read as X equals A or B. X= 1 (5V) when A = 1 (5V) or B = 1 (5V). Truth table and circuit symbol for a two input OR gate are shown.

NOT Gate The Boolean expression for the NOT operation is This is read as X equals not A , or X equals the inverse of A , or X equals the complement of A Truth table and circuit symbol for the NOT gate is shown
X =A

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NAND Gate The Boolean expression for the NAND operation is X = A B . This is read as X equals A nand B Truth table and circuit symbol for the NAND gate is shown

The NAND gate can be constructed using the 2 basic gates (AND and NOT) as shown below

Also the NAND gate can be implemented using 2 NOT gates and 1 OR gate.

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NOR Gate The Boolean expression for the NOR operation is X = A + B . This is read as X equals A nor B Truth table and circuit symbol for the NAND gate is show.

The NOR gate can be constructed using the 2 basic gates (OR and NOT) as shown below

Also the NOR gate can be implemented using 2 NOT gates and 1 AND gate

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XOR Gate The Boolean expression for the XOR operation is X = A B . This is read as X equals A xor B Truth table and circuit symbol for the XOR gate is show.

The XOR gate can be constructed using the 3 basic gates (AND, OR and NOT) as shown below
X = A B = A B + A B

XNOR Gate The Boolean expression for the XNOR operation is X = A B . This is read as x equals A xnor B Truth table and circuit symbol for the XNOR gate is show.

The XOR gate can be constructed using the 3 basic gates (AND, OR and NOT) as shown below

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Integrated Circuits (IC) All of the basic gates are available in several types of IC packages. They are identified by the last two or three digits in the series designation. For Example, 74LS00 means 74 = Logic Technology, LS = Low Power Schottky, 00 = Quad 2-input NAND Gate.

Below are the pin configuration for some common IC gates

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Data Sheet A typical data sheet consist of information page that shows the logic digram, package, electrical specifications and characteristics.

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Applications A seat Belt Alarm System

Home Security System

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Liquid Tank Level Indicator

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Airplane Landing Gear Monitoring System

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Combinational Logic Circuits

A combination of logic gates interconnected to produce a specific function. There is no feedback from output of the circuit to the input. The output is a function of the current input status. Combinational logic circuits uses some or all of the basic logic gates AND, OR and NOT. Example of combinational logic circuits:

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Designing Combinational Logic Circuits To solve any logic design problem: Interpret the problem and set up its truth table. Write the AND (product) term for each case where the output equals 1. Combine the terms in OR form. Implement the circuit . Example: A Petrol station has 2 underground tanks to store petrol. A level sensor attached to each tank produces 0V when the level of the petrol in the tank drops below a specified point. Design a circuit that will produce 5V to turn on a light when the level in any two tanks drops below the specified point. Solution: Interpret the problem and set up its truth table

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Sensor = 0V when tank below specified level 5V when tank above specified level Light = 5V Turn on 0V Turn off A 0 0 1 1 Truth Table B Output 0 1 1 1 0 1 1 0

Write the AND (product) term for each case where the output equals 1. A 0 0 1 1 B 0 1 0 1 Output 1 1 1 0
A B A B A B

Combine the terms in OR form

O tpu u t = A B +A B +A B

Implement the circuit .

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Deriving Boolean Expression for the output of a given Combinational Circuit To Find the Boolean expression for the output of a given combinational circuit: Trace each input signal all that way to the output Example: Find the Boolean expression for the output Q of the given circuit below.

Solution Trace each input signal all that way to the output

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Deriving the truth table for a given combinational circuit To Find the truth table of a given combinational circuit Identify the number of input signals and list all possible combinations for the input For each input combination, trace the circuit all the way to the output. Example: Find the truth table of the given circuit below

Solution: Identify the number of input signals and list all possible combinations for the input Number of input signals = 3 (A ,B and C) Number of possible combinations = 2 3 = 8 (from 0 to 7) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Output = Q

For each input combination, trace the circuit all the way to the output. 1st Combination

2nd Combination
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3rd Combination

4th Combination

8th Combination

Finally the complete truth table is shown

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A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Output = Q 1 1 1 0 1 1 1 0

Deriving the output voltage waveform for a given input waveform To Find the output voltage waveform for a given input waveform Identify the time slots where the input signals changes For each time slot, identify the voltage level for each input at intermediate points From the intermediate points compute the output voltage level Example: Determine the output voltage waveform of the circuit below, given the input waveform.

Solution: Identify the time slots where the input signals changes

For each time slot, identify the voltage level for each input at intermediate points 18
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From the intermediate points compute the output voltage level

Boolean Algebra and De Morgans Laws

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Boolean Algebra and De Morgans law are useful in optimizing (minimizing) expressions and thus reducing the logic circuit to their simplest form. Boolean Algebra Boolean Algebra is the mathematics of digital system. Boolean Algebra is divided into Laws and Rules. Boolean Algebra Laws: 1. Commutative Law of Addition A+B=B+A

2. Commutative Law of Multiplication: AB = BA

3. Associative Law of Addition: A + (B + C) = (A + B) + C

4. Associative Law of Multiplication: A(BC) = (AB)C

5. Distributive Law: A(B + C) = AB + AC

Boolean Algebra Rules: 1. Rule #1

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A+0 = A

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2. Rule #2

A + 1= 1

3. Rule #3

A0 = 0

4. Rule #4

A 1 = A

5. Rule #5

A+A= A

6. Rule #6

A +A =1

7. Rule #7

AA = A

8. Rule #8

A A =0

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9. Rule #9

A =A

10. Rule #10

A + AB = A

11. Rule #11

A + AB = A + B

12. Rule #12

( A + B )( A + C) = A + BC

Example (See page 13): A Petrol station has 2 underground tanks to store petrol. A level sensor attached to each tank produces 0V when the level of the petrol in the tank drops below a specified point. Design a circuit that will produce 5V to turn on a light when the level in any two tanks drops below the specified point.
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Sloution:

Using Boolean algebra the circuit can be minimized as follows:

Output = A B + A B + A B Output = A B + B + A B Output = A( 1) + A B Output = A + A B

( Distributive Law) ( Rule #6) ( Rule #4)

Example: Design combinational circuit that satisfy the given truth table

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Solution: The output Boolean expression is obtained for G = 1

G = xyz + xyz + xyz .

The circuit below satisfy the truth table.

The circuit can be minimized by using Boolean Algebra

De Morgans Laws Using De Morgans laws, makes it easy to manipulate Boolean expressions and simplify them or
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convert them to forms most convenient for translation to electronic logic circuits. The complement of AND is OR The complement of OR is AND The complement of two or more ANDed signals is equivalent to the OR of the complements of the individual signals
X Y =X Y X Y = X +Y

The complement of two or more ORed signals is equivalent to the AND of the complements of the individual signals
X+ = + Y X Y X + = Y Y X

Example:

Example: Prove that

( A + B + C ) D = A B C + D
( A + B +C ) D = ( A B C ) + D ( A + B +C ) + D = ( A B C ) + D

( A + B + C ) + D = ( A B C ) + D ( A B C ) + D = ( A B C ) + D

Example: Prove that

( A B +C ) + ( A + B C ) = A B C + A B C

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The Universal Property of NAND and NOR Gates NAND and NOR gates are universal because they can be used to produce any of the other logic functions. NAND Gate as an Inverter

NOR Gate as an Inverter

Two NAND Gates as an AND Gate

Three NOR Gates as an AND Gate

Three NAND Gates as an OR Gate

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Two NOR Gates as an OR Gate

Four NAND Gates as NOR Gate

Four NOR Gates as a NAND Gate

1) 2) 3)

The rules for the transformations are: The logical connective must be changed, (AND to OR, OR to AND). The logical state of each variable changes, (A to A , A to A). Finally the logical state of the complete expression must change, x es n x es n (e p r sio ) to (expression). (expression) to (e p r sio ) or

Example: Use only NAND gates to implement the following circuits

X = A B +C D

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Solution: Using De Morgans 1. The logical connective must be changed, (AND to OR, OR to AND).
X = ( A B ) (C D)

2. The logical state of each variable changes, (A to

X = ( A B ) (C D )

to A).

3. Finally the logical state of the complete expression must change, x es n x es n (expression) to (e p r sio ) or (e p r sio ) to (expression).
X = ( A B) (C D)

Example: Use only NAND gates to implement the following circuits

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Solution: The output of the circuit is

y = X X + X X 2 4 4 3

) (

Using De Morgans 4. The logical connective must be changed, (AND to OR, OR to AND).
y = X X X X 2 4 4 3

)(
)(

5. The logical state of each variable changes, (A to

y = X X X X 2 4 4 3

to A).

6. Finally the logical state of the complete expression must change, x es n p es n (ex r sio ) to (expression). (expression) to (e p r sio ) or
y = X X X X 2 4 4 3

)(

Example: Use only NOR gates to implement the following circuits

z = A +C (B +D )

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Solution: Using De Morgans 1. The logical connective must be changed, (AND to OR, OR to AND).
z = A +C +(B +D )

2. The logical state of each variable changes, (A to

z = A +C + B + D

(
(

) (

to A).

3. Finally the logical state of the complete expression must change, x es n p es n (ex r sio ) to (expression). (expression) to (e p r sio ) or
y = A +C + (B +D )

Karnaugh Map (K map)

The K map is a graphical tool used to optimize (reduce) the output boolean expression thus reducing the circuit. The truth table values are placed in the K map. Adjacent K map square differ in only one variable both horizontally and vertically. The pattern from top to bottom and left to right must be in the form
A B =0 , AB =0 , A =1 , A B =1 0 1 B 1 0

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Looping adjacent groups of 1, 2, 4, 8, 16, .of 1s will result in further simplification. Looping may also be wrapped between top, bottom, and sides. When the largest possible groups have been looped, only the common terms are placed in the final expression. Finally OR all groups that contain a 1.

Example:

Example:

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Example:

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Example: Write the optimized Boolean expression for the output Z shown in k map below

Z=

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Programmable Logic Devices (PLD)

Programmable logic devices (PLDs) are used in many applications to replace discrete Integrated Circuits. A PL containes logic gates and programmable switches that allow for different connections between the logic elements. PLD can implement many logic circuits.

The three common PLD devices are: 1. Programmable Logic Array (PLA) 2. Programmable Array Logic (PAL) 3. Generic Array Logic (GAL) Programmable Logic Array (PLA) PLA consists of input buffers and inverters that provide the true and complement form for each input variable. A collection of AND gates, with inputs that are selectable (programmable) and a collection of OR gates, with inputs that are selectable (programmable)

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Actual Gate Level Diagram

Simplified Schematic of PAL

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Each AND and OR gates have multiple inputs, but for simplicity the simplified schematic of a PAL show one line as an input to each gate. To make a connection on the simplified schematic of PAL, place an X at the desired node as shown in the figure below.

f1 = P + P2 + P3 1

f1 = ( X 1 X 2 ) + X 1 X 3 + X 1 X 2 X 3
f 2 = P + P3 + P4 1

) (

f2 = ( X1 X 2 ) + X1 X 2 X 3 + ( X 1 X 2 )

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Example: Design a logic circuit for the output f 39

=a b +b c

using PLA
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Solution #1:

Total number of Gates = 4 Total number of ICs =3 (one 7404, one 7408 and one 7432) Solution #2:

Total number of Gates = 4 Total number of ICs =1

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Programmable Array Logic (PAL) PAL consists of input buffers and inverters that provide the true and complement form for each input variable. A collection of AND gates, with inputs that are selectable (programmable) and a collection of OR gates, with inputs that are fixed.

Actual Gate Level Diagram

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Simplified Schematic of PAL

Example: Design a logic circuit for the output Solution:
f =a b +b c

using PAL

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Generic Array Logic (GAL) GAL , like the PAL , has a programmable AND array and a fixed OR array with programmable output logic . The two main differences between GAL and PAL devices are 1. The GAL reprogrammable 2. The GAL has programmable output configurations

Actual Gate Level Diagram

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Advantages of Programmable Logic Devices Reduce chip counts therefore less board area, power, and wiring. Simplify prototype circuitry. Shorten the development cycle. Allow the hardware of a circuit to be easily upgraded. Reduce parts inventory (save money)

Standard PAL Part Numbering Standard PAL come in variety of configurations , each of which is identified by a unique part number . This part number always begins with the prefix PAL . The first two digits following PAL indicate the number of inputs , which includes outputs that can be configured as inputs . The letter following the number of inputs designates the type of output: L-active-LOW , H-active-HIGH , or P-programmable polarity. The one or two digits that follow the output type is the number of outputs. Example: PAL10L8 PAL: Programmable array logic 10: Ten inputs L: Active-LOW output 8: Eight outputs In addition , a PAL part number may carry suffixes that specify speed , package type , and temperature range.

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Binary Decoder
Decoder : A digital circuit designed to detect the presence of a particular digital state/input. Can have one output or multiple outputs. Example : The simplest form of a decoder is the 2-Input AND. It detects the presence of 11 on the inputs to generate a 1 output.

Example: Design a circuit that generates a 1 at the output when it detects `1001 at the input. A3 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output = Q 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

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Example: Design a circuit that generates a 1 at the output when it detects `1011 at the input. 45

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A3 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1

A2 0 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1

A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Output = Q 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Example: Design a circuit that generates a 1 at the output when it detects `1001 or 1011 at the input.

If the circuit is going to detect all possible input combinations, then it will become a very large with many ICs.
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It will be more logical to design a special function IC that will detect all possible input combination. The IC will have n inputs and 2n outputs. It is called n-to-2n lines decoder or 1-of-2n decoder. The output can be active high or active low. The decoder below has 4 inputs and 2n = 16 outputs ( 4-to-16 lines decoder or 1-of-16 decoder). The output is active high. Each output corresponds to a specific input. If the input is A3 = 0, A2 = 0, A1 = 0, A0 = 0, then output number 0 is active 1 and the reset of the outputs are inactive 0. If the input changes to A3 = 1, A2 = 0, A1 = 1, A0 = 1, then output number 11 is active 1 and the reset of the outputs are inactive 0 and so on .

The output of the decoder below is active low. If the input is A3 = 0, A2 = 0, A1 = 0, A0 = 0, then output number 0 is active 0 and the reset of the outputs are inactive 1. If the input changes to A3 = 1, A2 = 0, A1 = 1, A0 = 1, then output number 11 is active 0 and the reset of the outputs are inactive 1 and so on .

Truth Table for 4-to-16 Lines Decoder (1-of-16 Decoder) Active Low Output
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The 74HC154 1 of-16 Decoder

S The C 1 and CS 2 inputs (pin #18 and pin #19) are chip selects (Enable) lines. They enable the chip to function when needed. Both lines need to be tied or driven low for the chip to function.

Example: A3 = 0, A2 = 0, A1 = 1, A0 = 1, CS 1 = 0 , CS 2 = 0 . What are the status of the output pins Solution: Output # 3 (pin #4) is active = Low and the rest of the outputs are inactive = High. Example: A3 = 0, A2 = 0, A1 = 0, A0 = 0, CS 1 = 0 , Solution: All of the outputs are inactive = High.
C 2 =1 . S

What are the status of the output pins

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The 74LS42 BCD-To-Decimal Decoder The BCD-To- Decimal decoder detects each BCD number ( 110 to 910). Each output corresponds to a specific BCD input. Output #4 (pin #5) corresponds to BCD 410 A3 = 0, A2 = 1, A1 = 0, A0 = 0. Any input greater than 910 is invalid and will not be detected by the decoder which cause all of the outputs will be inactive (5V).

The Seven Segment Display SSD is a display device. SSDs are commonly used in electronics as a method of displaying number or some letters. Below are a sample of available SSDs.

The figure below shows the basic layout of the segments in a SSD. The segments themselves are identified with lower-case letters "a" through "g," with segment "a" at the top and then counting clockwise. SSD also include a decimal point ("dp"). A segment can be turned on by driving the segement high (5V) or low (0V0 depending on the internal connections of the SSD.

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With a Common Anode SSD shown below, a low (0V) at the segment pin turns the segment on, provided that the common anode point is connected high (5V).

With a Common Cathode SSD shown below, a high (5V) at the segment pin turns the segment on, provided that the common cathode point is connected low (0V).

Below are the a) Pinout of a Common Cathode SSD b) Internal configurations and c) Interface

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Example: What inputs should be driven high = 5V in the common cathode SSD to display A ? Solution: a b c d e f g dp 1 1 1 0 1 1 1 0 The 74LS47 and 74LS46 BCD-To-Seven Segment Decoder The 74LS47 has active low outputs and it is suitable for common anode SSD where the 74LS46 has Active high outputs and it is suitable for common cathode SSD. The input is a BCD (010 to 910) number which will be detected by decoder and in response will activate the corresponding outputs for the SSD.

L T RI B
B I

= Lamp Test. When low all segments in the SSD are turned on. = Ripple Blanking Input. Used for Zero Suppression / R O = Blanking Input / Ripple Blanking output. Used for Zero Suppression. B

The number 06.030 can be display as 6.03 (zero suppression) by using the blanking control pins R I and BI / RBO . B If R I = 0 and the BCD input is 0000 then BI / RBO = 0 and all outputs are inactive = high and B the display of a common anode SSD will be blank. If R I = 0 and the BCD input is 0000 then B the BCD input
B /R O I B

=1 and the output will correspond to the

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The Comparator The basic function of a comparator is to compare the magnitude of 2 binary numbers to determine whether they are equal or not, and if they are not. The XOR gate is a basic one bit comparator as shown below. If A = B then X =1, otherwise X = 0

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Example: Design a circuit that compare two 2-bit binary numbers. The output of the circuit is equal to 1 if the numbers are equal otherwise 0. Solution: A = A1 A0 and B = B1 B0

The 74HC85 4-bit Magnitude Comparator The 74HC85 compares two 4-bit binay numbers say A and B and determines whether the number are equal ( A = B) or Less than (A < B) or greater than (A > B).

To determine an inequality of binary number A and B, first examine the MSB in each number. The following conditions are possible: 1. If A3 = 1 and B3 = 0, then A > B 2. if A3 = 0 and B3 = 1, then A < B 3. if A3 = B3, then must examine the next lower bit position for inequality.

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The 74HC85 has three cascading inputs A<B, A=B, A>B. these inputs allow several comparators to be cascaded for comparison of any number of bits greater than 4.

Example: Design a circuit that will compare two 4-bit binary numbers. Solution:

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Example: Design a circuit that will compare two 8-bit binary numbers. Solution: 1. The cascading inputs of the lower-order comparator should be connected as follows A>B = 0 , A=B = 1 , A<B = 0. 2. The outputs of the lower-order comparator should be connected to the corresponding cascading inputs of the higher-order comparator.

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