CMOS Analog Circuit Design (2nd Ed.

) – Homework Solutions Page 5-1

CHAPTER 5 – HOMEWORK SOLUTIONS

Problem 5.1-01
Assume that M2 in Fig. 5.1-2 is replaced by a 10kΩ resistor. Use the graphical technique
illustrated in this figure to obtain a voltage transfer function of M1 with a 10kΩ load
resistor. What is the maximum and minimum output voltages if the input is taken from
0V to 5V?
Solution
A computer generated plot of this problem is shown below.
5
+5V

4 10kΩ
Vout

Vin Μ1
3 2µm
Vout (V)

1µm

0
0 1 2 3 4 5
Vin(V) Fig. S5.1-01
The maximum output is obviously equal to 5V. The minimum output requires the
following calculation assuming that M1 is in the active region.
5- vout
110x10-6·2[(5-0.7)vout – 0.5vout2] =
10kΩ
5-vout
4.3 vout - vout2 = 2.22 → vout2 – 9.5 vout + 4.504 = 0
This gives,
vout (min) = 4.25±4.2945 = 0.5V
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-2

Problem 5.1-02
Using the large-signal model parameters of Table 3.1-2, use 5V
Eqs. (1) and (5) to calculate the values of vOUT(max) and
W2 = 1µm
vOUT(min). Compare with the results shown on Fig. 5.1-2 on L2 1µm
the voltage transfer function curve. ID
M2
Solution M1 +
From Eq. (5.1-1), Vout (max) can be calculated as vOUT
+ W1 = 2µm
vIN L1 1µm
Vout (max) = VDD − VTp = 4.3 V - -
Fig. S5.1-02

From Eq. (5.1-5), Vout (min) can be calculated as

(V − VT )
Vout (min) = VDD − VT − DD
β
1+ 2
β1
(5 − 0.7)
Vout (min) = 5 − 0.7 − = 0.183 V
(50)(1)
1+
(110)(5)
Problem 5.1-03
What value of β1/β2 will give a voltage swing of 70% of VDD 5V
if VT is 20% of VDD? What is the small-signal voltage gain W2 = β
L2 2
corresponding to this value of β1/β2?
ID
M2
Solution
+
Given VT = 0.2VDD and (Vout (max) − Vout (min)) = 0.7VDD M1
vOUT
+ W1 = β
From Eq. (5.1-1) and (5.1-5) vIN L1 1
- -
Fig. S5.1-03
(VDD − VT )
Vout (max) − Vout (min) =
β
1+ 2
β1
(V DD − 0.2VDD ) 1 + β 2  =  8 
2
β2
or, 0.7VDD = → β1   7  → β1 = 0.306
β 
1+ 2
β1

gm1 β
The small-signal voltage gain can be given by Av ≅ − = − 1 = -1.8 V/V
gm 2 β2
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-3

Problem 5.1-04
What value of Vin will give a current in the active load 5V
inverter of 100µA if W1/L1 = 5µm/1µm and W2/L2 = W2 = 2µm
2µm/1µm? For this value of V in, what is the small-signal L2 1µm
voltage gain and output resistance? ID
M2
Solution M1 +
vOUT
Assuming M 1 is operated in saturation + W1 = 5µm
vIN
'  W  (Vin − VT )
 2
 L1 1µm
I D1 = K N - -

 L 1  Fig. S5.1-04
2 
 (V − 0.7) 2 
or, 100 µ = (110 µ )(5) in  → Vin = 1.303V
 2 

The small-signal gain can be given by

g
Av ≅ − m1 = −
(K )  W   L 
'
N
= -2.345 V/V
gm 2 (K )  L   W 
'
P 1 2

1
The output resistance can be given by Rout ≅ = 7.07 kΩ
gm 2
Problem 5.1-05
Repeat Ex. 5.1-1 if the drain current in M1 and M2 is 50µA.
Solution
From Eqs. (5.1-1) and (5.1-5) we get
vOUT(max) = 4.3V
5-0.7
vOUT(min) = 5 – 0.7 - = 0.418 V
1 + (50·1/110·2)
From Eq. (5.1-7) we get,
vout gm1 148.3
vin = - gds1+gds2+gm2 = 2.0 + 2.5+ 70.71 = -1.972 V/V
From Eq. (5.1-8) we get,
1 106
Rout = g +g +g = 2.0 + 2.5 + 70.71 = 13.296 kΩ
ds1 ds2 m2
The zero is at,
gm1 148.3µS
z1 = C = 0.5ff = 2.966x1011 rads/sec → 47.2 GHz
gd1
The pole is at,
1 1
p1 = -ω-3dB = R (C +C +C +C ) =
out bd1 bd2 gs2 L (13.296kΩ)(1.0225pF)
= 73.555x106 rads/sec. → 11.71 MHz
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-4

Problem 5.1-06
Assume that W/L ratios of Fig. P5.1-6 are W1/L1 = VDD
2µm/1µm and W 2/L2 = W3/L3 = W4/L4 =
1µm/1µm. Find the dc value of V in that will give a
dc current in M1 of 110µA. Calculate the small
signal voltage gain and output resistance of Fig. M2 M3 M4
P5.1-6 using the parameters of Table 3.1-2. M1 +
Solution + vOUT 100µA
vIN
Assuming all transistors are in saturation and ideal - -
current mirroring Figure P5.1-6
 W   (Vin − VT ) 
2

I D1 = K N'
 L 1 2


 (V − 0.7) 2 
or, 110 µ = (110 µ )(2) in  → Vin = 1.7V
 2 
The small-signal voltage gain can be given by

gm1 K N'  W   L   I D1 
AV ≅ − =−   = -6.95 V/V
gm 2 K P'  L 1 W  2  I D 2 
where, I D 3 = I D 4 = 100 µA , and I D 2 = 10 µA .
The output resistance can be given by
1
Rout ≅ = 31.6 kΩ
gm 2
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-5

Problem 5.1-07
Find the small-signal voltage gain and the -3dB frequency in Hertz for the active-load
inverter, the current source inverter and the push-pull inverter if W1 = 2µm, L1 = 1µm,
W2 = 1µm, L2 = 1µm and the dc current is 50µA. Assume that Cgd1 = 4fF, Cbd1 = 10fF,
Cgd2 = 4fF, Cbd2 = 10fF and CL = 1pF.

VDD
M2 M2 M2
ID VGG2 ID
vOUT vOUT vIN ID vOUT

vIN vIN
M1 M1 M1

Active Current Push-

PMOS Load Source Load pull
Inverter Inverter Inverter
Figure 5.1-1 Various types of inverting CMOS amplifiers.
Solution
1. Active load inverter
The output resistance can be given by
1 1
Rout ≅ = = 14.14 kΩ
gm 2 2(50 µ )(1)(50 µ )
The total output capacitance can be given by
Cout = CL + Cgs2 + Cbd 2 + Cgd 1 + Cbd 1 = 1.029 pF
The –3 dB frequency can be given by
1
f −3 dB = = 10.9 MHz
2πRout Cout
2. Current-source inverter
The output resistance can be given by
1 1
Rout ≅ = = 222.22 kΩ
gds1 + gds2 I D ( λN + λP )
The total output capacitance can be given by
Cout = CL + Cgd 2 + Cbd 2 + Cgd 1 + Cbd 1= 1.028 pF
The –3 dB frequency can be given by
1
f −3 dB = = 0.697 MHz
2πRout Cout
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-6

Problem 5.1-07 - Continued

3. Push-pull inverter
The output resistance can be given by
1 1
Rout ≅ = = 222.22 kΩ
gds1 + gds2 I D ( λN + λP )
The total output capacitance can be given by
Cout = CL + Cgd 2 + Cbd 2 + Cgd 1 + Cbd 1= 1.028 pF
The –3 dB frequency can be given by
1
f −3 dB = = 0.697 MHz
2πRout Cout

Problem 5.1-08
What is the small-signal voltage gain of a current-sink 5V
inverter with W1 = 2µm, L1 = 1µm, W2 = L2 = 1 µm at ID W2 = 2µm
= 0.1, 5 and 100 µA? Assume that the parameters of the L2 1µm
devices are given by Table 3.1-2. 2.5V ID
M2
1. I D = 0.1 µA M1 +
vOUT
gm1 =
I D1
=
(0.1µ ) = 1.538 µS + W1 = 2µm
vIN
n pVt (2.5)(26 m) - -
L1 1µm

gm1 gm1
Av = − =− = - 170.9 V/V
(gds1 + gds2 ) ID (λN + λP )
2. I D = 5 µA

W 
gm1 = 2K P' I = 31.62 = 31.62 µS
 L 1 D1
gm1 gm1
Av = − =− = - 70.27 V/V
(gds1 + gds2 ) ID (λN + λP )
3. I D = 100 µA

W 
gm1 = 2K P' I = 141.42 µS
 L 1 D1
gm1 gm1
Av = − =− = -15.71 V/V
(gds1 + gds2 ) ID (λN + λP )
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-7

Problem 5.1-09
A CMOS amplifier is shown. Assume M1 and M2 operate in VDD
the saturation region. a.) What value of VGG gives 100µA M1
through M1 and M2? b.) What is the DC value of vIN? c.) vin 5µm/1µm
What is the small signal voltage gain, vout/vin, for this
amplifier? d.) What is the -3dB frequency in Hz of this vout
M2
amplifier if Cgd = Cgd = 5fF, Cbs = Cbd = 30fF, and CL =
500fF? 1µm/1µm
VGG
Solution
a) VGG = VT 2 + Vdsat 2 Figure P5.1-9
2ID 2
VGG = VT 2 + = 2.05 V
K (W L) 2
'
N

2 I D1
b) Vin = VDD − VT 1 − = 3.406 V
K (W L)1
'
P

v out gm1
c) Av = =− = -24.85 V/V
v in (gds1 + gds2 )
d) f −3 dB =
(gds1 + gds2 ) = 2.51 MHz.
(
2π Cgd 1 + Cgd 2 + Cbd 1 + Cbd 2 + CL )
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-8

Problem 5.1-10
A current-source load amplifier is shown. (a.) If C BDN VDD
=CBDP = 100fF, CGDN =C GDP = 50fF, C GSN = C GSP =
100fF, and C L = 1pF, find the -3dB frequency in Hertz. M3 M2
vout
(b.) If Boltzmann’s constant is 1.38x10-23 Joules/°K, find
the equivalent input thermal noise voltage of this amplifier CL
100µA
at room temperature (ignore bulk effects, η = 0). M1
vin All W/L's
Solutions
equal 10
(a.) The -3dB frequency is equivalent to the magnitude of
the output pole which is given as
Fig. P5.1-10
1 1 1 1
ω-3dB = R where Rout = g +g = 100µA(0.04+0.05) = = 111kΩ
C
out out ds1 ds2 9x10-6
Cout = Cgd1+Cbd1+Cgd2+Cbd2+CL = 0.05 + 0.05 + 0.1 + 0.1 +1 pF = 1.3pF
1
∴ ω-3dB = 0.111MΩ·1.3pF = 6.923x106 rads/sec. → f-3dB = 1.102 MHz

(b.) The noise voltage at the output can be written as

 gm1 2  gm2 2
eno 2 = en1 2 g +g  + en2 2 g +g 
 ds1 ds2  ds1 ds2
Reflecting this noise voltage back to the input gives the equivalent input noise as,

 g 3g8kT 
 gm22en22   m22 m2 = e 21 + gm2
eni 2 = en1 2 1 +g  e   = en1 2 1 + g  8kT
  m1  n1    m1 3g  n1  gm1
  m1
where
2IDKNW1 2IDKPW2
gm1 = L1 = 469µS, gm2 = L2 = 316µS,

2 8kT 8·1.38x10-23·300
and en1 = 3g = = 2.354x10-17 V2/Hz
m1 3·469x10-6
eni 2 = 2.354x10-17·1.6738 = 3.94x10-17V2/Hz → eni = 6.277nV/ Hz
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-9

Problem 5.1-11
Six inverters are shown. Assume that KN' = 2KP' and that λN = λP, and that the dc bias
current through each inverter is equal. Qualitatively select, without using extensive
calculations, which inverter(s) has/have (a.) the largest ac small signal voltage gain, (b.)
the lowest ac small signal voltage gain, (c.) the highest ac output resistance, and (d.) the
lowest ac output resistance. Assume all devices are in saturation.
VDD
M2 vIN vIN vIN
M2 M2 M2 M2
vOUT vOUT vOUT vOUT VBP vOUT vOUT
M2
vIN vIN M1
M1
M1 M1 M1
vIN VBN
M1
Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6

Figure P5.1-11
Solution

Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6

gm gmN= 2 gmP gmP gmN= 2 gmP gmP gmN= 2 gmP gmP
1 1 1 1 1 1
Rout ≈gmN+gmbN ≈gmP+gmbP ≈g
mP
≈g
mN gdsN+gdsP gdsN+gdsP
0.707 0.707 = =
=g +g ≈ g 1 1
mP mbP mP
gdsP(1+ 2) gdsP(1+ 2)
|Gain| gmP gmP 2 1 2 gmP gmP
gmP+gmbP gmP+gmbP gdsP(1+ 2) gdsP(1+ 2)
2

(a.) Circuit 5 has the highest gain.

(b.) Circuit 4 has the lowest gain (assuming normal values of gm/gmb).
(c.) Circuits 5 and 6 have the highest output resistance.
(d.) Circuit 1 has the lowest output resistance.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-10

Problem 5.1-12
Derive the expression given in Eq. (5.1-29) for the CMOS 5V
push-pull inverter of Fig. 5.1-8. If Cgd1 = Cgd2 = 5fF, Cbd1 W2 = 2µm
= Cbd2 = 50fF, CL = 10 pF, and ID = 200 µA, find the L2 1µm
ID
small-signal voltage gain and the −3 dB frequency if W1/L1 M2
= W2/L2 = 5 of the CMOS push-pull inverter of Fig. 5.1-8. + M1 +
vOUT
Solution vIN W1 1µm
=
L1 1µm
The effective transconductance can be given by - -
Fig.P 5.1-12
 W  W  
gm ,eff = gm1 + gm 2 = 2 I D  K N' + K P'
  L 1  L  2 
The output conductance can be given by
g out = (g ds1 + g ds 2 ) = I D (λ1 + λ 2 )
Thus, the small-signal gain becomes
g m, eff
Av = −
g out
 ' W  ' W 

K + K
2   L 1  L 2 
N P

Av = −   Eq. (5.1-29)
ID

( λ1 + λ2 )

 
For I D = 200 µA
Av = −43.63 = -43.63 V/V
The total capacitance at the output node is
( )
Ctotal = Cgd 1 + Cgd 2 + Cbd 1 + Cbd 2 + CL = 10.11 pF.
Thus, the –3 dB frequency is
gout
f −3 dB = = 283.36 kHz.
2πCtotal
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-11

Problem 5.1-13
For the active-resistor load inverter, the current-source load inverter, and the push-pull
inverter compare the active channel area assuming the length is 1µm if the gain is to be
−1000 at a current of ID = 0.1 µA and the PMOS transistor has a W/L of 1.

VDD
M2 M2 M2
ID VGG2 ID
vOUT vOUT vIN ID vOUT

vIN vIN
M1 M1 M1

Active Current Push-

PMOS Load Source Load pull
Inverter Inverter Inverter
Figure 5.1-1 Various types of inverting CMOS amplifiers.
Soluton
Given, I D = 10 µA , and Av = −100 V/V
a) Active-resistor load inverter
g
’
KN (W L )1 W1
Av ≅ − m1 → 100 = → L1 = 4546
g m2 K P’ (1)
Active area = 4546·1 + 5·1 = 4551 µm2
b) Current-source load inverter
g m1 2K N’
(W L )1 W1
Av = − → 100 = → L1 = 3.64
(g ds1 + g ds 2 ) I D (λ1 + λ 2 )2
Active area = 3.64·1 + 5·1 = 8.64 µm 2

c) Push-pull inverter
(g m1 + g m2 ) ’
2K N (W L )1 + 2 K P’ (1 / 1) W1
Av = − → 100 = → L1 = 1.55
(g ds1 + g ds 2 ) I D (λ1 + λ 2 )2
Active area = 1.55·1 + 5·1 = 4.55 µm 2
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-12

Problem 5.1-14
For the CMOS push-pull inverter shown, find the small signal VDD
voltage gain, Av, the output resistance, Rout, and the -3dB
frequency, f-3dB if ID = 200µA, W1 /L1 = W2/L2 = 5, Cgd1 = M2
Cgd2 = 5fF, Cbd1 = Cbd2 = 30fF, and CL = 10pF. vIN vOUT
Solution
The small-signal model for this problem is shown below. M1

CM iout VSS

+ Fig. P5.1-14
+
vin gm1vin rds1 gm2vin rds2 vout
Cout
- -
Fig. S5.1-14
Summing the currents at the output (ignoring the capacitors) gives,
gm1vin + gds1vout + gm2vin + gds2vout = 0
Solving for the voltage gain gives,

W1 W2 W1 W2
vout gm1+ gm2 2 L I D KN + 2 L I D KP K
L1 N + L 2 KP
1 2 2
= - gds1+ gds2 = - =-
vin I D ( λ N+ λ P ) ID λ N+ λ P

vout 2 5·110x10-6 + 5·50x10-6

vin = Av = - 200x10-6 0.05 + 0.04 = - (100)(0.436) = - 43.63V/V

∴ Av = - 43.63V/V
The output resistance is found by setting vin = 0 and solving for vout/iout.
Rout is simply expressed as,
1 1 1
Rout = g + g = = = 55.55kΩ
ds1 ds2 I (
D Nλ + λ P ) 200x10 -6 (0.05+0.04)

∴ Rout = 55.55kΩ
From Eq. (5.1-26) we can solve for the –3dB frequency as
gds1 + gds2 1
ω-3dB = ω1 = =
Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL Rout(Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL)

1 1
= ≈ = 1.8x106 rad/s
55.55x10-3( 5fF + 5fF + 30fF + 30fF + 10pF ) 55.55x103·10x10-12
∴ ω-3dB = 1.8x106 rad/s → f-3dB = 286.5 kHz
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-13

Problem 5.2-01
Use the parameters of Table 3.1-2 to calculate the small-signal, differential-in,
differential-out transconductance g md and voltage gain Av for the n-channel input,
differential amplifier when ISS = 100 µ A and W1/L1 = W2/L2 = W3/L3 = W4/L4 = 1
assuming that all channel lengths are equal and have a value of 1µm. Repeat if W1/L1 =
W2/L2 = 10W3/L3 = 10W4/L4 = 10.
Solution
Referring to Fig. 5.2-5 and given that

W  W  W  W 
a) = = = =1
 L 1  L  2  L  3  L  4

Differential-in differential-out transconductance is given by

W 
gmd = gm1 = gm 2 = K N' I = 104.8 µS
 L 1 SS

Small-signal voltage gain is given by

gm 2 2 gm 2
Av = = = 23.31 V/V
(gds2 + gds4 ) ISS (λ2 + λ4 )

W  W  W  W 
b) = = 10 = 10 = 10
 L 1  L  2  L 3  L 4

gmd = gm1 = gm 2 = 331.4 µS

gm 2
Av = = 36.82 V/V
(gds2 + gds4 )
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-14

Problem 5.2-02
Repeat the previous problem for the p-channel input, differential amplifier.
Solution
Referring to Fig. 5.2-7 and given that
W  W  W  W 
(a.) = = = =1
 L 1  L  2  L  3  L  4
Differential-in differential-out transconductance is given by

W 
gmd = gm1 = gm 2 = K P' I = 70.71 µS
 L 1 SS
Small-signal voltage gain is given by
gm 2 2 gm 2
Av = = = 15.7 V/V
(gds2 + gds4 ) ISS (λ2 + λ4 )
W  W  W  W 
(b.) = = 10 = 10 = 10
 L 1  L  2  L 3  L 4
gmd = gm1 = gm 2 = 223.6 µS
gm 2
Av = = 24.84 V/V
(gds2 + gds4 )
Problem 5.2-03
Develop the expressions for VIC(max) and VIC(min) for the p-channel input differential
amplifier of Fig. 5.2-7.
Solution
The maximum input common-mode input is given by
V IC (max) = VDD − (VT 1 + Vdsat1 + Vdsat 5 )

 I DD 2 I DD 
or, VIC (max) = VDD −  VT 1 + + 
 K P' (W L)1 K P' (W L) 5 

The minimum input common-mode input is given by

V IC (min) = VSS − VT 1 + VT 3 + Vdsat 3

I DD
or, VIC (min) = VSS − VT 1 + VT 3 +
K (W L) 3
'
N
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-15

Problem 5.2-04
Find the maximum input common mode voltage, v IC (max) and the minimum input
common mode voltage, vIC(min) of the n-channel input, differential amplifier of Fig. 5.2-
5. Assume all transistors have a W/L of 10µm/1µm, are in saturation and ISS = 10µA.
What is the input common mode voltage range for this amplifier?
Solution
The maximum input common-mode input is given by
V IC (max) = VDD + VT 1 − VT 3 − Vdsat 3

I SS
or, VIC (max) = VDD + VT 1 − VT 3 − = 4.86 V
K (W L) 3
'
P

The minimum input common-mode input is given by

V IC (min) = VSS + VT 1 + Vdsat1 + Vdsat 5

I SS 2 I SS
or, VIC (min) = VSS + VT 1 + + = 0.93 V
K (W L)1
'
N K N (W L) 5
'

So, the input common-mode range becomes

ICMR = VIC (max) − VIC (min) = 3.93 V

Problem 5.2-05
Find the small signal voltage gain, vo/vi, of the circuit in the previous problem if vin = v1
- v2. If a 10pF capacitor is connected to the output to ground, what is the -3dB frequency
for Vio(jω)/VIN(jω) in Hertz? (Neglect any device capacitance.)
Solution
Small-signal voltage gain is given by
gm 2 2 gm 2
Av = = = 233.1 V/V
(gds2 + gds4 ) ISS (λ2 + λ4 )
The –3 dB frequency is given by

f −3 dB ≅
(gds2 + gds4 ) = ISS (λ2 + λ4 ) = 7.16 kHz.
2πCL 4 πCL
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-16

Problem 5.2-06
For the CMOS differential amplifier of Fig. 5.2-5, find the small signal voltage gain,
vout/vin, and the output resistance, Rout, if ISS = 10µA, V DD = 2.5V and vin = vgs1-vgs2. If
the gates of M1 and M2 are connected together, find the minimum and maximum
common mode input voltage if all transistors must remain in saturation (ignore bulk
effects).
Solution
Small-signal model for calculations:
iout
+ vin -
+ + i3 +
vgs1 vgs2 vout
gm1vgs1 1 i3
rds1 rds3 gm3 gm2vgs2 rds2 rds4
- - -
Fig. S5.2-06
1 1
Rout = g + g = (0.04 + 0.05)5µA = 2.22 MΩ
ds2 ds4
gm1gm3rp1 
vout =  vgs1 − gm2vgs2Rout ≈ (gm1vgs1 – gm2vgs2)Rout = gm1Routvin
 1 + gm3rp1 
vout
∴ v = gm1Rout = gm2Rout , gm1= gm2 = 2·110·5·2) µS = 46.9 µS
in
vout
vin = 46.9µS·2.22MΩ = 104.1 V/V
Common mode input range:
 2·5 
Vicm(max) = VDD – VSG3 + VTN = 2.5 -  
50·2+0.7 + 0.7 = 2.5 - 0.3162 = 2.184 V
2·10  2·5 

Vicm(min) = 0+VDS5(sat)+VGS1= 110·2  110·2+0.7 = 0.3015+0.9132
= 1.2147 V
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-17

Problem 5.2-07
Find the value of the unloaded differential-transconductance gain, gmd, and the unloaded
differential-voltage gain, Av, for the p-channel input differential amplifier of Fig. 5.2-7
when ISS = 10 microamperes and ISS = 1 microampere. Use the transistor parameters of
Table 3.1-2.
Solution
Assuming all transistors have W/L = 1
a) Given, I SS = 10 µA

W  gmd 2 gmd
gmd = K P' I = 22.36 µS Av = = = 49.69 V/V
 L 1 SS (gds2 + gds4 ) ISS (λ2 + λ4 )
b) Given, I SS = 1 µA

W  gmd 2 gmd
gmd = K P' I = 7.07 µS Av = = = 157.11 V/V
 L 1 SS (gds2 + gds4 ) ISS (λ2 + λ4 )

Problem 5.2-08
What is the slew rate of the differential amplifier in the previous problem if a 100 pF
capacitor is attached to the output?
Solution
Slew rate can be given as
I
SR = SS
CL
For I SS = 10 µA and C L = 100 pF
I
SR = SS = 0.1 V/µs
CL
For I SS = 1 µA and C L = 100 pF
I SS
SR = = 0.01 V/µs
CL
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-18

Problem 5.2-09
Assume that the current mirror of Fig. 5.2-5 has an output current that is 5% larger than
the input current. Find the small signal common-mode voltage gain assuming that ISS is
100µA and the W/L ratios are 2µm/1µm for M1, M2 and M5 and 1µm/1µm for M3 and
M4.
Solution
Given that
I D 4 = (1.05) I D3 or, I D 2 = (1.05) I D1
This mismatch in currents in the differential input pair will result in an input offset
voltage.
Now, I D1 + I D 2 = I SS
So,
I D1 ≅ (0.49) I SS and I D 2 ≅ (0.51) I SS
To calculate the common-mode voltage gain, let us assume a small signal voltage
v s applied to both the gates of the differential input pair.
The small-signal output current iout is given by
iout = (i D 4 − i D 2 )
where,
 0.5 gds5 
iD 4 ≅  gm 4 v s
 gm 3 
i D 2 ≅ (0.5 g ds5 )v s
So,
g 
iout = (iD 4 − iD 2 ) = (0.5 gds5 ) m 4 − 1v s
 gm 3 
The output conductance can be given as
g out ≅ g ds 4 as M 2 and M 5 form a cascode structure.
Thus,
iout g g 
v out = ≅ ds5  m 4 − 1v s
gout 2 gds4  gm 3 
v out g g 
or, = ds5  m 4 − 1
vs 2 gds4  gm 3 
v out I SS ( λ5 )  I D 4 
or, =  − 1
vs I SS ( λ4 )  I D 3 
v out
or, = 0.02 V/V
vs
Thus, the small-signal common-mode gain is approximately 0.02 V/V
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-19

Problem 5.2-10
Use the parameters of Table 3.1-2 to calculate the differential-in-to-single-ended-output
voltage gain of Fig. 5.2-9. Assume that ISS is 50 microamperes.
Solution
Let, the aspect ratio of all the transistors be 1.

The small-signal differential-in single-ended out voltage gain is given by

g
Av = m1 =
K N'
W ( )
L 1

( )
'
= 0.74 V/V
2 gm 3 4KP W
L 3

Problem 5.2-11
Perform a small-signal analysis of Fig. 5.2-10 that does not ignore rds1. Compare your
results with Eq. (5.2-27).
Solution
Referring to Fig. 5.2-10
Applying KVL

( )
v ic − v gs1 = gm1v gs1 2 rds5 + 
(
 v o − v ic − v gs1 ) 2r
 ds 5
 rds1 
or, v gs1 {rds1 + 2rds5 (1 + g m1rds1 )}+ vo (2rds 5 ) = vic (rds1 + 2rds5 ) (1)

Also, applying KCL

−v o (
 v o − v ic − v gs1 
= gm1v gs1 + 
)

1 + r   rds1 
 gm 3 ds3 
{vic − vo (1 + g m3 rds1 )}
or, v gs1 = (2)
(1 + g m1rds1 )
Putting Eq. (2) in Eq. (1), and assuming g m1rds1 >> 1
{vic − vo (1 + g m3 rds1 )}
(2rds5 (1 + g m1rds1 ))+ vo (2rds5 ) = vic (rds1 + 2rds5 )
(1 + g m1rds1 )
or, − vo (g m3 rds1 )2rds5 = vic rds1
vo 1
or, =−
vic (g m3 2rds5 )
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-20

Problem 5.2-12
Find the expressions for the maximum and minimum input voltages, vG1(max) and
vG1(min) for the n-channel differential amplifier with enhancement loads shown in Fig.
5.2-9.
Solution
VG1 (min) = VT 1 + Vdsat1 + Vdsat 5

I SS 2 I SS
or, VG1 (min) = VT 1 + +
K N (W
’
L )1 K N (W L )5
’

VG1 (max) = VDD + VT 1 − VT 3 + Vdsat 3

I SS
or, VG1 (max) = VDD + VT 1 − VT 3 +
K P’ (W L )3
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-21

Problem 5.2-13
If all the devices in the differential amplifier of Fig. 5.2-9 are saturated, find the worst-
case input offset voltage, V O S , if |VTi| = 1 ± 0.01 volts and β i = 10-5 ± 5 × 10-7
amperes/volt2. Assume that
β1 = β2 = 10β3 = 10β4
and
∆ β1 ∆ β2 ∆ β3 ∆ β4
= = =
β1 β2 β3 β4
Carefully state any assumptions that you make in working this problem.
Solution
Referring to the figure
VGS1 = VT 1 + Vdsat1
2 I D1
or, VGS1 = VT 1 +
β1
VGS 2 = VT 2 + Vdsat 2
2I D 2
or, VGS 2 = VT 2 +
β2
The input-offset voltage can de defined as
VOS = VGS1 − VGS 2
2 I D1 2 I D1
or, VOS = VT 1 − VT 2 + −
β1 β2
Considering the transistors M 3 and M 4 , mismatches in these two transistors would
cause an offset voltage between the output nodes. But, if it is assumed that this offset
voltage between the output nodes is small as compared to the drain-to-source voltages of
the transistors M 1 and M 2 , then
V DS1 ≅ V DS 2
Thus, it is assumed here that
I D1 = I D 2 = I
So, the input-offset voltage becomes
2I 2I
VOS = VT 1 − VT 2 + −
β1 β2
Assuming I = 50 µA , the worst-case input offset voltage can be given by
 2(50 µ ) 2(50 µ ) 
VOS = (1.01 − 0.99) +  −
 0.95(10 µ ) 1.05(10 µ ) 
or, VOS(max) = 0.18 V
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-22

Problem 5.2-14
Repeat Example 5.2-1 for a p-channel input, differential amplifier.
Solution
The best way to do this problem is to use the equations for the n-channel, source-coupled
pair with opposite type transistor parameters and then subtract the result from 5V.
Eq. (5.2-15) gives
 2·50µA 
VIC(max) = 4 −  + 0.85 + 0.55 = 4 – 1.855 + 0.55 = 2.695 volts
 99µA/V 2·1 
Subtracting from 5V gives
VIC(min) =5 − 2.695 = 2.305 V
and Eq. (5.2-17) gives
 2·50µA 
VIC(min) = 0 + 0.2 +  +0.85 = 0.2 + 1.517 = 1.717 volts
 45µA/V 2·5 
Subtracting from 5 V gives,
VIC(max) = 5 − 1.717 = 3.282 V
Therefore, the worst-case input common-mode range is 0.978V with a nominal 5V power
supply.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-23

Problem 5.2-15
Five different CMOS differential amplifier circuits are shown in Fig. P5.12-15. Use the
intuitive approach of finding the small signal current caused by the application of a small
signal input, vin, and write by inspection the approximate small signal output resistance,
Rout, seen looking back into each amplifier and the approximate small signal, differential
voltage gain, vout/vin. Your answers should be in terms of gmi and gdsi, i = 1 through 8.
(If you have to work out the details by small signal model analysis, this problem will take
too much time.)
VDD

M7 M8 M7 M8 M7 M8 M7 M8 M7 M8

VBP
vOUT vOUT vOUT M5 M6 vOUT M5 M6 vOUT

M3 M4
M1 M1 M1 M1 M1
VBN
vIN M2 vIN M2 vIN M2 M2 M2

ISS ISS ISS ISS ISS

Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5

Figure P5.2-15
Solution
gm2
Assume gm1 = gm2 otherwise multiply the gain of circuits 1 and 2 by g .
m1+gm2
Circuit Rout vout/vin
1 gm1gm2 0.5gm2
1 gds2+gm8+gds8 =
(gm1+gm2)(gds8+gm8+gds8) gds2+gm8+gds8
1 gm1gm2 0.5gm2
2 gds2+gds8 =
(gm1+gm2)(gds2+gds8) gds2+gds8
1 gm1+gm2
3 gds2+gds8 2(gds2+gds8)

1 gm6 (gm1+gm2)˚gm6
4 =
gds6gds8 gds6gds8+gm6gds2 2(gm6gds2+gds6gds8)
gds2˚+ g
m6
gm4gm6 (gm1+gm2)gm4gm6
5 gds2gm6gds4˚+gm6gds4gds8 2(gds2gm6gds4˚+gm6gds4gds8)
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-24

Problem 5.2-16
If the equivalent input-noise voltage of each transistor of the differential amplifier of Fig.
5.2-5 is 1nV/ Hz find the equivalent input noise voltage for this amplifier if W 1/L1 =
W2/L2 = 2 µm/1 µ m, W3/L3 = W 4/L4 = 1 µ m/1 µm and I SS = 50 µ A. What is the
equivalent output noise current under these conditions?
Solution
From Equation. (5.2-39)
2
 gm 3  2
eeq = en1 + en 2 + 
2 2 2
 (en 3 + en24 )
 gm1 
  g 2 
or, eeq = 2en 1 +  m 3   = 2.455en2
2 2

  gm1  
Given
en = 1 nV / Hz
Thus,
eeq. = 1.567 nV/ Hz
The equivalent output noise current is given by
2 2 2
ito = gm1eeq

or, ito = 164 fA/ Hz

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-25

Problem 5.2-17
Use the small-signal model of the differential amplifier using a current mirror load given
in Fig. 5.2-8(a) and solve for the ac voltage at the sources of M1 and M2 when a
differential input signal, vid, is applied. What is the reason that this voltage is not zero?
Solution
Neglecting the current source i3 in the figure, let us assume that
v
v g1 = −v g 2 = id
2
Applying nodal analysis, we will get the following three equations

(g m1 + g ds1 )v s1 = g m1v g1 + (g m3 + g ds1 )v D3 (1)

(g m2 + g ds 2 )vs1 = g m2 v g 2 + (g ds 2 + g ds 4 )vout (2)
(g m1 + g m2 + g ds1 + g ds2 − g ds5 )v s1 = g m1v g1 + g m2 v g 2 + g ds1v D3 + g ds2 vout (3)
v
Now, assuming g m >> g ds , g m1 = g m 2 , g ds1 = g ds 2 , and v g1 = −v g 2 = id
2
g ds1v D3 + g ds 2 vout
v s1 =
(g m1 + g m2 + g ds1 + g ds 2 − g ds5 )
g v + g ds 2 v out
or, v s1 = ds1 D 3
(2 g m1 + 2 g ds1 − g ds5 )
Substituting from Equations (1) and (2), we get

 g 
gm10.25 − ds1 
 gm 3 
v s1 = v
  gm1   id
0.75 gm1 + gds12 − −g 
  gm 3  ds5 

The value of v s1 is non-zero because the loads (M3 and M4) seen by the input transistors
(M1 and M2) at their drains are different.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-26

Problem 5.2-18
The circuit shown Fig. P5.2-18 +1.5V
called a folded-current mirror
differential amplifier and is
useful for low values of power
supply. Assume that all W/L M9 M8 M6 M7 vout
values of each transistor is 100.
a.) Find the maximum input v1 v2
M1 M2
common mode voltage,
v IC (max) and the minimum M3 M4
input common mode voltage, 100µA M10 M5
v IC(min). Keep all transistors
in saturation for this problem.
b.) What is the input common
Fig. P5.2-18
mode voltage range, ICMR?
c.) Find the small signal voltage gain, vo/vin, if vin = v1 - v2.
d.) If a 10 pF capacitor is connected to the output to ground, what is the -3dB frequency
for Vo(jω)/Vin(jω) in Hertz? (Neglect any device capacitance.)
Solution
200
a.) v1(max) = VDD - VDS6(sat) + VTN = 1.5 - 50·100 + 0.7 = 1.5 – 0.2 + 0.7
∴ v1(max) = 2V

2·100  2·50 
v1(min) = 0 + VDS5(sat) + VGS1(50µA) =  
110·100 +  110·100 + 0.7
= 0.1348 + 0953 + 0.7 = 0.9302V ⇒ v1(min) = 0.9302V
b.) ICMR = v1(max) - v1(min) = 1.0698V
c.) Using intuitive analysis approach gives:
vin vin vin
id1 = gm1 2  ⇒ id3 = -gm1 2  ⇒ id4 =-gm1 2 
Also,
vin
id2 = -gm2 2  . ∴ vout = -Rout(id2 + id4)
1 vout gm1
However, Rout = rds2||rds4||rds7 = gds2+gds4+gds7 ⇒ vin = gds2+gds4+gds7
gm1 = 2·50·110·100 = 1049µS, g ds2 = gds4 = 0.04·50 = 2µS
and gds7 = 0.05·100 = 5µS
vout 1049
∴ vin = 7 = 149.8V/V
1 7x10-6
d.) ω-3dB = Rout10pF = 10x10-12 = 0.7x106 → ∴ f-3dB = 111.4kHz
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-27

Problem 5.2-19
Find an expression for the +1.5V
equivalent input noise voltage
of Fig. P5.2-18, veq2 , in terms
of the small signal model M9 M8 M6 M7 vout
parameters and the individual
v1 v2
equivalent input noise voltages, M1 M2
vni2 , of each of the
M3 M4
transistors (i = 1 through 7). M10 M5
100µA
Assume M1 and M2, M3 and
M4, and M6 and M7 are
matched.
Fig. P5.2-18
Solution
Equivalent noise circuit:
VDD
en62

* *
M6 en72 M7 vout
en12
v1 v1
* M1 M2 *
en22
en32 en42
M3 * * M4

VSS S99FES6
2 2 2 2 2 2 2
e out = (gm12 e n1+ gm22 e n2+ gm32 e n3+ gm42 e n4+ gm52 e n6+ gm62 e n7)Rout2
2
2 gm12
2 e out 2 2 2 gm12 2 2
e eq = = e n1 + e n2 + g  ( e n3 + e n4)+g  ( e n6+ e n7)
(gm1Rout)2  m3  m6
If M1 through M2 are matched then gm1 = gm3 and we get

2 2 gm12 2
e eq = 4 e n1 + 2g  e n6
 m6
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-28

Problem 5.2-20
Find the small signal transfer VDD
function V3(s)/Vin(s) of Fig. P5.2-
20, where Vin = V1-V2, for the M5 M6 M7 M8
capacitors shown in algebraic
form (in terms of the small signal v3 C3 v4
C2
model parameters and C1
capacitance). Evaluate the low- C4
frequency gain and all zeros and v1 M2 M3 v2
M1 M4
poles if I = 200µA and C1 = C2 =
C3 = C4 = 1pF. Let all W/L = 10. I
Solution VBias M9
Small-signal model:L
ΣiA = 0: (Gout = gds1 + gds5)
Fig. P5.2-20
0.5gm1vin + sC1v3
+ Goutv3 + gm5v6 = 0
 0.5gm3 
ΣiB = 0: sC2v6 + gm6v6 = 0.5gm3vin = 0 → v6 =  sC + g  v6
 2 m6

A B
gm1vin gm3vin
C1 v3 C2 1
v6
2 rds1 rds5 2
gm5v6 gm6 rds3 rds6
From the first equation we get,
 0.5gm3 
v3(sC1 + Gout) + gm5 sC + g  vin + 0.5gm1vin = 0
 2 m6
Solving for v3 gives,
v3  -0.5gm1 sC2 + gm5 + gm6 v3 -gm1
vin = sC1 + Gout sC2 + gm6  When s → 0, =
vin gds1 + gds5

gmN = 2·50µA·110x10 -6·10 = 331.6µS, gmP= 2·50µA·50x10 -6·10 = 223.6µS,

1 1
rdsN = -6 = 0.5MΩ, and rdsP = = 0.4MΩ
0.04·50x10 0.05·50x10-6
v3
∴ vin = - gmN·Rout = -(331.6)(0.5||0.4) = -73.69 V/V
Poles are at,
-1 -1 -gm6 -223.6µS
p1 = R C = = -4.5x106rad/s & p2 = C = 1pF = -223.6 x106 rad/s
out 1 22.22kΩ·1pF 2
-(gm5+ gm6) -(223.6µS + 223.6µS)
A zero is at, z1 = C2 = 1pF = -447.2 x106 rad/s
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-29

Problem 5.2-21
For the differential-in, differential-out amplifier of Fig. 5.2-13, assume that all W/L
values are equal and that each transistor has approximately the same current flowing
through it. If all transistors are in the saturation region, find an algebraic expression for
the voltage gain, vout/vin, and the differential output resistance, Rout, where vout = v3-v4
and vin = v1-v2. Rout is the resistance seen between the output terminals.
Solution
v out (v3 − v 4 ) g m1
= =−
vin (v1 − v2 ) (g ds1 + g ds3 )
vout 2K N’ W
( )
L1
or, =−
vin I BIAS (λ1 + λ3 )2

Considering differential output voltage swing, the output resistance can be given by
1 1
Rout = +
(g ds1 + g ds3 ) (g ds2 + g ds 4 )
2 2
or, Rout = =
(g ds1 + g ds3 ) I BIAS (λ1 + λ3 )
Problem 5.2-22
Derive the maximum and minimum input common mode voltage for Fig. 5.2-15
assuming all transistors remain in saturation. What is the minimum power supply
voltage, VDD, that will give zero common input voltage range?
Solution
The minimum input common-mode voltage is given by
V IC (min) = VT 1 + Vdsat1 + Vdsat 5
The maximum input common-mode voltage is given by
V IC (max) = VDD + VT 1 − Vdsat 3

Assuming all the Vdsat voltages to be the same, the minimum supply voltage for zero
input common mode can be given by
V IC (max) − VIC (min) = 0

or, (VDD + VT1 − Vdsat 3 )− (VT1 + Vdsat1 + Vdsat 5 ) = 0

or, VDD ≈ 3Vds(sat)
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-30

Problem 5.2-23
Find the slew rate, SR, of the differential amplifier shown VDD
where the output is differential (ignore common-mode
stability problems). Repeat this analysis if the two current
0.5ISS 0.5ISS
sources, 0.5ISS, are replaced by resistors of RL. CL
Solution + -
a.) Slew rate of the differential output amplifier with vOUT
M1 M2
constant current source loads.
Under large signal swing conditions, the maximum
current that can be carried by each of the two transistors ISS
M 1 and M 2 is I SS . Due to the presence of constant
current sources as loads, the maximum charging or VSS
discharging current through C L would be 0.5I SS . Thus,
Fig. P5.2-23
the slew rate can be given by
ISS
SR = 2C
L
b.) Slew rate of the differential output amplifier with resistive loads.
In presence of resistive loads, the maximum charging or discharging current through
C L would be I SS . Thus, the slew rate can be given by
ISS
SR = C
L
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-31

Problem 5.2-24
If all the devices in the differential amplifier shown in Fig. 5.2-5 are saturated, find the
worst-case input-offset voltage VOS using the parameters of Table 3.1-2. Assume that
10(W4/L4 = 10(W 3/L3) = W2/L2 = W1/L1 = 10 µ m/10 µ m. State and justify any
assumptions used in working this problem.
Solution
The offset voltage between the input terminals is given by
Vos = VGS1 − VGS 2

The drain current equations are

β
I D1 = 1 (VGS1 − VT 1 )2
2
β
I D 2 = 2 (VGS 2 − VT 2 )2
2
2 I D1 2I D 2
or, Vos = VGS1 − VGS 2 = (VT 2 − VT 1 )+ −
β1 β2

Mismatches would cause ID1 ≠ ID2. But, to simplify the problem, it can be assumed that
I D1 = I D 2 = 0.5I SS . Under this assumption and considering the mismatches in VT and
β only, the worst-case input-offset voltage (from Table 3.1-2) can be given by
I SS I SS
Vos = 0.3 + −
0.9 β 1.1β
Assuming
I SS = 100 µA
100 µ 100µ
Vos = 0.3 + − = 0.48 V
0.9(110 µ )(10 / 10 ) 1.1(110 µ )(10 / 10 )
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-32

Problem 5.3-01
Calculate the small-signal voltage gain for the cascode 5V
amplifier of Fig. 5.3-2 assuming that the dc value of vIN is M3 W3 2µm
=
selected to keep all transistors in saturation. Compare this L3 1µm
value with the slope of the voltage transfer function given 2.3V ID
in this figure. M2 +
Solution W2 = 2µm
L2 1µm
The small-signal voltage gain can be approximated as 3.4V vOUT
g M1
Av ≅ − m1 W1 = 2µm
g ds 3 + L1 1µm
vIN
’
2K N (W L )1 - -
or, Av ≅ − Fig. P5.3-2
I D3λ32

ID is calculated from M3 as,

KP'W2
ID = 2L (VSG3-|VTP|)2 = 50·(2.7-0.7)2 µA = 200µA
2

2KN'(W1/L1) 2·50·2
∴ Av = = 200·0.05·0.05 = -20 V/V
IDλN2
From the transfer characteristics, the small-signal gain is approximately -10 V/V.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-33

Problem 5.3-02
Show how to derive Eq. (5.3-6) from Eqs. (5.3-3) through (5.3-5). Hint: Assume that
VGG2-VT2 is greater than vDS1 and express Eq. (5.3-4) as iD2 ≈ β2(VGG2-VT2)vDS2. Solve
for vOUT as vDS1 + vDS2 and simplify accordingly.
Solution
From Eqs. (5.3-3) through (5.3-5)
I D1 ≅ β1 (VDD − VT 1 )Vds1

I D 2 ≅ β 2 (VGG 2 − Vds1 − VT 2 )(Vout − Vds1 )

I D3 = 0.5β 3 (VDD − VGG 3 − VT 3 )
2

Assuming, when Vin is taken to V DD , the magnitudes of Vds1 and Vout are small.
Equating I D1 = I D 3
β1 (VDD − VT 1 )Vds1 = 0.5β 3 (VDD − VGG 3 − VT 3 )
2

0.5β 3 (VDD − VGG 3 − VT 3 )

2
or, Vds1 = (1)
β1 (VDD − VT 1 )
Equating I D1 = I D 2
β1 (VDD − VT 1 )Vds1 = β 2 (VGG 2 − Vds1 − VT 2 )(Vout − Vds1 )
or, (VDD − VT1 )Vds1 = (VGG 2 − VT 2 )(Vout − Vds1 )
Vout (VGG 2 − VT 2 )
or, Vds1 = (2)
(VDD + VGG 2 − VT1 − VT 2 )
From Eqs. (1) and (2), the minimum output voltage is given by

β3 2 
Vout (min) =
2 β1
(VDD − VGG 3 − VT 3  ) (
V
1
− V
+
V
1
) (
− V

)
 DD T 1 GG 2 T2 
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-34

Problem 5.2-03
Redrive Eq. (5.3-6) accounting for the channel modulation where pertinent.
Solution
From Eqs. (5.3-3) through (5.3-5)
I D1 ≅ β1 (VDD − VT 1 )Vds1

I D 2 ≅ β 2 (VGG 2 − Vds1 − VT 2 )(Vout − Vds1 )

I D3 = 0.5β 3 (VDD − VGG 3 − VT 3 ) (1 + λ3 (VDD − Vout ))

2

Assuming, when Vin is taken to V DD , the magnitudes of Vds1 and Vout are small.

Equating I D1 = I D 3
β1 (VDD − VT 1 )Vds1 = 0.5β 3 (VDD − VGG 3 − VT 3 ) (1 + λ3 (VDD − Vout ))
2

0.5β 3 (VDD − VGG 3 − VT 3 ) (1 + λ3 (VDD − Vout ))

2
or, Vds1 = (1)
β1 (V DD − VT 1 )
Equating I D1 = I D 2
β1 (VDD − VT 1 )Vds1 = β 2 (VGG 2 − Vds1 − VT 2 )(Vout − Vds1 )
or, (VDD − VT1 )Vds1 = (VGG 2 − VT 2 )(Vout − Vds1 )
Vout (VGG 2 − VT 2 )
or, Vds1 = (2)
(VDD + VGG 2 − VT1 − VT 2 )
From Eqs. (1) and (2), assuming V DD − Vout ≅ V DD , the minimum output voltage is
given by
β3 2 
Vout (min) = (
2 β1
VDD − VGG 3 − VT 3  ) (
V
1
− V
+
V
1
− V) ( 1 + λ3VDD
)( )
 DD T 1 GG 2 T2 
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-35

Problem 5.3-04
Show that the small signal input resistance looking in the source VDD
of M2 of the cascode amplifier of Fig. 5.3-1 is equal to rds if the
simple current source, M3 is replaced by a cascode current
source. VGG4
M4
Solution
The effective resistance of the cascoded PMOS transistors is VGG3
M3
represented by RD3 and it is given by
RD3
RD3 ≅ g m3 rds 3 rds 4
Referring to the small-signal model in the figure Vout


v1 = gm 2v x +
(
v x − v1 ) R VGG2
M2
 D3
rds 2
  RS2
(1 + g m2 rds2 )RD3 Vin
or, v1 = v M1
(R D3 + rds 2 ) x
(1)
Now
(v x − v1 ) vx VSS
ix = g m2 v x + +
rds 2 rds1

i x = ( g m2 + g ds 2 + g ds1 )v x − g ds 2 v1

i x ≅ g m 2 v x − g ds 2 v1

Replacing v1 from Eq. (1) and assuming RD3 >> rds 2

ix ≅ v x
[g m2 (RD3 + rds 2 )− g m2 R D3 ]
RD 3
v R D3
or, RS 2 = x ≅
ix g m 2 rds 2
g r r
or, RS 2 = m3 ds 3 ds 4 = rds
g m 2 rds 2
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-36

Problem 5.3-05
Show how by adding a dc current source from VDD VDD
to the drain of M1 in Fig. 5.3-1 that the small-
signal voltage gain can be increased. Derive an
expression similar to that of Eq. (11) in terms of VGG3
M3
ID1 and ID4 where ID4 is the current of the added
dc current source. If ID2 = 10 µA, what value for ID4
Vout
this current source would increase the voltage gain
by a factor of 10. How is the output resistance
affected? VGG2
Solution M2

Assuming all the transistors are in saturation

Vin
I D1 = I D 2 + I D 4 M1
g
Av ≅ − m1
g ds 3
Fig. S5.3-05
’ W 
 (I D 2 + I D 4 )
VSS
2K N 
 L 1
or, Av ≅ −
2 2
ID 2λ3

I
or, Av ≅ Avo 1 + D 4
I D2

’ W 
2K N  
L 1
where, Avo = − is the gain in absence of the current source I D 4
I D 2 λ23

Av I D4
Thus, = 1+
Avo I D2
The small-signal voltage gain can be increased by making I D 4 >> I D 2 . In order to
achieve
Av I
= 10 → 10 = 1 + D 4
Avo I D2
or, I D 4 = 99 I D 2 = 990 µA
The output resistance can be given by
Rout ≅ [g m2 rds 2 rds1 || rds3 ]

The value of rds1 decreases due to increased current through M 1 , thus decreasing the
overall output resistance.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-37

Problem 5.3-06
Assume that the dc current in each transistor in +5V
Fig. P5.3-6 is 100µA. If all transistor have a W/L
of 10µm/1µm, find the small signal voltage gain, VP1 M3
vout/vin and the small signal output resistance,
M2
Rout, if all transistors are in the saturated region. VP2 M4 Rout
Solution vout
This circuit is a folded cascode amplifier. The VN2 M5
small signal analysis is best done by the
schematic analysis approach. In words, v i n vin M1 VN1 M6
creates a current flowing into the drain of M1 of
gm1vin. This current flows through M4 from
drain to source back around to M1. The output
voltage is simply this current times Rout . The Fig. P5.3-6
details are:
vout = -gm1Routvin
Rout ≈ [rds6(gm5rds5)]||[(rds1||rds2||rds3)(gm4rds4)]
The various small signal parameters are:
gmN = 2·110·100·10 = 469µS, gmP = 2·50·100·10 = 316.2µS
25V 20V
rdsN = 100µA = 0.25MΩ and rdsP = 100µA = 0.2MΩ

∴ Rout ≈ 29.31MΩ||(0.0667MΩ)(63.2) = 29.31MΩ||4.216MΩ = 3.686MΩ

Rout = 3.686MΩ

vout
vin = -(469µS)(3.686MΩ) = -1,729 V/V
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-38

Problem 5.3-07
Six versions of a cascode amplifier are shown below. Assume that K'N = 2K'P, λP = 2λN,
all W/L ratios of all devices are equal, and that all bias currents in each device are equal.
Identify which circuit or circuits have the following characteristics: (a.) highest small
signal voltage gain, (b.) lowest small signal voltage gain, (c.) the highest output
resistance, (d.) the lowest output resistance, (e.) the lowest power dissipation, (f.) the
highest Vout(max), (g.) the lowest Vout (max), (h.) the highest Vout (min), (i.) the lowest
Vout (min), and (j.) the highest -3dB frequency.
VDD
VBP1
vIN vIN vIN

VBP2
vOUT vOUT vOUT vOUT vOUT vOUT

VBN2

vIN vIN vIN

VBN1

Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6

Figure P5.3-7
Solution
Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6
gm gmN gmP gmN gmP 2 gmN 2 gmP
Rout ≈ rdsP ≈ rdsN R* R* ≈ rdsP ≈ rdsN

R* = (gmP·rdsP2)||(gmN·rdsN2) Note that gmN = 2 gmP and rdsN = 2rdsP

e.) Circuit 3 has the highest gain.
f.) Circuit 1 has the lowest gain.
g.) Circuits 3 and 4 have the highest output resistance.
h.) Circuits 1 and 5 have the lowest output resistance.
i.) Circuits 1-4 have the lowest power dissipation.
j.) Circuits 1 and 5 have the highest Vout(max).
k.) Circuit 4 has the worst (lowest) Vout(max).
l.) Circuits 2 and 6 have the best (lowest) Vout(min).
m.) Circuit 3 has the worst (highest) Vout(min).
n.) Circuits 1 and 5 have the highest –3dB frequency because of lowest Rout.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-39

Problem 5.3-08
All W/L ratios of each transistor in the VDD
amplifier shown in Fig. P5.3-8 are 10µm/1µm.
Find the numerical value of the small signal
voltage gain, vout/vin, and the output resistance, M8 M4
Rout.
Solution
The output resistance can be given as M7 M3 Rout
vout
Rout ≅ [g m 2 rds 2 rds1 || g m3 rds3 rds 4 ]
100µA

M6 M2
Neglecting body effects
vin
g m1 = g m 2 = 469 µS M1
M5
g m3 = g m 4 = 316 µS

g ds1 = g ds 2 = 4 µS Figure P5.3-8

g ds3 = g ds 4 = 5 µS

Thus, Rout ≅ [29.31M || 12.64 M ]

or, Rout ≈ 8.838 MΩ

The small-signal voltage gain is given as

v out
= −gm1Rout = -41.42 V/V
v in
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-40

Problem 5.3-09
Use the Miller simplification described in Appendix A on the capacitor C2 of Fig. 5.3-
5(b) and derive an expression for the pole, p1, assuming that the reactance of C2 at the
frequency of interest is greater than R3. Compare your result with Eq. (5.3-32).
Vout

R1 C1 V1 C3 Av R3
C2
gm1V1 (Av-1)
Vin/Rs (1-Av)C2

sC2<<R3
Vout

V1
R1 C3 R3
C1 gm1V1
Vin/Rs (1-Av)C2

Fig. S5.3-09

Solution
Given that in the frequency of interest, the reactance of C2 is greater than 1 /R3
1
or, 2πfC2 >>
R3
Referring to the figure
Vin ( s)
V1 ( s) = (1)
1 
RS
 R1 ( )
+ s C1 + (1 + Av )C2

where, Av = gm1R3

−gm1V1 ( s) −gm1V1 ( s)
Also, Vo ( s) = ≅
1  sC3
 + sC3 
 R3 
−gm1 Vin ( s)
or, Vo ( s) = (2)
1  1 
 + sC3  RS
 R3 
  R1
(
+ s C1 + (1 + Av )C2 )

The dominant pole in Eq. (2) can be expressed as
−1 −1
p1 = ≅
R1 ( Av C2 + C1 ) R1 ( Av C2 )

-1
or, p1 = g
m1 1R3C2
R
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-41

Problem 5.3-10
Consider the current-source load inverter of Fig. 5.1-5 and the simple cascode amplifier
of Fig. 5.3-1. If the W/L ratio for M2 is 1 µm/1 µm and for M1 is 3 µm/1 µm of Fig. 5.1-
5, and W3/L3 = 1 µm/1 µm, W2/L2 = W1/L1 = 3 µm/1 µm for Fig. 5.3-1, compare the
minimum output-voltage swing, vOUT(min) of both amplifiers if VGG2 = 0 V and VGG3 =
2.5 V when VDD = −VSS = 5 V.
Solution
a) Current source load inverter
When Vin = V DD , it can be assumed that M 1 operates in the triode region and
M 2 is in saturation. Thus,
β1 (VDD − VSS − VT 1 )(Vout (min) − VSS ) = 0.5β 2 (VSG 2 − VT 2 )
2

0.5 β 2 (VSG 2 − VT 2 )
2
or, Vout (min) = + VSS
β1 (VDD − VSS − VT 1 )
Assuming, VSG 2 = 5 V
Vout(min) = -4.85 V
b) Simple cascode amplifier
Vout (min) = VSS + Vdsat1 + Vdsat 2
2 I D1 2 I D2
or, Vout (min) = VSS + +
K N (W L )1
’
K N (W L )2
’

Now,
β3
I D3 = (VDD − VGG3 − VT 3 )2 = 81 µA
2
Thus, Vout(min) = -3.6 V
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-42

Problem 5.3-11
Use nodal analysis techniques on the cascode amplifier of Fig. 5.3-6(b) to find vout/vin.
Verify the result with Eq. (5.3-37) of Sec. 5.3.
Solution
Nodal analysis of cascode amplifier
Applying KCL
g m1vin + g ds1v1 + g m 2 v1 + g mbs 2 v1 = g ds 2 (vout − v1 )

or, g m1vin + ( g ds1 + g m 2 + g mbs 2 + g ds 2 )v1 = g ds 2 vout

(g ds 2 vout − g m1vin )
or, v1 = (1)
( g ds1 + g m 2 + g mbs 2 + g ds 2 )

Again, applying KCL

g ds 4 v 4 + g ds3 (v 4 − vout )+ g m3v 4 + g mbs 3v 4 = 0

g ds3
or, v4 = v (2)
(g m3 + g ds3 + g ds4 + g mbs3 ) out
Also,
(g m3 + g mbs3 )v4 + g ds3 (v4 − vout )+ (g m2 + g mbs2 )v1 + g ds 2 (v1 − vout ) = 0

or, (g m3 + g mbs3 + g ds3 )v4 + (g m2 + g mbs2 + g ds 2 )v1 = (g ds3 + g ds4 )vout (3)

Using Eqs. (1) through (3) and neglecting body effect, it can be shown that

− g m1 g m 2 g m3
Av =
(g m3 g ds1 g ds 2 + g m2 g ds3 g ds 4 )
− g m1
or, Av =
 g ds1 g ds 2 g ds 3 g ds 4 
 + 
 g m2 g m3 

− 2 K1’ (W L )1
or, Av = Eq. (5.3-37)
 
 λ1λ 2 λ3 λ 4 
ID + 
 2 K 2’ (W L ) 2 K 3’ (W L )3 
 2 
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-43

Problem 5.3-12
Find the numerical value of the small signal VDD
voltage gain, vout/vin, for the circuit of Fig.
M6 M5 M4 M3
P5.3-12. Assume that all devices are saturated
and use the parameters of Table 3.1-2. Assume 4/1 4/1 40/1
4/1
that the dc voltage drop across M7 keeps M1 in vout
saturation. M2
Solution 4/1
M7
I D 3 = I D 2 = 20 µA
1/1
vin M1
I D 3 = 220 µA 20µA 4/1

Now,
Fig. P5.3-12
gm1 = 440 µS and rds1 = 113.64 kΩ

gm 2 = 132.67 µS and rds2 = 1.25 kΩ

rds3 = 1 MΩ

Thus,

Rout = [rds3 || gm 2 rds2 rds1 ]

or, Rout = [1M || 18.8 M ] = 950 kΩ

So,

Av = −gm1Rout = -418 V/V

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-44

Problem 5.3-13
A cascoded differential amplifier is shown in VDD
Fig. P5.3-13.
(a) Assume all transistors are in saturation M7
M12 M8
and find an algebraic expression for the small I7 I8
signal voltage gain, vout/vin. M5
(b) Sketch how would you implement VBias? M11 M6
vout
(Use a minimum number of transistors.)
(c.) Suppose that I7+I8≠ I9. What would be M4
M3
the effect on this circuit and how would you I + M1 +
solve it? Show a schematic of your solution. vin VBias
- M2 -
You should have roughly the same gain and
the same output resistance. M9
Solution M10 I9
a ) The effective transconductance is
given by VSS
g Fig. P5.3-13
gm ,eff = m1
2
The output resistance of the cascoded output is given by
 
 1 
Rout =
 gds2 gds4 gds6 gds8 
+
 gm 4 gm 6 
Thus, the small-signal voltage gain is given by

 
 0.5 gm1 
Av =
 gds2 gds4 gds6 gds8 
+
 gm 4 gm 6 

b) The magnitude of VBIAS should be at least VGS + Vdsat . One way to implement VBIAS
is shown in Fig. 6.5-1(b) of the text.

c) If the currents were not equal, the voltages at the drains of M3-M5 and M4-M6
will near VDD or near the sources of M1 and M2. Either, M5-M8 or M1-M4 will
not be saturated. The best way to solve this problem is through the use of
common mode feedback. This is illustrated in Fig. 5.2-15 of the text.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-45

Problem 5.3-14
Design a cascode CMOS amplifier using Fig. 5.3-7 for the following specifications. VDD
= 5V, Pdiss ≤ 0.5mW, |Av| ≥ 100V/V, vOUT(max) = 3.5V, vOUT(min) = 1.5V, and slew
rate of greater than 5V/µs for a 5pF capacitor load. Verify your design by simulation.
Solution
1.) The slew rate should be at least 5 V/µs driving a 5 pF load. So, the load current
should be at least 25 µA.
Let,
I D 3 = I D 2 = I D1 = 25 µA
2.) The maximum output voltage swing should be at least 3.5 V
Let, Vdsat 3 = 1.5 V
W  2ID 3
= = 0.44
 L  3 K P' Vdsat
2
3
So, let us choose
W  W 
= =1
 L 3  L 4

3.) The small-signal voltage gain should be at least 100

Av ≅ −gm1rds3
 W  ( Av λ3 ) I D1
2

or, = = 2.84
 L 1 2K N'
So, let us choose
W 
=3
 L 1
Vdsat1 = 0.39 V
4.) The minimum output voltage swing should be greater than 1.5 V
Vout (min) = Vdsat1 + Vdsat 2
or, Vdsat 2 = Vout (min) − Vdsat1 = 1.11 V
W  2I
or, = ' D22 = 0.37
 L  2 K NVdsat 2
So, let us choose
W 
=1
 L 2
5.) The bias voltage VGG 2 can be calculated as
VGG 2 = VT 1 + Vdsat1 + Vdsat 2 = 1.76 V
6.) The power dissipation is given by
Pdiss = I D 3VDD = 0.125 mW
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-46

Problem 5.4-01
Assume that io = Ai(ip-in) of the current i2 R2
amplifier shown in Fig. P5.4-1. Find vout/vin
i1 R in
and compare with Eq. (5.4-3). 1 io
Solution ip Ai vo
Referring to the figure, i p = 0 . vs
Current
So, ( )
io = Ai i p − in = − Aiin Amplifier
Figure P5.4-1
Now, v in = i1R1
v o = −i2 R2
v i 
or, v o = (i1 − in ) R2 → v o =  in + o R2
 R1 Ai 
  −v o   R2
 R2  
v o =  in +
v vo R1
or, R → = Eq. (5.4-3)
 R1 Ai  2 v in 1 + 1 
   Ai 
Problem 5.4-02
The simple current mirror of Fig. 5.4-3 is to be used as a current amplifier. If the W/L of
M1 is 1µm/1µm, design the W/L ratio of M2 to give a gain of 10. If the value of I 1 is
100µA, find the input and output resistance assuming the current sources I1 and I2 are
ideal. What is the actual value of the current gain when the input current is 50µA?
Solution
The current gain can be expressed as
(W L)2
Ai =
(W L)1
For Ai = 10 , W 2 = 10 µm and L2 = 1 µm.
If I1 = 100 µA, then I 2 = 1000 µA.
The input resistance is
1
Rin = = 6.74 kΩ
gm1
The output resistance is
1
Rout = = 25 kΩ
λN I D 2
When I1 = 50 µA, then I 2 = 500 µA and the current gain ( Ai ) is still 10.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-47

Problem 5.4-03
VDD VDD
The capacitances of M1 and M2 in Fig. P.4-3
are Cgs1=Cgs2=20fF, Cgd1=Cgd2 =5fF, and
100µA 100µA
Cbd1=Cbd2=10fF. Find the low frequency iout
current gain, iout/iin, the input resistance seen
M1 M2
by iin, the output resistance looking into the iin 5µm
1µm RL=0
drain of M2, and the -3dB frequency in Hz. 5µm/1µm

Solution
Fig. P5.4-3
+
iin gm1 gds1 V1 C1 iout
gm1V1
-
S99E2S3

(a.) Small-signal model is shown.

Note that
C1=Cbd1 + Cgs2 + Cgd2 + Cgs1 = 55fF,
W1
gm1=gm2 = 2KN· L I1 = 2·110·5·100 = 332µS
1
and
gds1 = λNI1 = 0.04·100µA = 4µS
 iin˚ 
The current gain is, iout = gm2g +g +sC 
 m1 ds1 1
The low frequency current gain is
gm2 332
Ai(0) = g +g = 336 = 0.988⇒ Ai(0) = 0.988
m1 ds1
1 1
Rin = g +g = 336µS = 2.796kΩ ⇒ Rin = 2796Ω
m1 ds1
Rout = 1/gds2 = 1/gds1 = 250kΩ ⇒ Rout = 250kΩ
gm1+gds1 332µS+4µS
ω-3dB = C1 = 55fF = 6.11x109 ⇒ f-3dB = 973MHz
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-48

Problem 5.4-04
VDD
Derive an expression for the small-signal
input resistance of the current amplifier
of Fig. 5.4-5(a). Assume that the current I1
sink, I3, has a small signal resistance of I2
rds4 in your derivation.
Solution ix
M3 VGG3
Referring to the figure
v s3 = v x Vx M1 M2
g m3 rds4
v g1 = v d 3 ≅ v
(g ds3 + g ds 4 ) x
i x = id1 + id 3

or, i x = g m1v g1 + g m3v x

g m3
or, i x = g m1 v +g v
(g ds3 + g ds4 ) x m3 x
v (g + g ds 4 )
or, Rin = x ≅ ds3
ix g m1 g m3
Problem 5.4-05
Show how to make the current accuracy of Fig. 5.4-5(a) better by modifying the circuit
so that VDS1 = VDS2.
Solution
Referring to the figure, M3-M6 form a VDD
differential amplifier. If it is assumed that the small-
signal gain of this differential amplifier is large
M5 M6
enough, then the bias voltages at the gates of M3 and
I2
M4 would almost be equal (because in presence of I1
large gain, the differential input ports would act as null
M3 M4
ports). Thus, the drain bias voltages of M1 and M2
would almost be identical causing very good
mirroring.
M1 M2
It is also important to note that the bias voltage
at the drain of M4 could be very large as gate bias I3
voltages for M1 and M2. One can use a PMOS
differential amplifier in place of the shown NMOS
differential amplifier to overcome this problem.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-49

Problem 5.4-06
Show how to use the improved high-swing current mirror of Sec. 4.4 to implement Fig.
5.4-7(a). Design the current amplifier so that the input resistance is 1kΩ and the dc bias
current flowing into the input is 100µA (when no input current signal is applied) and the
dc voltage at the input is 1.0V.
Solution
The high-swing cascode current VDD
mirror, constitut-ing the
transistors M1 through M4, is
I I
shown in the figure. The overall i1 i1-i2 2I iout
figure shows a differential current
amplifier. To design the high- i2 i2
swing cascode current mirror, it is i1-i2
M3 M4 M7 M8
desired that
Rin = 1 kΩ
VBias =
or, g m1 = 1 µS M1 M2 VT + M5 M6
2VON
W  W 
or, = = 45.5
 L 1  L  2 Fig. S5.4-06
Let us assume
W  W 
= = 45.5
 L 3  L 4
Then, ignoring bulk effects
VBIAS = VT 3 + Vdsat 3 + Vdsat1 = 1.1 V
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-50

Problem 5.4-07
Show how to use the regulated cascode mirror of Sec. 4.4 to implement a single-ended
input current amplifier. Calculate an algebraic expression for the small signal input and
output resistance of your current amplifier.
Solution
iout
ix

vg3 M3 +
vgs3=(-gm1rds1)vs3 gm3vgs3 rds3
iin
M1 vs3 -
vs3
vx
M4 M2
rds2

Referring to the figure, the current gain of the regulated cascode mirror can be expressed
as
i (W L)2
Ai = out ≅
iin (W L) 4
The input resistance is given by
1
Rin =
gm 4
The output resistance can be calculated as follows:
v g 3 = −( gm1rds1 )v s3 (1)

Now, ix = gm 3v gs3 +
(v x − v s3 )
rds3

or, ix = −gm 3 ( gm1rds1 )v s3 +

(v x − v s3 ) (2)
rds3
Also, v s3 = ix rds2 (3)
Using Eqs. (2) and (3), it can be shown that
v x = ix ( gm1rds1gm 3 rds3 rds2 )
vx
or, Rout = = ( gm1rds1gm 3 rds3 rds2 )
ix
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-51

Problem 5.4-08
VDD
Find the exact expression for the small signal
input resistance of the circuit shown when the
output is short-circuited. Assume all transistors I I I iout
have identical W/L ratios, are in saturation and
ignore the bulk effects. Simplify your expression
by assuming that gm=100gds and that all M4
transistors are identical. Sketch a plot of iout as a iin
function of iin.
Solution
Rin M3
A small signal model for this problem is: M1 M2
gm4 vgs4
Rin
D2=G3=S4 D4 Figure P5.4-8
+ rds4
-
+ vgs4
vt v rds2 D3=G4
it gs3 +

- rds3
- gm3 vgs3

S2=S3
it = (gds2+gds4)vt - gm4vgs4

But, vgs4 = -gm3rds3vgs3 - vt

and
vgs3 = vt
∴ it = (gds2+gds4)vt + gm4(1+gm3rds3)vt
Thus, Rin is
vt 1 1
Rin = it = gds2+gds4+gm4 + gm3gm4rds3 ≈ gm3gm4rds3
Sketching iout as a function of iin:
i out
Note that iD4 = I + iout and iD4 + iin = iD2 = iD1 = I
1
Therefore, I + iout = I - iin ⇒ iout = - iin 1 i in
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-52

Problem 5.4-09
VDD VDD
Find the exact small signal expression for Rin for
the circuit in Fig. P5.4-9. Assume VDC causes the Vb2 M5
current flow through M1 and M2 to be identical.
Assume M1 and M2 are identical transistors and M1 M2
that the small signal rds of M5 can be ignored (do Vb1
+
not neglect rds1 and rds2). VDC
Solution Rin M3 -
+
The small-signal model is shown below. vin M4
We may write that, -
vin = vd1 = (iin – gm1vgs1)rds1 + (iin+ gm2vgs2) rds2 Fig. 5.4-9
but vgs1 = - vs1 and vgs2 = vg2 – vs2

gm1vgs1 gm2vgs2
iin
G2 = D3 = D4
D1 rds1 rds2
+ +
vin vd1 vg2
S1=S2
- G1=D2 gm2vd1 rds3 gm4vd1 rds4 -
Fig. S5.4-9

∴ vin = iin rds1 + gm1vs1rds1 + iin rds2 + gm2vg2rds2 - gm2vs2rds2

 gm3+ gm4 
= iin rds1 + iin rds2 + gm2vg2rds2 = iin (rds1 + rds2) - gm2rds2 g + g  vin
 ds3 ds4

(rds1 + rds2)iin vin (rds1 + rds2)

∴ vin = gm2rds2(gm3+ gm4) → R in = iin = gm2rds2(gm3+ gm4)
1+ gds3 + gds4 1 + gds3 + gds4

rds1 + rds2
or Rin = 1 + g
m2 ds2(gm3+ gm4)rds3||rds4
r
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-53

+2V
Problem 5.4-10
A CMOS current amplifier is shown. 50µA
10/1
Find the small signal values of the
current gain, Ai = iout/iin, input M5 M7
resistance, Rin, and output resistance, 100/1
Rin 10/1 10/1
Rout. For Rout, assume that gds2/gm6 is M1 M3 iout
equal to gds1/gm5. Use the parameters
M2 M4 Rout
of Table 3.1-3. iin
10/1 10/1
Solution 100/1
Since this is a new circuit, use the M6 M8
small signal model approach. The 10/1 50µA
model for this problem is given below.
iout = -(gm7v1 + gm8v2) -2V S98FEP6

gm7i1 gm8i2 gm7 gm7 iout

=- g - g = - g (i1+i2) = g iin → Ai = i = -10
m5 m6 m5 m5 in
gm2vin
i2 v2
iin rds2 gm1vin iout
+ i1 v1
rds1
vin 1 1
gm5 gm6 gm7v1 gm8v2 rds7 rds8
-
S98FES6
1 1 1
Rout = g +g = (500µA)(0.04+0.05) = 45µS = 22.2kΩ
ds7 ds8
Rin:
iin = gm1vin + gm2vin + gds1(vin-v1) + gds2(vin-v2)
gds1i1 gds2i2 gds1
= (gm1+gm2+gds1+gds2)vin - g - g = (gm1+gm2+gds1+gds2)vin - g iin
m5 m6 m5
gds1
vin 1 + gm5
∴ Rin = i = g +g +g +g , gm1 = 2KN·10·50 = 331.7µS, gds1= 2µS
in m1 m2 ds1 ds2
gm2 = 2KP·10·50 = 223.6µS, gds1= 2.5µS, and gm5 = gm2
1 + 0.0112
Thus, Rin = 331.7+223.6+2+2.5 = 1.8kΩ
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-54

Problem 5.4-11
Find the exact algebraic expression (ignoring bulk effects) VDD
for the following characteristics of the amplifier shown.
Express your answers in terms of gm’s and rds’s in the form
of the ratio of two polynomials. M6 M3
Rout
(a.) The small signal voltage gain, Av = vout/vin., and current
iout
vout
gain, Ai = iout/iin. 100µA
(b.) The small signal input resistance, Rin. M2
M5 Rin
∴ The small signal output resistance, Rout. iin
Solution vin
(a.) Small-signal model is shown below. Summing currents M4 M1
at the output node gives:
gm2vin + gds2(vin-vout) = gds3vout
Figure P5.4-11
vout gm2+gds2 rds3+gm2rds2rds3
or vin = gds2+gds3 = rds2+rds3

gm2vgs2 gm2vin
R
iin iout iin i iout

+ + + +
vgs2 = -vin
vin rds1 rds2 rds3 vout vin rds1 rds2 rds3 vout
- - - -
S98E2S3

(b.) The input resistance is best done by finding R and putting it in parallel with rds1.

vin rds2+rds3
vin = (i-gm2vin)rds2 + irds3 → R = i = 1+g r
m2 ds2

 rds2+rds3  rds1(rds2+rds3)
∴ Rin = rds1||R = rds1||1+g r  → Rin = r +r +r +g r r
 m2 ds2 ds1 ds2 ds3 m2 ds2 ds1

rds2rds3
(c.) Rout = rds2||rds3 = r +r
ds2 ds3
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-55

Problem 5.4-12
Find the exact expression for the small signal input VDD
resistance of the circuit shown. Assume all
transistors have identical W/L ratios, are in
saturation and ignore the bulk effects. Simplify I I I
iout
your expression by assuming that gm=100gds and
that all transistors are identical. Sketch a plot of
iout as a function of iin. iin M4
Solutions
A small signal model for this problem is: Rin M3
gm4 vgs4
M1 M2
Rin
D2=G3=S4 D4
+ r ds4
-
+ vgs4 Figure P5.4-12
vt v rds2 D3=G4
it gs3 +

- rds3
- gm3 vgs3

S2=S3
it = (gds2+gds4)vt - gm4vgs4
But, vgs4 = -gm3rds3vgs3 - vt

and
vgs3 = vt

∴ it = (gds2+gds4)vt + gm4(1+gm3rds3)vt

Thus, Rin is

vt 1 1
Rin = it = gds2+gds4+gm4 + gm3gm4rds3 ≈ gm3gm4rds3

Sketching iout as a function of iin:

Note that iD4 = I + iout and iD4 + iin = iD2 = iD1 = I i out

Therefore, I + iout = I - iin ⇒ iout = - iin 1

1 i in
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-56

Problem 5.5-01
Use the values of Table 3.1-2 and design the W/L ratios of M1 and M2 of Fig. 5.5-1 so
that a voltage swing of ±3 volts and a slew rate of 5 volts/µs is achieved if RL = 10 kΩ
and CL = 1 nF. Assume that VDD = −VSS = 5 volts and VGG2 = 2 volts.
Solution
K P'  W 
ID 2 = (
V − VGG 2 − VT 2
2  L  2 DD
) 2

For positive swing of the output voltage, the slew rate should be at least +5 V/µs.
ID 2
SR =
CL
Thus, I out = I D 2 = SR(CL ) = 5 mA
W  2ID 2 W 
Now, = → ≅ 38/1
'
P DD (
 L 2 K V − V − V
GG 2 T2 ) 2
 L 2

Also, for the output voltage to swing to +3 V, the load current into RL will be 0.3 mA.
Since I D 2 is greater than 0.3 mA, the output voltage would be greater than +3 V.
For negative output voltage swing
I out = SR(CL ) = 5 mA
I D1 = −I out + I D 2 = 10 mA
W  2 I D1 W 
or, = ' → = 2.1 ≅ 3/1
 L 1 K (V − V − V ) 2  L 1
N DD SS T1

For Vout (min) = −3 V, I out = −0.3 mA. Since I D1 > −I out + I D 2 , the output will be able to
swing down to –3 V.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-57

Problem 5.5-02
Find the W/L of M1 for the source follower of Fig. 5.5-3a when VDD = −VSS = 5 V, VOUT
= 1 V, and W2/L2 = 1 that will source 1 mA of output current. Use the parameters of
Table 3.1-2.
Solution
Given, Vout = 1 V and VSS = −5 V
So, VGS 2 = 6 V
K N'  W 
ID 2 =

2 L 2 
(VGS 2 − VT 2 )
2
→ I D 2 = 1.55 mA

Thus, I D1 = I D 2 + I out = 2.55 mA

Due to body effects, the threshold voltage of M1 can be given by
VT 1 = VT 0 + γ 1 Vout − VSS = 1.68 V
W  2 I D1
Now, = ' = 8.6/1
 L 1 K (V − V − V ) 2
N DD out T1

Problem 5.5-03
Find the small-signal voltage gain and output resistance of the source follower of Fig.
5.5-3b. Assume that VDD = −VSS = 5 V, VOUT = 1 V, ID = 50 µA, and the W/L ratios of
both M1 and M2 are 20 µm/10 µm. Use the parameters of Table 3.1-2 where pertinent.
Solution
The small-signal voltage gain is given by
gm1
Av =
(gm1 + gds1 + gds2 )
VT 1 = VT 0 + γ 1 Vout − VSS → VT1 = 1.68 V

W 
gm1 = 2K N' I → gm1 = 148 µS
 L 1 D1
gds1 + gds2 = 4.5 µS
∴ Av = 0.943 V/V
The output resistance is given by
1
Rout = = 6.37 kΩ
(gm1 + gds1 + gds2 )
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-58

Problem 5.5-04
An output amplifier is shown. Assume that vIN can +2.5V
vary from -2.5V to +2.5V. Let KP’ = 50µA/V 2, VTP
= -0.7V, and λP = 0.05V-1. Ignore bulk effects. 200µA
a.) Find the maximum value of vOUT, vOUT(max). vOUT
b.) Find the minimum value of vOUT, vOUT(min). vIN 300/1 50pF 10kΩ
SR+
c.) Find the positive slew rate, when vOUT = 0V
in volts/microseconds. -2.5V
d.) Find the negative slew rate, SR- when vOUT = 0V
in volts/microseconds.
e.) Find the small signal output resistance (excluding the 10kΩ resistor) when vOUT =
0V.
Solution
∴ When vIN = +2.5V, the transistor is shut off and vOUT(max) = 200µA·10k Ω =
+2V
∴ When vIN = -2.5V, the transistor is in saturation (drain = gate) and the minimum
output voltage under steady-state is,
50·300 
vOUT = -10kΩ(ID-200µA) = -10kΩ  2 (vOUT+2.5-0.7)2 - 200µA 
vOUT = -75(vOUT+1.8)2 +2 → vOUT2+3.6133vOUT + 3.21333 = 0
3.61333 (3.61333)2 - 4·3.21333
∴ vOUT = - 2 ± 2 = -1.80667 ± 0.22519
It can be shown that the correct choice is vOUT(min) = -1.80667 + 0.22519 = -1.5815V
200µA
c.) The positive slew rate is SR+ = 50pF = +4V/µs → SR+ = +4V/µs
d.) The negative slew rate is found as follows. With vOUT = 0V, the drain current is
ID = 7.5mA/V2(2.5-0.7)2 = 24.3mA
Therefore, the sourcing current is 24.3mA-0.2mA = 24.1mA which gives a negative slew
24.1mA
rate of SR- = 50pF = - 482V/µs → SR- = - 482V/µs
e.) The output resistance, Rout, is approximately equal to 1/gm. Therefore,
1 L 1
Rout ≈ g = 2KPIDW = 2·50·200·300 = 408.2Ω → Rout ≈ 408Ω
m
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-59

Problem 5.5-05
An output amplifier is shown. Assume that
+2.5V
vIN can vary from -2.5V to +2.5V. Ignore
bulk effects. Use the parameters shown
below. vIN 300µm
a.) Find the maximum value of vOUT, 1µm
vOUT(max). vOUT
b.) Find the minimum value of vOUT,
200µA 50pF 10kΩ
vOUT(min).
c.) Find the positive slew rate, SR+ when
vOUT = 0V in volts/microseconds. -2.5V
d.) Find the negative slew rate, SR- when Figure P5.5-5
vOUT = 0V in volts/microseconds.
e.) Find the small signal output resistance when vOUT = 0V.

Solution

(a.) When vIN = 2.5V, the transistor shuts off and vOUT(max) = 200µA·10kΩ = +2V

(b.) Assume vIN = -2.5V. Therefore, the transistor is in saturation and the minimum
output voltage under steady-state is,
110x10-6·300 
vOUT = -10kΩ(ID-200µA) = -10kΩ  2 (v OUT +2.5-0.7) 2-200µA 

or
vOUT = -165(vOUT+1.8)2 + 2V → vOUT2 + 3.6061 vOUT + 3.228 = 0
3.6061 (3.6061)2 - 4·3.228
∴ vOUT = - 2 ± 2 = -1.8030 ± 0.1516
It can be shown that the correct choice is vOUT = -1.8030 + 0.1516 = -1.6514V
Thus vOUT(min) = -1.6514V

200µA
(c.) The positive slew rate is SR+ = 50pF = +4V/µs
(d.) The negative slew rate is found as follows. With vOUT = 0V, the drain current is
110x10-6·300
ID = 2 (2.5-0.7)2 = 53.46mA
Therefore, the sourcing current is 53.46mA - 0.2mA = 53.44mA which gives a negative
53.44mA
slew rate of SR- = - 50pF = 1069V/µs
(e.) The output resistance, Rout, is approximately equal to 1/gm. Therefore,
1 L 106
Rout = g = 2KIDW = = 275.24Ω
m 2·110·300·200
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-60

Problem 5.5-06
For the circuit shown in Fig. P5.5-6, find the small signal voltage +5V
gain, vout/vin and the small signal output resistance, Rout. Assume M1 10/1
that the dc value of vOUT is 0V and that the dc current through vin -5V
M1 and M2 is 200µA. vout
Solution M2 Rout
-3V 10/1
(Unfortunately the gate-source voltage is given on the schematic
which causes a conflict with the problem statement of 200µA of -5V
current. We will use the 200µA in the solution.)
Fig. P5.5-6
The small-signal model for this problem is shown below.

iout
+ vgs1 -
+
rds1 rds2 vout
gm1vgs1 gmb1vbs1 -
Fig. S5.5-6
663.3µS(0.4)
gm1 = 2·110·200·10 µS = 663.3µS, gmb1 = = 55.57µS,
2 0.7 + 5
gds1 = gds2 = 0.04·200µA = 8µS
Summing currents at the output,
vout(gds1 + gds2) = gm1vgs1 + gmb1vbs1 = gm1vin - gm1vout - gmb1vout

vout gm1 663.3

(e.) v = g + g + g + g = 663.3 + 55.57 + 8 + 8 = 0.9026 V/V
in m1 mb1 ds1 ds2

vout 1 1
Rout = i =g +g + g + g = 663.3 + 55.57 + 8 + 8 = 1361Ω
out m1 mb1 ds1 ds2
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-61

Problem 5.5-07
Develop an expression for the efficiency of the source follower of Fig. 5.5-3b in terms of
the maximum symmetrical peak-output voltage swing. Ignore the effects of the bulk-
source voltage. What is the maximum possible efficiency?
Solution
Efficiency (η) is expressed as
 Vout ( peak ) 2 
 
PRL  2 RL 
η max = =
Psup ply (VDD − VSS )IQ
The maximum output voltage swing is
Vout (max) ≅ VDD − VT 1
The minimum output voltage swing is
Vout (min) ≅ VSS
Assuming symmetrical maximum positive and negative output swings
Vout ( peak ) ≅ VDD − VT 1
The quiescent current can be expressed as
(V (max) − Vout (min))
IQ = out
2 RL

or,
(V − VSS − VT 1)
IQ = DD
2 RL
Thus,
 Vout ( peak ) 2 
 
η max =
 2 RL 
=
(VDD − VT 1 )
2

(VDD − VSS )IQ (VDD − VSS )(VDD − VSS − VT 1)

Assuming VDD = −VSS = 5 V gives ηmax ≈ 20%
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-62

Problem 5.5-08
Find the pole and zero location of the source followers of Fig. 5.5-3a and Fig. 5.5-3b if
Cgs1 = Cgd2 = 5fF and Cbs1 = Cbd2 = 30fF and CL = 1 pF. Assume the device parameters
of Table 3.1-2, ID = 100 µA, W1/L1 = W2/L2 = 10 µm/10 µm, and VSB = 5 volts.
Solution

Cgd1
+
gm1vgs
vgs Cgs1 rds1
-
vin
vout
CL
RL2=(gm2+gds2+gL)-1

a.) Referring to the figure

The location of the zero of the follower is given by
−g
z = m1 = -14.9 GHz
Cgs1
The location of the pole of the follower is given by
−( gm1 + gm 2 + gds1 + gds2 + gL )
p= = -140.8 MHz
(Cgs1 + Cgs2 + Cbd 1 + Cbd 2 + CL )
b.) Referring to the figure
The location of the zero of the follower is given by
−g
z = m1 = -14.9 GHz
Cgs1
The location of the pole of the follower is given by
−( gm1 + gds1 + gds2 + gL )
p= = -71.1 MHz
(Cgs1 + Cgs 2 + Cbd 1 + Cbd 2 + CL )
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-63

Problem 5.5-09
Six versions of a source follower are shown below. Assume that K'N = 2K'P, λP = 2λN,
all W/L ratios of all devices are equal, and that all bias currents in each device are equal.
Neglect bulk effects in this problem and assume no external load resistor. Identify which
circuit or circuits have the following characteristics: (a.) highest small-signal voltage
gain, (b.) lowest small-signal voltage gain, (c.) the highest output resistance, (d.) the
lowest output resistance, (e.) the highest vout(max) and (f.) the lowest vout(max).
VDD
vin M1 M2 vin M1 M2 vin M1 VBP M2

vout vout vout vout vout vout

M2 vin M1 vin M2 vin M1
VBN
M2 M1 VSS
Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6
FS02E1P1
Solution
(a.) and (b.) - Voltage gain. Small signal model: + +
vout gm vin GL vout
The voltage gain is found as: vin = gm+GL g v g v
- m in m out -
where GL is the load conductance. Therefore we get:
Circuit 1 2 3 4 5 6
vout gmN gmP gmN gmP gmN gmP
vin gmN+gmN gmP+gmP gmN+gmP gmP+gmN gmN+gdsN+gdsP gmP+gdsN+gdsP
But gmN = 2 gmP and gdsN = 0.5gdsP, therefore
Circuit 1 2 3 4 5 6
vout 1 1 0.5858 0.4142 gmP gmP
vin 2 2 gmP+(gdsP+gdsN)/ 2 gmP+gdsP+gdsN
Thus, circuit 5 has the highest gain and circuit 4 the lowest gain
(c.) and (d.) - Output resistance.
The denominators of the first table show the following:
Ckt.6 has the highest output resistance and Ckt. 1 the lowest output resistance.
(e.) Assuming no current has to be provided by the output, circuits 2, 4, and 6 can pull
the output to VDD. ∴ Circuits 2, 4 and 6 have the highest output swing.
(f.) Assuming no current has to be provided by the output, circuits 1, 3, and 5 can pull
the output to ground. ∴ Circuits 1, 3 and 5 have lowest output swing.
Summary
(a.) Ckt. 5 has the highest voltage gain (d.) Ckt. 1 has the lowest output resistance
(b.) Ckt. 4 has the lowest voltage gain (e.) Ckts. 2,4 and 6 have the highest output
(c.) Ckt. 6 has the highest output resistance (f.) Ckts. 1,3 and 5 have the lowest output
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-64

Problem 5.5-10
Show that a class B, push-pull amplifier has a VDD
maximum efficiency of 78.5% for a sinusoidal
signal. M1
Solution
VBias VSS
Referring to the figure, assuming there is no iOUT
v
cross-over distortion, the efficiency can be given IN V vOUT
Bias
by
RL
2 M2 VDD
Vout ( peak )
2 RL
η= VSS
 V ( peak )  Fig. S5.5-10A
(VDD − VSS ) out 
 πRL 
vin
For maximum efficiency, it can be assumed
that the output swing is symmetrical and the
peak output voltage can be given by
t

Vout ( peak ) = VDD = −VSS

2
VDD
vout
2 RL
Thus, η = vout(peak)
V 2 
(VDD − VSS ) DD 
 πRL  t

π
or, η= = 78.5%
4 id1

vout(peak)/RL

id2

-vout(peak)/RL
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-65

Problem 5.5-11
Assume the parameters of Table 3.1-2 are valid VDD
for the transistors of Fig. 5.5-5a. Design VBias so
M1
that M1 and M2 are working in class-B
operation, i.e., M1 starts to turn on when M2 VBias VSS
starts to turn off.
vIN iOUT
Solution VBias vOUT
VGS1 = (Vin + VBIAS − Vout )
RL
M2 VDD
VGS 2 = (Vin − VBIAS − Vout )
VSS Fig. S5.5-10A
In Class B operation, when M1 starts to turn on
and M 2 starts to turn off, the drain currents can be written as

I D1 = I D 2 + I out

K N'  W  K' W 
or,
2  L 1
(VGS1 − VT 1 ) = P
2
V − VT 2
2  L  2 SG 2
( ) 2
+
Vout
RL

Assuming, when Vin = 0 , Vout = 0 , we get

K N'  W  K' W 
2  L 1
(VBIAS − VT 1 ) = P
2
V − VT 2
2  L  2 BIAS
( ) 2

 VBIAS − VT 1  K P'  W   L 
or,  =
 VBIAS − VT 2  K N'  L  2  W 1

 K P'  W   L  
VT 1 − K N  L  2  W 1
' VT 2 
or, VBIAS = 
 K P'  W   L  
1 − K N'  L  2  W 1 

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-66

Problem 5.5-12
Find an expression for the maximum and minimum output voltage swing for Fig. 5.5-5a.
Solution
To calculate the maximum output voltage swing, it can be assumed that the input is taken
to VDD . Thus,

VGS1 − VT 1 = (VDD + VBIAS − Vout (max) − VT 1 )

and, VDS1 = (VDD − Vout (max))

So, VDS1 − (VGS1 − VT 1 ) = (VBIAS − VT 1 )

Thus, if VBIAS ≥ VT 1, VDS1 ≥ (VGS1 − VT 1 ) and M1 will be in saturation.

Now, I D1 = I L

K N'  W  V (max)
or,

2 L 1 
(VDD + VBIAS − Vout (max) − VT 1 ) = out
2

RL

or, Vout (max) = (VDD + VBIAS − VT 1 ) + Y

1 1 2(VDD + VBIAS − VT 1 )
where, Y = − +
RL K (W L)1
'
N (R K (W L) )
L
'
N 1
2
(R K (W L) )
L
'
N 1

To calculate the minimum output voltage swing

I D 2 = −I L

K P'  W 
or, (
V − VBIAS − Vout (min) + VT 2
2  L  2 SS
) 2
=−
Vout (min)
RL

or, (
Vout (min) = VSS − VBIAS + VT 2 − Z )

where, Z =
1
−
1
−
(
2 VSS − VBIAS + VT 2 )
RL K P (W L) 2
'
(R K (W L) )
L
'
P 2
2
(R K (W L) )
L
'
P 2
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-67

Problem 5.5-13
Repeat the previous problem for Fig. VDD
5.5-8.
Solution M2
Assuming M 2 operate in triode region VTR2 iOUT
when Vin = VSS , the maximum output vIN vOUT
voltage swing can be calculated as VTR1
follows:
M1CL RL
I D 2 = I out

or,
Figure 5.5-8 Push-pull inverting CMOS amplifier.

W 
K P'
 L 2
( ) V (max)
VSS − VDD + VTR 2 + VT 2 (Vout (max) − VDD ) = out
RL

VDD
or, Vout (max) =
  
  1 
1 +  '  W  
(
  K P  L  RL VSS − VDD + VTR 2 + VT 2 ) 

 2

Assuming M1 operate in triode region when Vin = VDD , the minimum output voltage
swing can be calculated as follows:

I D1 = −I out

W  −V (min)
or, K N'
 L 1
( −VSS + VDD − VTR1 − VT 1 )(Vout (min) − VSS ) = out
RL

VSS
or, Vout (min) =
  
  1 
1 +
  ' W  
  K N  L  RL ( −VSS + VDD − VTR1 − VT 1 ) 
 1 
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-68

Problem 5.5-14
Given the push-pull inverting CMOS amplifier shown in Fig. 5.5-14, show how short-
circuit protection can be added to this amplifier. Note that R1 could be replaced with an
active load if desired.
Solution
VDD

ISC
M9
VSS
VDD

M7 M8
M3

Vout VSS
VBIAS

VDD
M2
Vin
M1
M5 M6
VSS

M4
ISC

VSS

The current source I SC in the figure represents the short circuit current whose value can
be set as desired. The current through the transistors M2 and M3 need to be regulated for
short circuit protection. The currents carried by M2 and M3 are mirrored into M4 and M9
respectively. When the current tends to increase in M2, the current in M4 would also
increase. This would tend to increase the voltage at the drain of M5, but it will decrease
the current in M5. Since the current carried by M4 and M5 are same, the gate bias of M4
as well as M2 cannot increase beyond a point where they both carry the maximum limit
of the current as set by the short circuit current source. Similarly, the diode-connected
transistor M9 would limit the gate bias of M3, thus limiting the output sinking current.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-69

Problem 5.5-15
If R1 = R2 of Fig. 5.5-12, find an expression for the small-signal output resistance Rout.
Repeat including the influence of RL on the output resistance.
Solution
VDD
R1
v g1 = v g 2 = v
(R1 + R2 ) x
or, v g1 = v g 2 = 0.5v x
id2
id 1 = 0.5 gm1v x
R1 R2 ix
and, id 2 = 0.5 gm 2v x

Now, ix = id 1 + id 2 R1
Vx id1 Vx
(R1+R2)
or, ix = 0.5( gm1 + gm 2 )v x

So, the output resistance becomes

VSS
v 2
Rout = x =
ix ( gm1 + gm 2 )

In presence of load ( RL ) , the output resistance will become

 2 
Rout =   || [RL ]
 ( gm1 + gm 2 ) 

The presence of the load resistance ( RL ) will tend to decrease the output resistance.
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-70

Problem 5.5-16
Develop a table that expresses the dependence of the small-signal voltage gain, output
resistance, and the dominant pole as a function of dc drain current for the differential
amplifier of Fig. 5.2-1, the cascode amplifier of Fig. 5.3-1, the high-output-resistance
cascode of Fig. 5.3-6, the inverter of Fig. 5.5-1, and the source follower of Fig. 5.5-3b.
Solution

Differential Cascode High-Gain Inverting Source

Amplifier Amplifier Cascode Amplifer Follower
Amp.
VDD VDD VDD VDD
VDD
M4 M1
M3 M4 M3 vIN
VGG4 M2 VSS
iOUT
vout VGG3 vOUT
M3 VGG2 ID
+ vOUT
Circuit M1 M2 M2
VGG3 VGG2
M2

+ vo VSS
vi VGG2 vIN
- M2 Fig. 5.5-3(b)
vout Rout M1
M5
VGG2
VBias +
vin M1 vin M1
FigS5.2-05 - -
Figure 5.1-1
Figure 5.3-1 Fig. 5.3-6(a)

KN'W See Eq. (5.3- KN'W Error!

Av 2 2KN'W1 -2
37)
λΝ+λP 2IDL1 - λΝ+λP 2IDL1
L1IDλP2
Gain ∝ ID-1

Rout 1 1 1 1 1
∝I ∝I ∝ -1.5 ∝I ∝
D D ID D ID

|p1| ∝ ID ∝ ID ∝ ID1.5 ∝ ID ∝ ID0.5

CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-71

Problem 5.6-01
Propose an implementation of the VCCS of Fig. 5.6-2(b).
Solution
VDD

M3 M4
io

M1 M2
+
vi
-
M5
VBias

FigS5.6-01

Problem 5.6-02
Propose an implementation of the VCVS of Fig. 5.6-3(b).
Solution
VDD

M3 M4

M6
vo
M1 M2
+
vi
-
M5
M7
VBias

FigS5.6-02
CMOS Analog Circuit Design (2nd Ed.) – Homework Solutions Page 5-72

Problem 5.6-03
Propose an implementation of the CCCS of Fig. 5.6-4(b).
Solution
VDD VDD VDD

I 2I I
i1 io

i2 i2
i1-i2
M1 M2 M3 M4

Fig. S5.6-03

Problem 5.6-04
Propose an implementation of the CCVS of Fig. 5.6-5(b).
Solution
VDD VDD VDD VDD

I 2I I
i1
M6
i2 i2 vo
i1-i2
M1 M2 M3 M4
M7
VBias

Fig. S5.6-04