Comparing Constraint Behavior to Determine Equivalency

TAU 2011
Sonia Singhal Loa Mize Subramanyam Sripada Szu-Tsung Cheng Cho Moon

Synopsys 2011

Constraints
Communicate design requirements and intent to implementation and analysis tools
set_input_delay 2.75 -clock CLK1 -setup [get_ports in1] create_clock name CLKA period 10 edges {0 5 10} [get_port clka] create_clock name CLKB period 50 edges {0 20 50} [get_port clkb] set_output_delay 1.5 clock CLK1 setup [get_ports out1] set_multicycle_path 2 -from [get_pins ff1/CP - to [get_pins ff2/D] set_false_path -from CLKA to CLKB set_false_path -from CLKB to CLKA

MCP 2

Constraint file size can be more than a few gigabytes

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Motivation
Pair-wise comparison not enough
Constraints in different forms can have the same effect
compressed vs. non-compressed constraints
set_false_path from A to Z set_false_path from B to Z vs. set_false_path from {A B} to Z

- set_false_path, set_case_analysis, set_disable_timing, set_clock_group

- Different syntax and representation - Different propagation effects on the netlist - Similar effect (disable) on the design

Constraints change form during the flow

Implementation and Analysis tools Experts know which form has potential benefits in runtime and faster timing closure

Synopsys 2011

Motivation
Constraints overlap and override
inv

rA
and rB

rX

rY

set_multicyle_path 3 \ through [get_pins inv/Z] set_multicycle_path 2 \ -through [get_pins and/Z]

Behavior Not Equivalent

set_multicycle_path 3 \ from [get_pins rA/CP] set_multicycle_path 2 \ through [get_pins and/Z]

Partially overridden, partially invalid constraints along with constraint precedence cannot be matched simply by comparing the netlist objects of the constraints
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Motivation
Netlist optimizations 2 netlists, same constraint-set
u1 rA u2 rB rY
?

u1 rX rA u3 rB rY rX

set_false_path from rB through u1/Z

set_false_path

from rB through u1/Z

Netlist optimizations have led to bad chips despite no changes in logical functionality and constraints There is a strong need to compare constraint behaviors (effects of constraints on designs)
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Timing relationships
Constraint representation for a set of paths
Clk rA and Clk Clk rX
create_clock period 10 name Clk [get_ports Clk} set_multicyle_path 2 through [get_pins inv/Z] set_false_path -through [get_pins and/B]

rB

Clk

rY

Timing Timing start-point end-point * rX/D

Launch clock Clk(r)

Capture clock Clk(r)

Min/ Max/ Rise/ Fall All

State MCP(2)

rA rB

rY/D rY/D

Clk(r) Clk(r)

Clk(r) Clk(r)

All All

MCP(2) FP

We create a minimal set of Timing Relationships necessary to describe the design and its constraints.
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Constraint Comparison Algorithm

Three Pass Approach

Compares the timing relationships of a set of paths across 2 netlist-constraint sets using a multi-pass gradual refinement method:
Pass 1: Fast method to detect mismatches of all paths reaching an endpoint. Pass 2: Main method to detect matches/mismatches for all paths between a startpoint-endpoint pair. Pass 3: Detailed method to remove remaining potential mismatches involving reconvergence points
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Pass 1
Compare the effect of constraints on timing path endpoints between 2 netlist/constraint pairs
Check same state for each endpoint timing relationship
Value Exception state - None - False - Cycle relationship - set_min_delay/set_max_delay value Key - Launch clock and clock edge - Timing Endpoint - Capture clock and clock edge - Endpoint data rise/fall - Min and Max path

Fast - Single bread-first traversal on netlist. Only endpoints with multiple matching timing relationships need further analysis

Synopsys 2011

Pass 1
Example
inv1 Clk rA inv2 Clk rX
First constraint set set_false_path from [get_pins rA/CP] set_false_path from [get_pins rB/CP] set_multicycle_path 2 from [get_pins rC/CP] Second constraint set set_false_path from [get_pins rA/CP] set_multicyle_path 2 from [get_pins rB/CP] set_false_path from [get_pins rC/CP]
Min/Max/ Rise/ Fall All All All 1st sets state 2nd sets state Pass1 Result

Clk

rB
and

Clk

rY

Clk
Timing start-point * * *

rC
Timing endpoint rX/D rY/D rZ/D

Clk
Launch Clock Clk(r) Clk(r) Clk(r)

rZ
Capture Clock Clk(r) Clk(r) Clk(r)

FP FP Match FP MCP Mis-match FP, MCP (2) FP, MCP (2) Needs further analysis

Synopsys 2011

Pass2
Compare the effect of constraints on timing path between startpoint-endpoint pairs across 2 netlist/constraint pairs
Check same state for each startpoint-endpoint pairs timing relationship
Value Exception state - None - False - Cycle relationship - set_min_delay/set_max_delay value Key -Timing Startpoint - Launch clock and clock edge - Startpoint data rise/fall - Timing Endpoint - Capture clock and clock edge - Endpoint data rise/fall - min and max path

Each inconclusive endpoint left over from Pass1 is analyzed Data gathered for all startpoints to the endpoint to be analyzed and cleared before proceeding to next endpoint Highly parallelizable
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Pass 2
Example
inv2
Clk rB and Clk rC Clk rZ Clk rY
First constraint set set_false_path from [get_pins rB/CP] set_multicycle_path 2 from [get_pins rC/CP] Second constraint set

set_multicyle_path 2 from [get_pins rB/CP] set_false_path from [get_pins rC/CP]

Timing startpoint rB/CP rC/CP

Synopsys 2011

Timing endpoint rZ/D rZ/D

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Launch clock

Clk(r) Clk(r)

Capture Min/ 1st sets clock Max/ state Rise/ Fall Clk(r) All FP Clk(r) All

2nd sets state

Result

MCP (2) MCP (2) FP

Mismatch Mismatch

Pass 3
Compare multiple timing relationships due to reconvergent points
First constraint set

mux rA rB

set_multicycle_path 2 through mux/A

Second constraint set set_multicycle_path 2 -through mux/B

Timing startpoint rA/CP rA/CP

Timing endpoint rB/D rB/D

Reconvergent Points mux/A mux/B

1st Set State MCP(2) Cycle(1)

2nd Set State

Result

Cycle (1) MCP(2)

Mismatch Mismatch

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Block constraints vs Top Constraints

Bottom-up or Top-down design flow validation
Chip_Top
set_input_delay Input 2.75 -clock CLK1 Signal? -setup [get_ports in1] create_clock name CLKA period 10 edges Clock 10} {0 5 [get_port clka]

USB core
MCP? MCP 2

Output Signal ?
set_output_delay 1.5 clock CLK1 setup [get_ports out1] set_multicycle_path 2 -from [get_pins ff1/CP - to [get_pins ff2/D] set_false_path -from CLKA to CLKB set_false_path -from CLKB to CLKA

Signals?

create_clock name CLKB period 50 edges {0 20 50} [get_port clkb]

False clock relationship?

Bottom-up flow: 3. Block-level constraints are up to top 1. Constraints are propagated created level 4. Block is optimized alone top-level constraints are 2. User wants to ensure thatthen integrated with chip complete
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Results
Single netlist and 2 constraints
Design #instances (M) 0.7 1.2 2.2 2.2 3.5 4.4 4.7 5.4 Single Core (sec) 97 215 7 58 1442 59952 420 5952 4 cores (sec) 45 60 2 24 718 15901 133 2521 X factor Single Core (GB) 1.70 5.43 0.29 2.84 26.7 7.85 7.94 12.55 4 cores (GB) 1.70 5.43 0.29 2.84 26.7 7.85 7.94 12.55

D1 D2 D3 D4 D5 D6 D7 D8

2.2 3.6 3.5 2.4 2 3.8 3.2 2.4

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Results
Block Constraints vs top Constraints
Design Top1/Block1 Top1/Block2 Top2/Block1 Top2/Block2 Top3/Block1 Top3/Block2 #instances in Top (M) 4.7 4.7 1.4 1.4 1.1 1.1 #instances in Block (M) 1.5 0.9 0.6 0.5 0.2 0.2 Runtime (CPU Sec) 182 212 109 309 14 8

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Summary
Advantages of our approach

Efficient solution that compares two constraint behaviors

Compare compressed vs. non-compressed exceptions Compares different constraints with similar affects (false paths vs. set_case_analysis) Accounts for precedence rules

Easily parallelizable Timing relationships help report mismatches in form of original user constraints Many applications
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Thank You
Questions

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