Introduction

Abstract
A Metal Semiconductor Metal (MSM) structure has been fabricated by metallization of
Au(with Cr to increase adhesion) on both the surfaces of a ntypeSi substrate. Metallized
circular dots have been formed on one surface by means of photolithography and the
other surface was completely metallized. The fabrication process was carried out using
conventional technology. Current and Voltage characteristics of the device fabricated, has
been studied both theoretically and experimentally under both illuminated and dark
condition. The study of surface morphology was performed using FESEM analysis.
Theoretical evaluation of carrier concentration, minority carrier diffusion coefficient,
minority carrier lifetime and estimation of the surface state density at the metal-
semiconductor interface has been performed. Rise in current under illumination of
reverse biased junction suggests the photodetective property of the device fabricated and
hence provides a step towards careful design of photodetectors in future through more
sophisticated fabrication procedure. Defects of the metallization surface and the
importance of the process in which metallization should be carried out to yield proper
schottky contacts have been studied.

A planar metal-semiconductor-metal photodetector (MSMPD) consists of

interdigitated metal fingers forming Schottky diodes on a semiconductor surface. These
detectors are very attractive for many optoelectronic applications,particularly because of
their high frequency capability combined with simple, IC compatible processing
technology,which enables multi-Gbit optical communication and easy integration. The
planar structure of MSM detectors also results in the inherently low capacitance,which is
beneficial for the detector sensitivity.The operation of the MSM photodetectors can be
classified into two groups according to whether its intrinsic speed is limited by transit
time or recombination time .In the first group, the detector speed is tried to be increased
by minimizing the finger spacing, which decreases the transit time of the photogenerated
charge carriers. In the latter group, the carrier recombination time is shortened by
introducing recombination centers into the semiconductor.However, this technique to
increase the device speed has its drawbacks: it is not an IC compatible technique and it
decreases the sensitivity of the detector.The fastest transit-time-limited GaAs-MSM
photodetectors have been fabricated by Chou et al. [1]. By using e-beam lithography they
could make detectors having the smallest finger spacing and finger width of 25nm
resulting in an estimated impulse response as short as 250fs. Compound semiconductors
have been the most studied materials for MSM detectors, but recently also silicon has
attracted significant interest [2] due to the low cost substrate material and IC
compatibility.In this paper we present the design, fabrication and characterization of
MSM photodetectors. We focus on silicon MSM-PDs, but for comparison show also
some results for GaAs-MSM detectors made with the same dimensions as the Si-PDs. As
a new structure we present a n+ - n--structure for the Si-MSM-PD in order to increase the

1
device speed. A comparative study of the dufferent types of detectors commonly used is
shown in the schematic below :

Detector Technologies
Layer Structure Features
Simple, Planar,
MSM Semiinsulating GaAs
Low Capacitance
Low Quantum Efficiency
(Metal Semiconductor Metal)

Contact InGaAsP p 5x10 18 Trade-off Between

PIN Absorption InGaAs n- 5x10 14 Quantum efficiency
Contact InP n 1x10 19 and Speed

Contact InP p 1x1018 Gain-Bandwidth:

Multiplication InP n 5x10 16 120GHz
APD Transition InGaAsP n 1x1016 Low Noise
Absorption InGaAs n 5x10 14 Difficult to make
Contact InP n 1x1018 Complex
Substrate InP Semi insulating

Waveguide Absorption Layer High efficiency

High speed
Guide Layers Difficult to couple into

Key: Absorption Layer

Contact layers

From fabrication point of view ,photoconductor is an attractive device ,but its high dark
current and associated Johnson noise makes its unsuitable for high performance
communication systems .With proper design ,APD p-i-n diode can give high
responsively and good quantum efficiency, and thus can satisfy most of the detection
needs in optical communication systems.However because certain drawbacks like
requirements of high bias values, together with requirement of bias stability, and
considerable noise associated with avalanche process has renewed interest in other
devices such as phototransistors, modulated barrier photodiodes, schottky diode and
metal- semiconductor –metal(MSM)diodes .For simplicity of operation and ease of
fabrication, schottky diodes and MSM diodes are mostly preferred now a days in
communication applications .Since MSM diodes have simple technology, any
improvement in responsivity, the current limiting factor to their widespread use,will
allow this class of photodetectors to supplant existing photodetectors in the market place.

2
Metal-semiconductor-Metal(MSM) photodetectors offer an attractive benefit over
alternative photo detectors such as conventional p-i-n diode.

A MSM photo detector is inherently planar and requires only a single lithography
step , which is compatible with existing Field Effect Transistor(FET)technology-MSM
photodetectors have very low dark current.The advantages of a MSM Photodetector can
sumamrised in the schematic shown below :

MSM Detectors
Light
Schottky barrier
gate metal
•Simple to fabricate

•Quantum efficiency: Medium Semi insulating GaAs

Problem: Shadowing of absorption
region by contacts Simplest Version

•Capacitance: Low
To increase speed
•Bandwidth: High decrease electrode spacing
Can be increased by thinning absorption layer and and absorption depth
backing with a non absorbing material. Electrodes
must be moved closer to reduce transit time.
Absorption
•Compatible with standard electronic processes layer

GaAs FETS and HEMTs E Field

InGaAs/InAlAs/InP HEMTs Non absorbing substrate penetrates for
~electrode spacing
into material

To fabricate the MSM device we choose Silicon as the base material. Silicon is the
preferred material for semiconductor device fabrication .One of the reasons is that silicon
is cheap and easily available due to its abundance in the earths crust. Moreover SiO2 can
be easily grown over silicon. SiO2 is used for isolation, junction passivation, and
masking and for growing the gate and field oxide layers.

A lot of work has been carried out in the area and reports are available on the
fabrication of the photoreceiver with MSM photodetector and HBT\HEMT as a
preamplifier on the same chip in published literature. Very recently MISIM{Metal
Insulator Semiconductor Insulator Metal) tunnel transistor has been reported which

3
shows sizable current gain of 30 in the common base mode and switch in the common
emitter mode. Thus in the near future a planar integrated photoreceiver system can be
realized through the MISIM tunnel transistor as a preamplifier in lieu of HBT/HEMT. A
MSM photodiode and MISM tunnel transistor can be connected in CE configuration as a
pre amplifier .The advantage of this tunnel transistor is that it can operate at a very low
current level of the order of Na. Hence a very weak signal can be amplified to a very
large magnitude by such a device. The simplicity of fabrication and economic
consideration are the major advantage of the devices compared to the conventional
photoconducter. But the proper care should taken while fabricating the device such that
insulating layer of the MISIM tunnel transistor should very thin of the order of nm.
Owing to the rapid & phenomenal development of MOS technology. It is now possible
to have a gate oxide layer thickness of the order of a few nanometers even in
commercially fabricated MOS –VLSI circuits. Therefore realization of MISIM tunnel
transistor with few nm of insulating layer thickness is now possible by using the latest
techonology in this field Apart from the use of the MSM Devices in photoreceiver as
photodetector this structure can also be used to realize microwave BARITT diodes. Not
withstanding the inferior efficiency and power of the BARITT as compared to IMPATT
diodes, these diodes have good signal to noise performances and are useful as local
oscillators in microwave receivers .The microwave oscillations in BARITT Diodes starts
when the applied voltage exceeds a characteristics voltage known as reach through
voltage ,As per the power level is now low BARITT is a better option than the IMPATT
diode, which has become the industry standard microwave devices. This type of reach
through diode is useful as a high voltage limiter having a sharp current rise above reach
through voltage .The diodes with voltages as low as 1.5Volt have been made with
performance comparable or better than the conventional Zener diode, which operate s via
break down mechanisms .

The Scope of my Work :

The aim is to fabricate Si-MSM photodetector, which is different from the conventional
method. A lot of papers have been published in this area. Today many interdigitated
MSM structures are being developed with micrometer spacings between the fingers. But
the preparation of mask is very difficult and can not be done without advanced
lithography techniques.Therefore to simplify the fabrication process the author is
motivated by the fundamental worksin 1970 by S.M.Sze & D.J.Coleman [Solid state
electron, 14,1209 (1971)]. Here a MSM is fabricated which is asymmetric with respect to
work function. I-V, C-V measurements are done for the fabricated structure. Raise in
current from I-V measurement under illuminated condition predicts the expected
photodetction properties of the device. Deviation from the theoretical behavior will be
confirmed by surface state studies at the metal semiconductor interface.Even though the
MSM structure can be used as a microwave device, in my current project, the device
characteristics with regard to photodetection capabilities is studied.

4
BASIC THEORY

5
 Chapter 1
The Metal-Semiconductor Junction.
Schottky Diode & Ohmic Contacts

Metal-to-semiconductor contacts are of great importance since they are present in every
semiconductor device. They can behave either as a Schottky barrier or as an ohmic
contact dependent on the characteristics of the interface. This chapter contains an analysis
of the electrostatics of the M-S junction (i.e. the charge, field and potential distribution
within the device) followed by a derivation of the current voltage characterisitics due to
diffusion, thermionic emission and tunneling and a discussion of the non-ideal effects in
Metal-Semiconductor junctions.

Structure and principle of operation

1 Structure
The structure of a metal-semiconductor junction is shown in Figure 1. It consists of a
metal contacting a piece of semiconductor. An ideal Ohmic contact, a contact such that
no potential exists between the metal and the semiconductor, is made to the other side
of the semiconductor. The sign convention of the applied voltage and current is also
shown on Figure 1.

Figure 1 : Structure and sign convention of a metal-semiconductor junction

2 Flatband diagram and built-in potential

The barrier between the metal and the semiconductor can be identified on an energy band
diagram. To construct such diagram we first consider the energy band diagram of the
metal and the semiconductor, and align them using the same vacuum level as shown in

6
Figure 2 (a). As the metal and semiconductor are brought together, the Fermi energies
of the metal and the semiconductor do not change right away. This yields the flatband
diagram of Figure 2 (b).

Fig2 : Energy band diagram of the metal and the semiconductor

(a) before and (b) after contact is made.

The barrier height, φB, is defined as the potential difference between the Fermi energy of
the metal and the band edge where the majority carriers reside. From Figure 2 (b) one
finds that for an n-type semiconductor the barrier height is obtained from:

(1.1)

Where ΦM is the work function of the metal and χ is the electron affinity. The work
function of selected metals as measured in vacuum can be found in Table 1. For
p-type material, the barrier height is given by the difference between the valence
band edge and the Fermi energy in the metal:

(1.2)
A metal-semiconductor junction will therefore form a barrier for electrons and holes
if the Fermi energy of the metal as drawn on the flatband diagram is somewhere
between the conduction and valence band edge.
In addition, we define the built-in potential, φI, as the difference between the Fermi
Energy of the metal and that of the semiconductor.

7
 (1.3)

(1.4)
The measured barrier height for selected metal-semiconductor junctions is listed in
Table 1. These experimental barrier heights often differ from the ones calculated
using (1.1) or (1.2). This is due to the detailed behavior of the metal-semiconductor
interface. The ideal metal-semiconductor theory assumes that both materials are
infinitely pure, that there is no interaction between the two materials nor is there an
interfacial layer. Chemical reactions between the metal and the semiconductor alter
the barrier height as do interface states at the surface of the semiconductor and
interfacial layers. Some general trends however can still be observed. As predicted
by (1.1), the barrier height on n-type semiconductors increases for metals with a higher
work function as can be verified for silicon. Gallium arsenide on the other hand is known
to have a large density of surface states so that the barrier height becomes virtually
independent of the metal. Furthermore, one finds the barrier heights reported in the
literature to vary widely due to different surface cleaning procedures.

Table 1: Workfunction of selected metals and their measured barrier height

on Ge, Si and GaAs.

2.3. Thermal equilibrium

8
The flatband diagram, shown in Figure 2 (b), is not a thermal equilibrium diagram,
since the Fermi energy in the metal differs from that in the semiconductor. Electrons
in the n-type semiconductor can lower their energy by traversing the junction. As the
electrons leave the semiconductor, a positive charge, due to the ionized donor atoms,
stays behind. This charge creates a negative field and lowers the band edges of the
semiconductor. Electrons flow into the metal until equilibrium is reached between the
diffusion of electrons from the semiconductor into the metal and the drift of electrons
caused by the field created by the ionized impurity atoms. This equilibrium is
characterized by a constant Fermi energy throughout the structure.

Fig3: EB Diagram of a metal semiconductor contact under

thermal equilibrium condition

It is of interest to note that in thermal equilibrium, i.e. with no external voltage applied,
there is a region in the semiconductor close to the junction ( ), which is depleted of
mobile carriers. We call this the depletion region. The potential across
the semiconductor equals the built-in potential, φi.

2.4. Forward and reverse bias

Operation of a metal-semiconductor junction under forward and reverse bias is
illustrated with Figure 4. As a positive bias is applied to the metal (Figure 4 (a)),
the Fermi energy of the metal is lowered with respect to the Fermi energy in the
semiconductor. This results in a smaller potential drop across the semiconductor.
The balance between diffusion and drift is disturbed and more electrons will diffuse
towards the metal than the number drifting into the semiconductor. This leads to a
positive current through the junction at a voltage comparable to the built-in potential.

9
Fig4 : Energy band diagram of a metal-semiconductor junction
under (a) forward and (b) reverse bias

As a negative voltage is applied (Figure 4 (b)), the Fermi energy of the metal is raised
with respect to the Fermi energy in the semiconductor. The potential across the
semiconductor now increases, yielding a larger depletion region and a larger electric field
at the interface. The barrier, which restricts the electrons to the metal, is unchanged so that
the flow of electrons is limited by that barrier independent of the applied voltage. The
metal-semiconductor junction with positive barrier height has therefore a pronounced
rectifying behavior. A large current exists under forward bias, while almost no current exists
under reverse bias.
The potential across the semiconductor therefore equals the built-in potential, φi, minus the
applied voltage, Va.
(2.1)

3 Electrostatic analysis

3.1. General discussion - Poisson's equation

The electrostatic analysis of a metal-semiconductor junction is of interest since it provides
knowledge about the charge and field in the depletion region. It is also required to obtain the
capacitance-voltage characteristics of the diode.
The general analysis starts by setting up Poisson's equation:

10
 (3.1)
where the charge density, ρ, is written as a function of the electron density, the hole density
and the donor and acceptor densities. To solve the equation, we have to express the electron
and hole density, n and p, as a function of the potential, φ, yielding:

(3.2)
with

(3.3)
where the potential is chosen to be zero in the n-type region, where x >> xn.
This second-order non-linear differential equation (3.2) can not be solved analytically.
Instead we will make the simplifying assumption that the depletion region is fully depleted
and that the adjacent neutral regions contain no charge. This full depletion approximation is
the topic of section 3.2.

3.2. Full depletion approximation

The simple analytic model of the metal-semiconductor junction is based on the full depletion approximation.
This approximation is obtained by assuming that the semiconductor is fully
depleted over a distance xd, called the depletion region. While this assumption does not
provide an accurate charge distribution, it does provide very reasonable approximate
expressions for the electric field and potential throughout the semiconductor.

3.3. Full depletion analysis

We now apply the full depletion approximation to an M-S junction containing an n-type
semiconductor. We define the depletion region to be between the metal-semiconductor
interface (x = 0) and the edge of the depletion region (x = xd). The depletion layer width, xd,
is unknown at this point but will later be expressed as a function of the applied voltage.
To find the depletion layer width, we start with the charge density in the semiconductor
and calculate the electric field and the potential across the semiconductor as a function of
the depletion layer width. We then solve for the depletion layer width by requiring the
potential across the semiconductor to equal the difference between the built-in potential
and the applied voltage, φi - Va. The different steps of the analysis are illustrated by
Figure 3.1
As the semiconductor is depleted of mobile carriers within the depletion region, the charge
density in that region is due to the ionized donors. Outside the depletion region, the
semiconductor is assumed neutral. This yields the following expressions for the charge
density, ρ:

11
 (3.4)
where we assumed full ionization so that the ionized donor density equals the donor
density, Nd. This charge density is shown in Figure3.1(a). The charge in the semiconductor
is exactly balanced by the charge in the metal, QM, so that no electric field exists except
around the metal-semiconductor interface.

Fig3.1: (a) Charge density, (b) electric field, (c) potential and
(d) energy as obtained with the full depletion analysis.
Using Gauss's law we obtain electric field as a function of position, also shown in
Figure 5 (b):

(3.5)
where εs is the dielectric constant of the semiconductor. We also assumed that the electric
field is zero outside the depletion region. It is expected to be zero there since a non-zero field
would cause the mobile carriers to redistribute until there is no field. The depletion region does
not contain mobile carriers so that there can be an electric field. The largest (absolute) value
of the electric field is obtained at the interface and is given by:

12
 (3.6)
where the electric field was also related to the total charge (per unit area), Qd, in the
depletion layer. Since the electric field is minus the gradient of the potential, one obtains
the potential by integrating the expression for the electric field, yielding:

(3.7)
We now assume that the potential across the metal can be neglected. Since the density of
free carriers is very high in a metal, the thickness of the charge layer in the metal is very thin.
Therefore, the potential across the metal is several orders of magnitude smaller that that
across the semiconductor, even though the total amount of charge is the same in both regions.
The total potential difference across the semiconductor equals the built-in potential, φi, in
thermal equilibrium and is further reduced/increased by the applied voltage when a
positive/negative voltage is applied to the metal as described by equation (3.5). This
boundary condition provides the following relation between the semiconductor potential
at the surface, the applied voltage and the depletion layer width:

(3.8)
Solving this expression for the depletion layer width, xd, yields:

(3.9)
3.4. Junction capacitance
In addition, we can obtain the capacitance as a function of the applied voltage by taking
the derivative of the charge with respect to the applied voltage yielding:

(3.10)
The last term in the equation indicates that the expression of a parallel plate capacitor still
applies. One can understand this once one realizes that the charge added/removed from the
depletion layer as one decreases/increases the applied voltage is added/removed only at the
edge of the depletion region. While the parallel plate capacitor expression seems to imply
that the capacitance is constant, the metal-semiconductor junction capacitance is not constant
since the depletion layer width, xd, varies with the applied voltage.

3.5. Schottky barrier lowering

Image charges build up in the metal electrode of a metal-semiconductor junction as carriers
approach the metal-semiconductor interface. The potential associated with these charges

13
 reduces the effective barrier height. This barrier reduction tends to be rather small compared
to the barrier height itself. Nevertheless this barrier reduction is of interest since it depends
on the applied voltage and leads to a voltage dependence of the reverse bias current. Note
that this barrier lowering is only experienced by a carrier while approaching the interface and
will therefore not be noticeable in a capacitance-voltage measurement.
An energy band diagram of an n-type silicon Schottky barrier including the barrier lowering
is shown in Figure 3.2:

Figure 3.2: Energy band diagram of a silicon Schottky barrier with

φ B = 0.8 V and Nd = 1019 cm-3.

Shown is the energy band diagram obtained using the full-depletion approximation, the
potential reduction experienced by electrons, which approach the interface and the resulting
conduction band edge. A rounding of the conduction band edge can be observed at the
metal-semiconductor interface as well as a reduction of the height of the barrier.
The calculation of the barrier reduction assumes that the charge of an electron close to the
metal-semiconductor interface attracts an opposite surface charge, which exactly balances
the electron's charge so that the electric field surrounding the electron does not penetrate
beyond this surface charge. The time to build-up the surface charge and the time to polarize
the semiconductor around the moving electron is assumed to be much shorter than the transit
time of the electron . This scenario is based on the assumption that there are no mobile or
fixed charges around the electron as it approaches the metal-semiconductor interface. The
electron and the induced surface charges are shown in Figure 3.3:

14
 Fig 3.3: a) Field lines and surface charges due to an electron
in close proximity to a perfect conductor and
b) the field lines and image charge of an electron.

It can be shown that the electric field in the semiconductor is identical to that of the carrier
itself and another carrier with opposite charge at equal distance but on the opposite side of
the interface. This charge is called the image charge. The difference between the actual surface
charges and the image charge is that the fields in the metal are distinctly different. The image
charge concepts is justified on the basis that the electric field lines are perpendicular to the
surface a perfect conductor, so that, in the case of a flat interface, the mirror image of the
field lines provides continuous field lines across the interface.
The barrier lowering depends on the square root of the electric field at the interface and is
calculated from:

(3.11)

4. Schottky diode current

The current across a metal-semiconductor junction is mainly due to majority carriers. Three
distinctly different mechanisms exist: diffusion of carriers from the semiconductor into the
metal, thermionic emission of carriers across the Schottky barrier and quantum-mechanical
tunneling through the barrier. The diffusion theory assumes that the driving force is distributed
over the length of the depletion layer. The thermionic emission theory on the other hand
postulates that only energetic carriers, those, which have an energy equal to or larger than the
conduction band energy at the metal-semiconductor interface, contribute to the current flow.
Quantum-mechanical tunneling through the barrier takes into account the wave-nature of the
electrons, allowing them to penetrate through thin barriers. In a given junction, a combination
of all three mechanisms could exist. However, typically one finds that only one limits the
current, making it the dominant current mechanism.
The analysis reveals that the diffusion and thermionic emission currents can be written in the
following form:

15
 (4.1)
This expression states that the current is the product of the electronic charge, q, a velocity, v,
and the density of available carriers in the semiconductor located next to the interface. The
velocity equals the mobility multiplied with the field at the interface for the diffusion current
and the Richardson velocity (see section 3.4.2) for the thermionic emission current. The minus
one term ensures that the current is zero if no voltage is applied as in thermal equilibrium any
motion of carriers is balanced by a motion of carriers in the opposite direction.
The tunneling current is of a similar form, namely:
(4.2)
where vR is the Richardson velocity and n is the density of carriers in the semiconductor. The
tunneling probability term, Θ, is added since the total current depends on the carrier flux arriving
at the tunnel barrier multiplied with the probability, Θ, that they tunnel through the barrier.

4.1. Diffusion current

This analysis assumes that the depletion layer is large compared to the mean free path, so that
the concepts of drift and diffusion are valid. The resulting current density equals:

(4.3)
The current therefore depends exponentially on the applied voltage, Va, and the barrier height,
φB. The prefactor can more easily be understood if one rewrites it as a function of the electric field
at the metal-semiconductor interface, max:

(4.4)
yielding:

(4.5)
so that the prefactor equals the drift current at the metal-semiconductor interface, which for zero

4.2 Thermionic emission

The thermionic emission theory assumes that electrons, which have an energy larger than the
top of the barrier, will cross the barrier provided they move towards the barrier. The actual shape
of the barrier is hereby ignored. The current can be expressed as:

(4.6)

where is the Richardson constant and φB is the Schottky barrier height.

16
The expression for the current due to thermionic emission can also be written as a function of
the average velocity with which the electrons at the interface approach the barrier. This velocity
is referred to as the Richardson velocity given by:

(4.7)
So that the current density becomes:

(4.8)

4.3. Tunneling
The tunneling current is obtained from the product of the carrier charge, velocity and density.
The velocity equals the Richardson velocity, the velocity with which on average the carriers
approach the barrier. The carrier density equals the density of available electrons, n, multiplied
with the tunneling probability, Θ, yielding:
(4.9)
Where the tunneling probability is obtained from:

(4.10)
and the electric field equals = φB/L.
The tunneling current therefore depends exponentially on the barrier height, φB, to the
3/2 power.

SCHOTTKY DIODES

Metal-semiconductor contact at zero bias

Electrons in the conduction band of a crystal can be viewed as sitting in a potential box
formed by the crystal boundaries (see Fig. 1). This potential box for electrons is usually
deeper in a metal than in a semiconductor. If a metal and a semiconductor are brought
together into a close proximity, some electrons from the metal will move into the
semiconductor and some electrons from the semiconductor will move into the
metal. However, since the barrier for the electron escape from the metal is higher, more
electrons will transfer from the semiconductor into the metal than in the opposite
direction. At thermal equilibrium, the metal will be charged negatively, and the
semiconductor will be charged positively, forming a dipole layer that is very similar to
that in a p+-n junction. The Fermi level will be constant throughout the entire metal-
semiconductor system, and the energy band diagram in the semiconductor will be similar
to that for an n-type semiconductor in a p+-n junction (see Fig. 2).

17
Fig. 1. Schematic energy diagram for electrons in conduction bands of a metal and of a
semiconductor.

Energies m and s shown in Fig. 2 are called the metal and the semiconductor
work functions. The work function is equal to the difference between the vacuum
level (which is defined as a free electron energy in vacuum) and the Fermi level. The
electron affinity of the semiconductor, s (also shown in Fig. 2), corresponds to the
energy separation between the vacuum level and the conduction band edge of the
semiconductor.

18
Fig. 2. Simplified energy diagram of GaAs metal-semiconductor barrier q b is the
barrier height (0.75 eV), s is the electron affinity in the semiconductor, s and m are
the semiconductor and the metal work functions, and Vbi (0.591 V) is the built-in
voltage. Donor concentration in GaAs is 1015 cm–3.

A metal-semiconductor diode is called a Schottky diode. In the idealized picture of the

Schottky junction shown in Fig. 2, the energy barrier between the semiconductor and the
metal is

(1)

Since m > s the metal is charged negatively. The positive net space charge in the
semiconductor leads to a band bending

(2)

where Vbi is called the built-in voltage, in analogy with the corresponding quantity in a
p-n junction. Note that qVbi is also identical to the difference between the Fermi levels
in the metal and the semiconductor when separated by a large distance (no exchange of
charge); see Fig. 1.

19
However, eq. (1) and Fig. 2 are not quite correct. In reality, a change in the metal work
function, m, is not equal to the corresponding change in the barrier height , b, as
predicted by eq. (1). In actual Schottky diodes, b increases with an increase in m but
only by 0.1 to 0.3 eV when m increases by 1 to 2 eV. Even though a detailed and
accurate understanding of Schottky barrier formation remains a challenge, many
properties of Schottky barriers may be understood independently of the exact mechanism
determining the barrier height. In other words, we can simply determine the effective
barrier height from experimental data. Usually, as a crude and empirical rule of thumb,
we can assume that the Schottky barrier height for an n-type semiconductor is close to
1/2 and 2/3 of the energy gap.

In a Schottky diode, the semiconductor band diagram looks very similar to that of an n-
type semiconductor in a p+-n diode (compare Fig. 1a and 2). Hence, the variation of the
space charge density, , the electric field, F, and the potential, , in the semiconductor
near the metal-semiconductor interface can be found using the depletion approximation:

(3)

(4)

(5)

(Here x = 0 corresponds to the metal-semiconductor interface.) The depletion layer

width, xn, at zero bias is given by

(6)

Schottky diode under bias

Forward bias corresponds to a positive voltage applied to the metal with respect to the
semiconductor. Just as for a p+-n junction, the depletion width under small forward
bias and reverse bias may be obtained by substituting Vbi with Vbi– V, where V is the
applied voltage. As illustrated in Fig. 3, the application of a forward bias decreases the
potential barrier for electrons moving from the semiconductor into the metal. Hence, the
current-voltage characteristic of a Schottky diode can be described by a diode equation,
similar to that for a p-n junction diode :

(7)

20
where Is is the saturation current, Rsis the series resistance, Vth = kBT/q is the thermal
voltage, and is the ideality factor ( typically varies from 1.02 to 1.6).

(a) (b) (c)

Fig. 3. Band diagrams for a GaAs Schottky barrier diode at (a) zero bias, (b) 0.2 V
forward bias, and (c) 5 V reverse bias. Dashed line shows the position of the Fermi
level in the metal (x < 0) and in the semiconductor (x > 0).

Thermionic emission.

The diode saturation current, Is, is typically much larger for Schottky barrier diodes than
in p-n junction diodes since the Schottky barrier height is smaller than the barrier height
in p-n junction diodes. In a p-n junction, the height of the barrier separating electrons in
the conduction band of the n-type region from the bottom of the conduction band in the
p-region is on the order of the energy gap. A typical Schottky barrier height is only about
two thirds of the energy gap or less, as mentioned above. Also, the mechanism of the
electron conduction is different. One can show that the saturation current density in a
Schottky diode with a relatively low doped semiconductor is given by

(8)

where A* is called the Richardson constant. For a conduction band minimum with
spherical surfaces of equal energy (such as the minimum in GaAs),

21
 (9)

where mn is the effective mass and is an empirical factor on the order of unity. The
Schottky diode model described by eqs. (8) and (9) is called the thermionic emission
model. For Schottky barrier diodes of Si, A* = 96 A/(cm2K2). For GaAs, A* = 4.4
A/(cm2K2).

The basic assumption of the thermionic model is that electrons have to pass over the
barrier in order to cross the boundary between the metal and the semiconductor. Hence,
to find the saturation current, we have to estimate the number of electrons passing over
the barrier and their velocities. The number of electrons, N(E)dE, having energies
between E and E + dE is proportional to the product of the Fermi-Dirac distribution
function, f(E), and the number of states in this energy interval, g(E)dE, where g(E) is the
density of states:

(10)

[N(E) = dn(E)dE where n(E) is the number of electrons in the conduction band with
energies higher than E. At high energies, the Fermi-Dirac occupation function is very
close to the Boltzmann distribution function :

(11)

The next step should be to multiply the number of the electrons, N(E)dE, in the energy
interval from E to E + dE by the velocity of these electrons. We have to account for
different directions of the electron velocities and integrate over energies higher than the
barrier height in order to determine the flux of the electrons coming from the
semiconductor into the metal. Finally, we deduct the flux of the electrons coming from
the metal into the semiconductor. The difference between these two fluxes will be
proportional to the current density predicted by the thermionic model. However, we can
take a much simpler route if we are interested in understanding the physics of the
thermionic model. To this end, let us consider a Schottky diode under a strong reverse
bias when V is negative and – V >> kBT. Then I = – Is [see eq. (7)], and the band
diagram looks like that shown in Fig. 3c. In this case the energy difference between the
Fermi level in the semiconductor and the top of the barrier is so large that practically no
electrons are available to come from the semiconductor into the metal. However, the
Fermi level in the metal is much closer to the top of the barrier, and electrons still come
from the metal into the semiconductor. The flux of these electrons constitutes the
saturation current. In order to estimate this flux, we should recall that the density of
states is a relatively slow function of energy [g(E) is proportional to (E – Ec)1/2; compared

22
to the distribution function, which decreases by exp(1) ≈ 2.718 each time E increases by
kBT. Hence, the largest contribution into the electron flux will come from the electrons
that are a few kBT above the barrier. The number of such electrons will be proportional to
the effective density of states in the semiconductor

(12)

and to exp(– b/kBT). Their velocity in the direction perpendicular to the metal
semiconductor interface is proportional to the thermal velocity

(13)

Hence, the saturation current density is given by

(14)

where C is a numerical constant of the order of unity. With a proper choice of C, this
equation coincides with eqs. (8) and (9).

Thermionic-field emission

In relatively highly doped semiconductors, the depletion region becomes so narrow that
electrons can tunnel through the barrier near the top (see Fig. 4b). This process is called
thermionic-field emission. In order to understand thermionic-field emission, we have to
recall once again that the number of electrons with energies above a given energy E
decreases exponentially with energy as exp[–E/(kBT)]. On the other hand, the barrier
transparency increases exponentially with the decrease in the barrier width. Hence, as the
doping increases and the barrier becomes thinner, the dominant electron tunneling path
occurs at lower energies than the top of the barrier (see Fig. 4b).

In degenerate semiconductors, especially in semiconductors with a small electron

effective mass such as GaAs, electrons can tunnel through the barrier near or at the Fermi

23
level, and the tunneling current is dominant. This mechanism is called field emission
(see Fig. 4c).

Fig. 4. Band diagrams of Schottky barrier junctions for GaAs for doping levels Nd =
1015 cm–3 (top graph), Nd = 1017 cm–3 (middle graph), and Nd = 1018 cm–3 (bottom
graph). Arrows indicate electron transfer across the barrier under forward bias. At
very low doping levels, electrons go over the barrier closer to the top of the barrier
(this process is called thermionic emission). At moderated doping levels, electrons
tunnel across the barrier closer to the top of the barrier (this process is called
thermionic-field emission). In highly doped degenerate semiconductors, electrons
near the Fermi level tunnel across a very thin depletion region (this process is called
field emission).

The current-voltage characteristic of a Schottky diode in the case of thermionic-field

emission can be calculated using the same approach as for the thermionic model, except
that in thermionic-field emission case, we have to evaluate the product of the tunneling
transmission coefficient and the number of electrons at a given energy as a function of
energy and integrate over the states in the conduction band. Such a calculation [see
Rhoderick and Williams (1988)] yields the following expression for the current density in
the thermionic-field emission regime under forward bias:

24
 (15)

where

(16)

(17)

(18)

In GaAs Schottky diodes, the thermionic-field emission becomes important for Nd >
1017 cm–3 at 300 K and for Nd > 1016 cm–3 at 77 K. In silicon, the corresponding values
of Nd are several times larger. The forward j-V characteristics are shown in Fig. 5.

Fig. 5. Forward j-V characteristics of GaAs Schottky diodes doped at 1015, 1017, and
1018 cm–3 (curves are marked accordingly) at T = 300 K.

The resistance of the Schottky barrier in the field emission regime is quite low.
Therefore metal-n+ contacts are used as ohmic contacts. The specific contact resistance,
c, decreases with the increase in the doping level of the semiconductor.(This resistance

25
may vary from 10-3 Ωcm2 to 10-7 Ωcm2 or even smaller depending on semiconductor
material, doping level, contact metal, and ohmic contact fabrication technology.)

A Schottky diode is a majority carrier device, where electron-hole recombination is

usually not important. Hence, Schottky diodes have a much faster response under
forward bias conditions than p-n junction diodes. Therefore, Schottky diodes are used in
applications where the speed of a response is important, for example, in microwave
detectors, mixers, and varactors.

26
27
28
OHMIC CONTACTS

29
In the case of a p-n diode, for example, contacts have to be provided to both p-type and n-
type regions of the device in order to connect the diode to an external circuit. These
contacts have to be as unobtrusive as possible, so that the current flowing through a
semiconductor device and, hence, through the contacts, leads to the smallest parasitic
voltage drop possible. Whatever voltage drop does occur across the contact has to be
proportional to the current so that the contacts do not introduce uncontrollable and
unexpected nonlinear elements into the circuit. Since such contacts satisfy Ohm's law,
they are usually called ohmic contacts.

As was discussed, a contact between a metal and a semiconductor is typically a Schottky

barrier contact. However, if the semiconductor is very highly doped, the Schottky
barrier depletion region becomes very thin, as illustrated in Fig. 4. At very high doping
levels, a thin depletion layer becomes quite transparent for electron tunneling. This
suggests that a practical way to make a good ohmic contact is to make a very highly
doped semiconductor region between the contact metal and the semiconductor.

It may have been better to use a metal with a work function, m, which is equal to or
smaller than the work function of a semiconductor, s. However, for most
semiconductors, it is difficult to find such a metal acceptable for practical contacts.

Current-voltage characteristics of a Schottky barrier diode and of an ohmic contact are

compared in Fig. 1. As was mentioned above, a good ohmic contact should have a linear
current-voltage characteristic and a very small resistance that is negligible compared to
the resistance of the active region of the semiconductor device. An ohmic contact with
the I-V characteristic shown in Fig. 2 does not satisfy fully these conditions since the
voltage drop across this contact is not negligibly small compared with the voltage drop
across the Schottky diode at moderate current densities above 0.1 kA/cm2.

As was discussed, the barrier between a metal and a semiconductor is usually smaller for
semiconductors with smaller energy gaps.Hence, another way to decrease the contact
resistance is to place a layer of a narrow gap highly doped semiconductor material
between the active region of the device and the contact metal. Some of the best ohmic
contacts to date have been made this way.

A quantitative measure of the contact quality is the specific contact resistance, c,

which is the contact resistance of a unit area contact. Depending on the semiconductor
material and on the contact quality, c can vary anywhere from 10-3 Ωcm2 to 10-7 Ωcm2 or
even less.

30
Fig. 1. Current-voltage characteristics of ohmic and Schottky barrier metal-
semiconductor contacts to GaAs. (Schottky contact is to GaAs doped at 1015 cm-3.)
Ohmic contact resistance is 104 Ωcm2.

Most semiconductor devices have either a sandwich structure or a planar structure, as

illustrated in Fig. 2. The contact resistance of each contact in a sandwich structure
contact is given by

(1)

A typical current density in a sandwich type device can be as high as 104 A/cm2. Hence,
the specific contact resistance of 10-5 Ωcm2 would lead to a voltage drop on the order of
0.1 V. This may be barely acceptable. A larger specific contact resistance of 10-4 Ωcm2
or so would definitely lead to problems, as we can see from Fig. 1.

These estimates show that a semiconductor material can become viable for applications
in electronic devices only when good ohmic contacts with low contact resistances
become available. Often, poor ohmic contacts become a major stumbling block for
applications of new semiconductor materials.

31
 Chapter 1
Basic Theory
1.1 Theory of MSM Devices
The simplest form of a metal semiconductor metal (MSM) structure is a two terminal
device having uniformly doped semiconductor slice with metal contacts on the opposite
sides of the slices as shown in Fig1(a). the energy band diagram for a MSM structure
under thermal equilibrium is shown in Fig1(b),where φn1 and φn2 are the barrier heights for
the two contacts and VD1 and VD2 are built in potentials respectively and L is the thickness
of the slice. If the areas of the contacts are equal and φ n1= φn2 , we have the symmetrical
MSM structure.

32
It is clear that a MSM structure is basically two back to back Schottky diodes connected
together. Under an applied voltage, one of the contacts (contact no.1) is reversed biased
and the other contact (contact no.2) is forward biased. As the voltage increases, the sum
of the two depletion layer width also increases. Eventually at the reach through voltage
VRT , the two depletion regions touch each other and the sum equals to exactly L . This
situation is illustrated in Fig2(a).

As the voltage increases further, a point is reached at which the electric field at x=L
becomes flat. That is band condition with the corresponding flat. This is the flat band
condition with the corresponding flat band VFB, shown in Fig2(b). For the voltages in
excesses of VFB the energy band is bent further downward as illustrated in Fig2(c) , and
the maximum voltage that can be applied to the MSM structure is limited by the
avalanche breakdown near the maximum field at the contact no.1.

L x
33
- Emf
E
 L
E x V=VFB

- EMF

Fig 2(b) Condition of flat band at which the energy-band at x=L

becomes flat. The corresponding voltage VFB is called flat-band
voltage

E JN

O
-Em2 V
-Emf

φP

Fig2(c) Condition for applied voltage larger than VFB JP

We first consider the potential distribution and the electron current transport in the
following section (1.2). One outstanding feature of the MSM structure is that the
hole(minority) current is many orders of magnitude larger than the electron (majority)
current. The hole current is considered in section 1.6. the total current-voltage
characteristics and CV characteristics are presented in section 1.7.

34
1.2. Potential Distribution and Electron Current :-
When a negative voltage is applied to the contact no.1 , w.r.t. the contact no.2 , as shown
in Fig(3), the barrier φn1 is reverse biased and φn2 is forward biased. The electron current
is due to the thermionic emission of the electrons from contact no.1 . In this case that
before the reach through condition the injected hole current from the contact no.2 is
generally much smaller than the electron current. The current continuity requirements
thus dictate that the electron currents across both the barriers must be equal.

At VRT the structure is entirely depleted but the current is still small. With further increase
in voltage, the electron current remains small but the injected hole current from the
forward biased contact begins to increase rapidly as the hole barrier (φP2 + VD2 – V2)
is lowered.

At VFB the hole current reaches a critical value as the hole barrier approaches its limiting
magnitude φP2 . Further increase in voltage will cause the current to increase slowly due
to field dependence of Schottky barrier height. Finally the Avalanche Breakdown is
reached and the current increases rapidly. We shall first consideer the electron current and
the then the hole current in the following subsections.

1.3 Small Voltage Range :

For low biases such that the sum of depletion widths W1 and W2 are smaller than the
thickness L , the charge distribution of a MSM structure is as shown in Fig3(a), for a n-
type semiconductor with impurity concentration ND .

qND + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+ + + +
+ + + + + + + + +
x
L
Fig 3(a) Charge distribution in a MSM structure for low bias .

35
The potentials can be obtained from the integration of Poisson’s equation.
An* = the effective Richardson constant for electrons.
T = The temperature
q
Β =
RT
Em1 = maximum Electric field at (x=0)
α1 = intrinsic barrier lowering coefficient
∆ϕ n1 = Schottky barrier lowering

qEm 2
We have , ∆Φn1 = ……………………. (1)
4Π εs

2qΝD(V 1 + VD1)
Em1 = …………………….. (2)
εs

The forward current density is given by ,

Jn2 = An*T2 e- βφn2 e β( ∆ φn2 + α 2 Em 2 ) (eβV2 – 1) …………………….. (3)

In the above expression ∆ φn2 can be obtained using eq (3) by evaluating Em2 from eq(2)
replacing (V1 + VD1) by (V2 + VD2 ).

With necessary substitutions we obtain a relationship between V1 and V2 as ,

1
( ∆n1 − ∆n 2 ) + (α 1Em1 + α 2 Em 2 ) + (ϕn1 − ϕn 2 ) =
 e βV2 − 1  …………………….. (4)
β ln 
β V1 
 1 − e 

For symmetrical MSM structure , ϕ n1 =ϕ n 2 , (VD1- VD2)= VD and assuming α 1 = α 2 =0

36
Using the above assumptions the equations can be solved numerically to give the electron
current as a function of the applied voltage.Since contact1 is reverse biased and contact2
is forward biased, thus most of the voltage drop occurs across the depletion region of the
contact1.
1.4 Voltage range larger than the reach-through voltage VRT :
The reach through voltage VRT is defined as the voltage at which the sum of the depletion
width is exactly equal to L.

2ε s (V1 + V D1 )
W1= ………………………. (5)
qN D

2ε s (V D 2 − V2 )
W2 = ……………………….. (6)
qN D

Under reach through condition ,

W1 + W2 = L …………………………(7)

Taking , V1+V2=VRT we have ,

VRT = VFB - 4(VFB + ∆VD )(VD 2 − V 2) …………………………(8)

Where , VFB = Flat Band Voltage =

qNDL2
2ε S
(
− V D1 − V D 2 ) …………………… (9)

And , ∆ VD = VD1 - VD2 ……………………….. (10)

The voltage VD1 - VD2 is the applied voltage which makes W2 = 0.

Since the depletion edge of the reverse biased contact is pushed into that of the forward
biased one, the forward barrier is rapidly reduced with increasing voltage. It follows that
the electron current is now limited by the reverse biased contact.
1.5 Voltages larger than the Flat Band Volatge :

As the voltage increases further, eventually the electric field at x=L becomes zero and the
enrgy band at the contact2 becomes flat . The applied voltage corresponding to the above
situation is called Flat Band Volatge , which has been defined earlier in eq (9). For
assymetrical MSM structure , i.e. ∆ VD = VD1 - VD2 = 0, and hence eq (9) reduces to

qNDL2
VFB = ………………………… (11)
2ε S

37
A plot of VFB with ND is shown in Fig(4) taking L as a parameter. The maximum VFB is
limited by the voltage at which avalanche break down occurs near the reverse biased
contact 1.

103

W=40μm
Avalanche
102
20 Breakdown

VFB (volts) 10

5
101 2
0.5
1

100
1014 1015 1016 1017
N ( cm-3)
Fig4. Flat Band voltage versus doping concentration for Si diodes with
various lengths. For a given length, the maxm. VFB is limited by the Avalanche
Breakdown voltage.

1.6 Hole Current Transport :

The hole current comes about because of the thermionic emission of the holes from the
contact no.2. As shown in Fig3 for small bias , the effective barrier for holes at contact2
is given by (φP2 +VD2 – V2). Those emitted holes which diffused from x2 to x1 constitute
the hole current.

For x2<x<x1 i.e. in neutral region the steady state continuity for hole is given by

∂2 p p − pn0
− ( )=0 …………………………. (12)
∂x 2 D pτ p

where,
pn0 is the equilibrium hole density ,
Dp is the diffusion coefficient &

38
τ p is the life time.
The solution to the eq(12) is simply ,

x −x
p − p n 0 = A exp ( ) + B exp( ) ………………………….. (13)
LP LP

1
Where Lp = diffusion constant.=
DPτ P

The boundary conditions are at :-

− qV1
(a) x = x1 , P=Pn0* exp ( ) ………………………. (14)
KT
(b) x = x2 , JP2 = AP*T2 exp [-β(φP2 + VD2 – V2)] ……………………… (15)

Where AP is the effective Richardson constant for holes. The arbitrary constants A and B
are determined from the boundary conditions.

The hole current density JP1 is then given by the gradient at X1 and the condition that JP1 =
0 at the thermal condition (i.e. V =0)

x −x 
qD p dp  L 
(
qD p pn 0 tanh 2 1  1 − e 1
− βV

A
)T 2
exp [ (
− β ϕ + V )](
e
β V2
)
−1
J p1 = =  p  + P p1 D 2

dx Lp x −x 
x = x1
cosh 2 1 
 L 
 P 
……………………… (16)

For applied voltages in excess of VRT , the neutral region , x2 – x1=0 , and the hole current
reduces to ,

JP1= AP*T2 exp[-β(φP2 + VD2)](eβV2 – 1) …………………… (17)

Therefore for V > VRT ,

( )
  − β V − V 2  
expexp    − exp(− βVD 2 ) ………………………(18)
( )
* 2 -β φ FB
JP1 = AP T e
  FB + ∆VD  
P2
4 V

At V=VFB , the factor in the bracket approaches unity and the hole current density is given
as ,

JP1 = AP*T2e-β φP2 ……………………… (19)

39
For voltages in excess of VFB , we have to consider the barrier lowering effect at the
contact no.2 due to the applied field and the hole current expression is then given as ,

Jp1 = AP*T2e-β φP2 eβ ∆ φP2 ……………………… (20)

Where,

∆ϕ P 2 =
qE m 2
=
(
q V − V FB )
…………………….. (21)
4hε S 4hε S L
Now , JPS = hole saturation current density = AP*T2e-β φP2

VFB = flat-band voltage defined earlier and ,

VRT = reach through voltage = VFB - 4V D1V D 2

Taking into account of all the above features theoretical IV characteristics of a MSM
structure is illustrated in the Fig(5).

1.7 CV characteristics :

The variation of differential capacitance of the symmetric MSM structure is mirror

symmetric w.r.t. zero bias voltage , can be analysed in two voltage ranges seperated by
reach through voltage (VRT).

For ,

V < VRT the result capacitance per unit area is capacitance in series :

C1C 2
C=
C1 + C 2

In addition to that if during processing a finite oxide layer of thickness d ox is present at

ε ε
the two contacts we then have additional capacitances Cx= S and Cy = S . For that
L L
resultant Ctotal will be series combination of C, Cx and Cy given as :

1 1 1 1 
= + +
C total  C Cx C 
 y 

40
41
FABRICATION
PROCEDURES

Chapter 3

Cleaning

WAFER SPECIFICATIONS :

Crystal Orientation: < 111>{n-type]

Substrate resistivity: 1.5 ohm cm
Water thickness: 500 ± 25 μm

42
DETAIL FABRICATION TECHNIQUES :
The above specified wafer is first subjected to detailed degreasing and cleaning cycle and
cut into pieces by means of diamond scriber along principle flat direction before being
placed in a vacuum system for metallization. The detail of the cleaning process that are
performed are given as follows :

3.1 BEAKER CLEANING :

1. All the beakers are first washed with TCE , followed by acetone and finally
rinsed thoroughly by DI water several times before use .
2. Next 10% HCL is poured in all beakers and kept for few minutes .
3. All the beakers are again rinsed by DI water and stored in chemical bench .

3.2 WAFER CLEANING :

The wafer is cleaned to make it hydrophobic and to make it free from all mechanical,
inorganic and organic contaminations. The necessary steps to clean the wafer are stated
briefly.
a) Before starting diffusion , the wafer should look physically clean with eye
estimation.The wafer is immersed in a beaker containing DI water and
ultrasonically agitated for two minuites to remove any Si dust or other loose
particles. This process is repeated twice for better result.
b) Next the wafer is subjected to ultrasonic agitation using TCE for 15 minutes,
followed by acetone and methanol to remove the airbone bacteria , wax and
variety of plasticizers.
c) Then it is boiled with hot trichloroethylene (TCE) at 80 to 85oC for 10 to 15
minutes to remove the grease.
d) TCE is removed by acetone.
e) Acetone is removed by rinsing with DI water.
f) The is transferred in a beaker containing a solution of NH 4OH , H2O2 and H2O at
the ratio of 1:1:8 , and kept it for 10-15 minutes at 80 to 85oC .This is performed
to remove any organic contaminants present.
g) The wafer is rinsed with DI water several times.
h) It is immersed in a beaker containing a solution (8 : 2 : 1 parts by volume of H2O :
H2O2 : HCl ) at 60-70 oC for about 10 minutes to remove heavy metals.
i) The wafer is dipped for few seconds in 10% solution of HF to remove the SiO 2
layer as far as possible.

43
 j) The wafer is properly rinsed with DI water and check wheather it is completely
hydrophobic or not .To make it perfectly hydrophobic within practical limitations
concentration of HF is varied.
The cleaned wafer is now ready for diffusion.

Fig1) The Ultrasonic Vibrator

Chapter 4

Metallization

The interface between a metal contact and a semiconductor must be considered for
metallization purpose. By definition an ohmic contact is one in which the magnitude of
the potential barrier , at the metal- semiconductor interface is independent of the
magnitude and direction of the current flow through the contact . The connection process
is performed using one of several vacuum deposition techniques.

4.1 Metallization Requirements :

1) Low resistance electrical contact with the silicon.
2) The metal must have a limited reactivity with the silicon.

44
3) The metal must have a high electrical conductivity.
4) The metal adhere well to the underlying silicon, silicon –dioxide, or other dielectric
oxide.
5) A pattern must be easily definable in the layer using photolithographic techniques.
6) The metallization must not exhibit electromigration.
7) The Metallization must not corrode under normal operating condition.
8) It must be possible to bond easily to the metallization , in order to allow for external
connection.
9) The metallization must be economically competitive

4.2 System requirements for vacuum generation :

1) A chamber that may be evacuated to provide a sufficient vacuum for the deposition to
take place
2) A vacuum pump (or pumps ) to reduce the gas pressure in the chamber to an
acceptable level.
3) Instrumentation to monitor the vacuum level and other system parameters
4) A method of depositing the desired layer or layers of material both glass and stainless
steel –enclosures for vacuum deposition systems are common, but stainless steel
accommodates more non standard configuration and does not break.

To obtain a sufficient vacuum, different types of pumps are used

1) Atmospheric to intermediate vacuum level (10-100 u) Rotary oil sealed pumps; The
rotary oil sealed pumps uses a rotor that is sealed against leakage by a vacuum oil. The
air left in the vacuum system enters the pump through the inlet port, is compressed and is
ejected to the atmosphere through the exhaust or discharge port..
2) Intermediate vacuum level to low vacuum level (25 u – 10 -6 mm)
Diffusion pump: In the diffusion pump, vapor from a boiler pump passes through series
of nozzles in a downward direction carrying residual atoms in the vacuum chamber with
it.
3) Low vacuum level to ultra low vacuum levels ( 10 6-10 -10mm),
Ion pump: Using a combination of an electric and a magnetic field, the ion pump
provides a method ionizing atoms and then trapping them.
The instrumentation of a vacuum deposition system must provide a method of :
1) Determining the vacuum level in the chamber .
2) Measuring the status of all valves etc, in the system.
3) Determining the thickness of any deposited layers.

4.3 Deposition techniques or sources for vacuum deposition:

Four vacuum deposition techniques are used to deposit materials in the semiconductor
industry;
1) Filament evaporation : Current flows through a filament causing first melting and then
evaporation of the material on the material.
2) Electron beam ( e-beam ) evaporation ; An intense beam of electron is used to
evaporate the material to be deposited.
3) Flash evaporation: A wire or pallets are fed on to a hot substrate , evaporating the
material on contact.

45
4) Sputtering: A gas at low pressure such as argon , bombards and dislocates atoms from
a target of the material to be deposited.
Filament evaporation is the simplest and least expensive deposition technique. However
the contamination level is often sufficiently high to interfere with the functioning of the
device. For this reason this technique is not suitable for aluminium deposition, The
technique is often used to deposit backside gold ,since contamination is not a concern in
this case.
Electron beam evaporation technique uses a focussed beam of electron to heat the
material. A high intensity beam is generated and focused on the material content .in a
hearth or crucible for high purity application of metallization to a micro electronic
substrate ,evaporation sources can be quite sophisticated . Heating the crucible might
dissolve the crucible material into the aluminium , so direct heating is avoided . Instead
an electron beam impinges on to the aluminium , heating the centre of the melt only
.Only electron come in contact with the material to be evaporated, so it can be allow
contamination process . It is a rapid process. Because of intense electron beam source
used radiation damage may occur to the devices in there substrates .These damage must
be annealed out later in the process
Flash evaporation uses a continuously fed spool of wire incident on the heated ceramic
bar for the deposition. In the sputtering method for vacuum deposition ions open inert gas
such as argon are introduced in the chamber a satisfactory vacuum level has been reached
an electric field ionizes these atoms and accelerate them towards one electrodes in the
chamber called the target, When the ion sticks the target they dislodge atoms from it
depositing them on the substrate facing the target.

4.4 Front- Side Metallisation

Metallization is performed both on the junction side of the wafer and also on the substrate
side by electron beam evaporation technique.It provides contacts for external connections
of the device.Two metals , chromium and gold are alternatively used for metallization by
successive rotation without breaking vacuum.This procedure is also called Chrome-Gold
metallization. Due to high conductivity and low degradation, gold is the most suitable
metal for this purpose.Gold atom can easily pass through the Si lattice which at high temp
will diffuse from the contact and short the p-n junction of the device.To avoid the
penetration of gold through Si , a thin layer of chromium is deposited between the Si
surface of the device and the outer gold layer. Here chromium prevents the short-circuit
breakdown by migration of gold atoms across the junction into the device at the high
temperature.It is the suitable candidate for bonding with very low series resistance.
Uniformity of coating depends on the order of vacuum and also on the substrate
temperature. We briefly mention the process steps for high vacuum creation , returning to
normal condition and the action of different parts of the vacuum system.

4.4.1 Process steps for high vacuum creation :

46
The gas inlet is opened first. After a short time , the chamber is opened and the wafer is
inserted in the wafer holder with appropriate surface facing the metal source.The gas inlet
is closed and the chamber is closed.Then the following operations are performed :
1) Main-switch is on.
2) Reset switch is on.
3) Rotary pump (RP) switch is on (Vacuum is of the order of 10-3 torr range).
4) Pirani guage switch is on (Vacuum =0.01 torr ).
5) The roughing valve (RV) is opened (Pyrani guage reading first increases and then
comes to 0.02 torr). After 10 to 12 minutes , when the reading rises upto 0.02 torr
, then the roughing valve is closed.
6) The baking valve is now opened.
7) Diffusion pump is switched on. Wait for 45 minutes till the opening guage reading
rises upto 10-6 torr.
8) Backing valve (BV) is now closed for 2-3 minuites and roughing valve is opend
for high vaccum creation and then the roughing valve is closed and baking valve
is opend.
9) The high vacuum vulve (HVV) is opened .The pinning guage reading decreases
first and then comes to 5 × 10-6 torr.Wait for 10-15 minuites till the desired
vaccum is reached.
10) Using proper amount of LNT (Liquid Nitrogen) , the pressure is further reduced
to 2 × 10-7 torr.

4.4.2 Cleaning of metals:

Before metallization the metals are cleaned by following process :

1) Chromium is cleaned by etching solution , which is a mixture of one part of
solution A and 3 parts of solution B.
2) Solution A is prepared by dissolving 50gm of KOH in 10gm of K3Fe(CN)6 in 300
cc of DI water.
3) Gold pieces are degreased by methanol and etched by aquaregia(1 part of HNO3
and 3 parts of HCL).

The wafer is inserted and heated in upto a temperature of 3500C.Substrate heating is

performed due to the following reasons. The vacuum generated inside the metallization
unit is 10-7 torr.At this pressure the percentage of water molecule in air is 98%. So after
inserting the diffused wafer , there is a probability of generation of SiO2 at the surface
level, which is totally undesired. Heating of the substrate provides the required amount of
energy to break the newly formed Si—O bonds, though they are very few. Also heating
provide very good metal contact, which is essential. Then the following steps are
performed :
1) Two metals Chromium(Cr) and Gold(Au) are kept in two small boats mounted on
a revolving circular arrangement. Mo (Molibdanum) boat is used for gold and W
(tungsten) boat is used for chromium.
2) The Gunn power supply is kept around 6.6 KV , and current is kept within
100 mA (70-80 mA).

47
 3) Chromium and gold is successfully evaporated on the wafer without breaking
vacuum.Then the sample is taken out and stored in a clean place.The gold
evaporated surface had mirror like shiny appearance.

4.4.3 Process steps for returning normal conditions :

1) The high vacuum valve is closed.

2) The diffusion pump (DP) is switched off.
3) The wafer circulation pump is opend for 45 to 60 minutes.
4) The baking valve is closed.
5) The rotary pump is switched off.
6) The water flow is stopped.
7) The wafer is cooled and taken out from the vacuum unit.

4.4.4 Electroplating :

After vacuum coating at 10-7 mm of Hg , the metallic layers are electroplated with gold to
produce an integral heat sink.The necessity of heat sink formation is first discussed :

Due to low d.c to r.f conversion efficiency of P+-N-N+ structures , an enormous amount of
heat will be dissipated around the junction. Under breakdown condition , when a large
amount of d.c. current is flowing across the junction , an efficient arrangement for
removal of heat from the junction is necessary.

Gold is highly suitable candidate for heat sink metal. At elevated temperature , the
vacuum deposited thin layer of gold forms a bond with a thick gold layer used as heat
sink. Commonly used heat sink technologies are either by electroless plating of gold or
by electroplating of gold on the evaporated gold layer close to the junction.

A methodical experimentation for selective electrolysis deposition of gold metal on

Si-substrate has been carried out in the following way :
1) The wafer with metallic layers is placed at cathode and gold is placed at anode
thickness of gold sheet is of 100 µm and area of the gold sheet is 100 cm2.
2) Gold-Potassium Cyanide solution is used as electrolyte with pH is of 5.The
solution is prepared by dissolving 0.6 gm of GPC (Gold-Potassium Cyanide) in
one liter of DI water.The acidic nature of the solution is due to addition of the
phosphoric acid (H3PO4) which is added to 2 gm in one liter.
3) The gold coated Si substrate is mounted with a black wax on a glass slide such
that all of its edges are covered with wax to avoid plating on the edges.
4) The deposition rate maintained 5µm/hr by keeping the current density constant at
2 mA/cm2. The total time taken for the electroplating is about 10 hr.
5) For uniform deposition , the solution is stirred. Because of current flow , Gold-
Potassium-Cyanide decomposes and free gold ions are deposited on the gold
coated wafer acting as cathode.
6) After electro plating , the wafer is demounted from the glass slide by dissolving
the back wax from TCE.

48
4.4.5 Etching Solution :

The etchant for this purpose is a mixture of HNO3 ,HF and CH3COOH in the ratio 8:1:1 .
Here HNO3 behaves as an oxidizing agent and HF dissolves the oxidized products.
CH3COOH dilutes the system so that etching can be better controlled.

The procedure can be stated as follows :

1) The electroplated wafer is chemically etched with that specified etching solution
for 5 minutes. This etch simultaneously polishes the surface and removes the
mechanical damage from the surface of the substrate.
2) The wafer is removed from etching solution when thickness of the substrate
becomes 10µm.
3) It is then washed with DI water thoroughly and blown dry and kept in dry place.

4.5 Back Side Metallization :

The thinned substrate wafer is again metallized (on the opposite side of electroplating )
by chromium and gold following the same procedure under a pressure of 2 × 10-7 torr.
The back side metallization provides the external electrical contact for the backside of the
device.

Fig 4.1) The Sample after Metallisation

49
 Fig 4.2) Metallisation Unit Fig4.3) Vacuum Chamber

4.6 Rotary and Diffusion Pumps :

Fig 4.5) Measuring unit of
In this section ,important steps for operation of rotary and diffusion
Diffusion Pumppumps will be
discussed.

4.6.1 Rotary Pump :

Fig4.4) Electron Beam Generator
A rotary pump helps in evacuating air to make a vacuum of the order of 1E -3 torr.A
roughing line allows I t to pump the chamber directly down to a pressure at which
vacuum can operate. Operation is done in the following way:

1) After opening the switch of rotary pumpand Pirani gauge ,the backing valve is
opened for 10 minutes .So the vacuum will decrease first and then it will come to
normal
Fig 4.6)condition.
Digital Penning Gauge
2) The backing valve is closed when the vacuum reading will come nearly upto 0.02
torr.
3) The roughing valve is opened for 10 -12 minutes and when the reading rises up to
0.02 torr, the valve is closed .

50
 4) Then the backing valve is again opened and water is allowed to flow from the
chilling water plant ( 10 - 12ºC).

Fig 4.7) Schematic Of a Rotary Pump

4.6.2 DIFFUSION PUMP:

Diffusion pump is used to enhance the quality of vacuum .It makes a vacuum of the order
of 1 E- 6 torr . It is a type of high vacuum pump. It operates in the following way:

1) Diffusion pump is switched ON and wait for at least 2 -2.5 hours till the penning
rises up to `1E- 5 to 1E -6 torr.
2) Backing valve is closed for 2-3 minutes and roughing valve is opened at this time
for helping high vacuum pressure. Then the roughing valve is closed and again
backing valve is opened.
3) High vacuum valve is opened. The Penning gauge reading decreases first and then
comes to normal condition , ie, between 1E – 5 to 1E -6 torr. Wait until desired
vacuum is reached.

51
 Fig 4.8) Schematic of Diffusion Pump

At the bottom of the diffusion pump, there is no oil reservoir. When the oil is heated ,it
vaporizes and rises through the stack to the nozzle jets . It emerges from the jet in a
downward direction. The oil molecules collide with the gas molecules giving them a
downward momentum and directing them out of the pump. There are three nozzles in the
pump. It has a final ejector stage pointed towards roughing of the pump. Water cools the
sides of the pump , reconditioning the oil vapour whenever it hits the wall. At the top of
the pump there is a clod trap cooled to L N T , which prevents oil from escaping from the
pump. It is operated at a vicious flow pressure ,the diffusion would rapidly fill the system
with oil vapour ,and so it must be kept under vacuum.

Chapter 5

Photolithography and Mesa Etching

Mask Specifications :

Circular holes
Diameter : 370 µm
Separation distance between two holes : 8 mm
Mask Material : Thin Al sheet
Mask Thickness : 0.2mm

52
5.1 Photolithography :

The purpose of lithographic process is to transfer the mask features to the surface of Si
wafer.This process is performed in the following manner :

a) The wafer is subjected to photoresist (here we apply negative photoresist) and

then it was rotated at 2500 rpm in a vacuum chamber in order to spread the
photoresist uniformly using the photoresist spinner.Angular speed of the spinner
depends on viscosity of the photoresist.

b) After coating , it was exposed to U-V light through a photomask for 20 to 30

minutes at 60 to 700C . This process is known as pre-baking.Under exposition of
light , the wafer became hard.

c) Next it was subjected to a developer solution which dissolves the unexposed part
of the photoresist since we used negative resist.This step is termed as developing.

d) After removing the developer by rinsing , it was inspected under microscop then
it was post baked in order to dry out for at least half an hour at 80 to 1200C.Thus
we obtained P+-N-N+ structure which is our requirement for our experimental
work.Post baking makes the image permanent .We enlist here the schematic
diagrams for the photolithographic process which reveals how wafer is processed
using negative photo resist.

5.2 Mesa Etching :

After photolithography , some porsion of the silicon is etched out in a very selective way
and the porsion under the resist mask remains unaffected during the etching process.
The process is carried out in the following way :

a) The gold from unmasked portion is removed by gold etchant and subsequently the
chrome by chrome etchant.The chrome etchant is prepared from the two
solutions – one by dissolving 50 gm of KOH in 100 cc DI water and other by
dissolving 10 gm of KFe(CN)6 in 300 cc of Di water. Then 1 part of the first
solution is mixed up with 3 part of the second solution by volume.

b) Next, using the Si etchant (a mixture of HNO3 ,HF and CH3COOH in the ratio
8:1:1 ) , the Si lying below the unmasked portion is etched up to N+ substrate and
the etching results the formaton of mesa structure for the device.This mesa
etching leads to a large no of p-n junction diodes over the N+ substrate.
c) The wafer is then mounted over a plate by means of wax and placed below a
wire-saw machine attached with the microscope.The devices are physically
separated by using th wire-saw.

53
d) The devices are cleaned with acetone several times to remove the wax and then
rinsed thoroughly in DI water.

e) The devices are taken dried out.

54
 Characterizatio
n
&
Sample
Analysis

Chapter 6
Study of Surface morphology
6.1 Theory of SEM

55
The Scanning Electron Microscope (SEM) is a microscope that uses electrons rather than
light to form an image. There are many advantages to using the SEM instead of a light
microscope.
The SEM has a large depth of field, which allows a large amount of the sample to be in
focus at one time. The SEM also produces images of high resolution, which means that
closely spaced features can be examined at a high magnification. Preparation of the
samples is relatively easy since most SEMs only require the sample to be conductive. The
combination of higher magnification, larger depth of focus, greater resolution, and ease of
sample observation makes the SEM one of the most heavily used instruments in research
areas today.

 The Electron Source

The electron beam comes from a filament, made of various types of materials. The most
common is the Tungsten hairpin gun. This filament is a loop of tungsten which functions
as the cathode. A voltage is applied to the loop, causing it to heat up. The anode, which is
positive with respect to the filament, forms powerful attractive forces for electrons. This

56
causes electrons to accelerate toward the anode. Some accelerate right by the anode and
on down the column, to the sample. Other examples of filaments are Lanthanum
Hexaboride filaments and field emission guns.

 Beam's Path through the Column

A beam of electrons is generated in the electron gun, located at the top of the column,
which is shown above. This beam is attracted through the anode, condensed by a
condenser lens, and focused as a very fine point on the sample by the objective lens. The
scan coils are energized (by varying the voltage produced by the scan generator) and
create a magnetic field which deflects the beam back and forth in a controlled pattern.
The varying voltage is also applied to the coils around the neck of the Cathode-ray tube
(CRT) which produces a pattern of light deflected back and forth on the surface of the
CRT. The pattern of deflection of the electron beam is the same as the pattern of
deflection of the spot of light on the CRT.

57
The electron beam hits the sample, producing secondary electrons from the sample.
These electrons are collected by a secondary detector or a backscatter detector, converted
to a voltage, and amplified. The amplified voltage is applied to the grid of the CRT and
causes the intensity of the spot of light to change. The image consists of thousands of
spots of varying intensity on the face of a CRT that correspond to the topography of the
sample.

58
 SEM Ray Diagrams

These schematics show the ray traces for two probe-forming lens focusing
conditions: small working distance (left) and large working distance (right). Both
conditions have the same condenser lens strength and aperture size. However, as the
sample is moved further from the lens, the following occurs:
• the working distance S is increased
• the demagnification decreases
• the spot size increases
• the divergence angle alpha is decreased

The decrease in demagnification is obtained when the lens current is decreased, which in
turn increases the focal length f of the lens. The resolution of the specimen is decreased
with an increased working distance, because the spot size is increased. Conversely, the
depth of field is increased with an increased working distance, because the divergence
angle is smaller.

59
 Signal Detection

While all these signals are present in the SEM, not all of them are detected and used for
information. The signals most commonly used are the Secondary Electrons, the
Backscattered Electrons and X-rays.

 Using a Vacuum

When a SEM is used, the column must always be at a vacuum. There are many reasons
for this. If the sample is in a gas filled environment, an electron beam cannot be
generated or maintained because of a high instability in the beam. Gases could react with
the electron source, causing it to burn out, or cause electrons in the beam to ionize, which
produces random discharges and leads to instability in the beam. The transmission of the
beam through the electron optic column would also be hindered by the presence of other
molecules. Those other molecules, which could come from the sample or the microscope
itself, could form compounds and condense on the sample. This would lower the contrast
and obscure detail in the image.

A vacuum environment is also necessary in part of the sample preparation. One such
example is the sputter coater. If the chamber isn't at vacuum before the sample is coated,
gas molecules would get in the way of the argon and gold. This could lead to uneven
coating, or no coating at all.

60
 Sample Chamber

The photo on the left shows the sample chamber located at the base of the column.

 Objective Lens

The lens that focuses the beam of electrons towards the sample is in the center of the
picture. The parts off to the right of the sample are different detectors. One is for
detecting the secondary electrons and the other is for detecting the backscattered
electrons. The operator has the power to choose and switch detectors for use on each
sample. Using the secondary electron detector produces a clear and focused topographical
image of the sample. The backscatter electron detector produces an image that is useful
when determining the make-up of the sample. Each element in the sample appears as a
different shade, from almost white to black.

61
 Stage

A prepared sample is mounted on a specimen stub and placed on the stage.

 Specimen Preparation

There are two basic types of SEM's. The regular SEM, which we have in the Iowa State
Materials Science Department, requires a conductive sample. An environmental SEM can
be used to examine a non-conductive sample without coating it with a conductive
material. Three requirements for preparing samples for a regular SEM such as in the Iowa
State Materials Science Department are:
• Remove all water, solvents, or other materials that could vaporize while in the
vacuum.
• Firmly mount all the samples.
• Non-metallic samples, such as bugs, plants, fingernails, and ceramics, should be
coated so they are electrically conductive. Metallic samples can be placed directly
into the SEM.

 Mounting the Specimen

Any specimen, whether it has been sputter coated or is naturally conductive, must be
firmly attached to the specimen support before being viewed in the SEM. Attention to
detail in the mounting proceedure is very important if a researcher desires a quality result.

62
 • Non-conductive samples
Make sure the support (specimen stub) is clean before use and also check to make sure
the stub you are using is compatible with the stage of the SEM you will be using.Place
the specimen on the stub before the sputter coating procedure. This will increase the
conductivity and therefore the quality of your results.

• Conductive samples
The specimen stub you choose should be of a material that will not interfere with the
backscattered-electron and x-ray signals that will be emitted from the specimen. Again,
make sure the stub is clean and compatible with the SEM you are using.
Additional Notes
For some samples it will be necessary and perhaps more convenient to place the
specimen on a substrate that will be mounted on the stub. Substrate materials range from
glass and plastic cover slips to metal and crystalline disks, plastics, waxes and many
membrane filters. Since it is frequently necessary to attach the specimen or substrate to
the stub, a variety of adhesives is available for this purpose. You should make sure to
choose an adhesive that will not decrease the quality of your results.

 Sputter Coater

The sputter coater is used to coat non-metallic samples (bugs, plants, human hair, etc.)
with a thin layer of gold. This makes them conductive, and ready to be viewed by the
SEM. If the samples are metallic, they can simply be mounted and placed in the SEM.

63
6.2 Experimental observations of the sample with SEM

A Schematic of the sample structure is shown which illustrates the two samples used for
SEM analysis.The are as follows :-

64
 Fig1 :- top View of the a single metal dot at a resolution x95. The lines on the
metal top have been formed due to scratches produced while the metal zig
used to make contact during IV characteristics study .

 Fig2 :- View of the metal dot at Resolution x 1000 . The surface roughness
becomes apparent.

65
 Fig3 :- Metallised Part at resolution x 10,000. This figure shows the region of
metallisation where unwanted scratches were formed due to the contact zig.
Readings for IV characteristics near these parts should be avoided.

 Fig4 :- Metallised part at a resolution of x30,000. This figure shows a uniform

metallised part. Mainly this is the part where there were no scratches due to
the contact zig.

66
 Fig5 :- Cross Sectional View of the Metal Semiconductor junction (upper
junction) showing the thickness of both the layers.

 Fig6 :- Cross Sectional View of the Metal Semiconductor junction (lower

junction) .The thickness of the metallised layer is marked. It can be seen that
this metal semiconductor junction is much smoother than that in Fig4
because there is no scriber marks. The way the sample is to be broken for
cross sectional SEM is very important.

67
6.3 EDX Analysis

Theory to be prepared ………

68
6.4 Experimental study of sample with EDX

 Fig1 : The three psitions whre EDX was performed. Pos 001 : Top metallised
surface,
Pos 002 : Cross Section of the upper metal semiconductor contact , Pos 003 : Cross
Section of the lower metal semiconductor contact.

69
 Fig2 :- The fig shows the plot of Energy Vs Total Count of sample at position
001 . It also shows the Quantitative measure of the different components
present at this position. The presence of Carbon and Oxygen are to be
ignored because they have crept in due to the fact that the sample mount is of
carbon. Both the presence of Gold,Chromium (metallisation elements) and
Silicon (Substrate element) are detected in a proportion as expected.

70
 Fig 3 :- Qualitative Analysis of the elements present in Pos 001 :-

71
  Fig4 :- Quatitative Analysis of the elements present in Pos 001 :-

Fig5 :- Analysis of Pos 002

72
 Fig 6 :- Energy Vs Sample Count Plot for Pos 002 .

73
 Fig 7 :- Qualitative Analysis of Pos 002 of the sample

74
 Fig 8 :- Quantitaive Analysis of Pos 002 of Sample

 Fig9 :- Analysis of Pos 003

75
 Fig 10 :- Energy Vs Sample Count Plot for Pos 003

76
 Fig 11 :- Qualitative Analysis of Pos 003 of the sample

77
 Fig 12 :- Quantitative analysis of Pos003 of the sample

78
 Fig 13 :- Final Discussion of the presence of desired elements at the three
positions . It is evident from the chart below that the presence of Au and Cr
(Metallisation elements) is profound in Pos 001. The Pos 002 and 003 being
cross sectional positions the amount of metallisation elements to the substrate
Si is much smaller as the metallised layer thickness is much smaller (about 2
µm) than the substrate (about 20 µm) . Still for pos 003 Au has been detected
the reason being that the lower layer(pos003) contact is much smoother than
the upper layer contact (pos 002).

79
 Chapter 7

Experimentally obtained Values for IV and CV characteristics

7.1 IV characteristics :-
The experimental setup for the measurement of IV has been shown in the schematic
below. It was difficult to perform the experiment under totally dark condition because of
the unavailability of proper dark room. Also due to the unavailability of proper
Wavelength source the illumination was achieved only through a Solid State Laser diode
in the Red optical frequency range commonly available from the market.

Schematic Diagram Showing Circuit Arrangement Used to Measure I-V Characteristics

80
 IV Characteristics of MSM structure (Dot2)

Without Illumination With Illumination

Voltage(V) Current(mA) Current(mA)
0.1 7 14
0.2 19 25
0.3 31 37
0.4 47 52
0.5 57
0 0 0
-0.1 -20 -15
-0.2 -37 -31
-0.3 -50 -45
-0.4 -63 -60

Voltage of MSM
IV Characteristics Current (mA)
structure (Dot2)
(volts)
With Illumination
-0.6 -38
-0.5 -33
-0.4 -26
-0.3 -20
-0.2 -12
-0.1 -6
0 -1
0 3
0.1 5
0.2 11
0.3 18
0.4 25
0.5 31
0.6 37
0.7 43

7.2 CV Characteristics:

Bias Voltage (volts) Device Capacitance (pF)

0 1022
1 965

81
 2 900
3 843
4 788
5 743
6 664
7 630
8 586
9 557
10 550
11 542
12 540
13 530
14 528
15 480
16 472
17 460
18 455
19 428
20 420

Conclusion

The MSM Device fabricated has studied for IV and CV characteristics. The results
obtained were not immensely satisfactory and I think that there were certain reasons for

82
it. Firstly the Contact Zig that had been used made a very rough contact and one could
evidently find the scratches that had been formed at the time of measurement from the
SEM Pictures of the sample taken after the measurements. After metallization proper
annealing need be done to create a better Schottky barrier otherwise Ohmic contact
becomes a threat. Due to unavailability of proper annealing facilities I ahd to skip that
process. Given the Photolithography facilities availablei n the lab I had to go for circular
dots. An interdigited metal structure would have yielded better results and usually all
MSM structures fabricated and reported in journals are of that type.The sample
preparation for cross sectional SEM analysis is very important. The sample had been
scribed and broken which produced difficulty in distinguishing the metal and
semiconductor junction. However we could ultimately distinguish that.I was eager to
perform another metallaisation and prepare another sample taking into consideration my
experience in preparing the first sample. However time became a constraint and also the
metallization unit in our lab was disfunct for a significant period hindering speed of
work.

Discussion and Future Scope of Work :

A detailed theoretical study has been made in my report and rigorous derivations for the
expression of current and capacitance of interdigited MSM structure have been
explained.One can simulate those expressions and and obtain the theoretical
characteristics. The order of current is an important feature different papers on different
MSM structures show various natures of plot. Fabrication of Interdigited structure
requires preparation of the mask in the µm range using AutoCAd or other design
software. After the layout, we have to take a print out of that layout to scale in a
transparency and finally get our desired mask. This task is also important given the
facilities available to us with regards choice of mask. There is requirement of proper dark
room to study the dark current response and also a range of optical wavelength sources
are required to study the illumination response.The CV characteristics are better studied
in a CV plotter rather than the crude CV apparatus used in our measurement.

Bibliography
1. Chou, S. Y., Liu, Y. and Fischer, P. B., Appl. Phys. Lett. 61,477 (1992).

83
2 Levine, B. F., Wynn, J. D., Klemens, F. P. and Sarusi, G., Appl. Phys.Lett. 66,2984
(1995).

3 Chou, S. Y. and Liu, M. Y., IEEE J. Quantum Electronics 28

4 Physics of Semiconductor Devices, Second edition, S. M. Sze, Wiley & Sons, 1981,
Chapter 5.

5. Device Electronics for Integrated Circuits, Second edition, R.S. Muller and T. I.
Kamins, Wiley & Sons, 1986, Chapter 3.

6. Physica Scripta. Vol. T69, 163-166, 1997

A Comparative Study of Si and GaAs Metal-Semiconductor-Metal Photodetectors
K. Honkanen,' T. Siirtola,' T. Majamaa,' A. Hovinen' and P. Kuivalainen','

7. “Fabrication and modelling of SOI and GaAs MSM Photodetectors and GaAs based
photreceivers.” - Dissertation for the degree of Doctorate in Technology by Katri.
Honkanen, Helsinki University of of Technology.

8. “Current transport in Metal – semiconductor Barriers”-C. R. Crowell & S. M. Sze

solid state electronics , 9, 1035 . ( 1966 )

9. Solid State Electronic Devices. B .G .Streetman

10. Semiconductor Opto-Electronic Devices .Pallab Bhattacharya.

11. VLSI Fabrication principles , S K Gandhi.

84
12. “Fabrication and characterization of Al-Si-Al MSM device” --- MTech Project of
Pranab Hazra under the guidance of Prof. J.P. Bandyopadhyay. (2007 IRPE, CU)

13. http://www.mtmi.vu.lt/pfk/funkc_dariniai/diod/schottky.htm

13. http://www.princeton.edu/~chouweb/newproject/page18.html

85