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21.9 A Fully Integrated BiCMOS PLL for 60 GHz An important issue is the optimization of the loop bandwidth.
Wireless Applications The high PLL output frequency results in a large PLL division
factor if a commercial crystal oscillator is used to drive the PLL.
This enhances the jitter contributions of the input signal and the
Wolfgang Winkler, Johannes Borngräber, Bernd Heinemann,
charge pump, which are low-pass filtered in a PLL making a nar-
Frank Herzel
row-band PLL desirable. However, due to the absence of high-
quality passives in an integrated PLL, the VCO phase noise,
IHP, Frankfurt (Oder), Germany
which is high-pass filtered in the PLL, will significantly degrade
the PLL jitter performance. As shown in [8], the corresponding
An integrated PLL tunable from 54.5 to 57.8GHz manufactured
rms phase error contribution (in radians) can be deduced from
in a SiGe:C BiCMOS technology is presented. The PLL is aimed
the single-sideband phase noise SSSB [1/Hz] of the free-running
at wireless transceivers in the unlicensed band from 57 to 64GHz
VCO measured at the offset ∆f from the carrier, and the loop
[1]. Existing 60GHz transceivers are based on compound semi-
bandwidth fL [Hz] according to
conductors [2]. By contrast, silicon-based solutions will enable a
high integration level at low cost. The known 60GHz systems uti- π ⋅ S SSB
VCO
406 • 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE.
ISSCC 2005 / February 9, 2005 / Salon 7 / 12:00 PM
Figure 21.9.1: Circuit schematic of the PLL. Figure 21.9.2: Chip micrograph of the fully integrated PLL.
Figure 21.9.3: VCO output frequency as a function of coarse tuning voltage. Figure 21.9.4: Output spectrum of PLL including 20dB external attenuation. 21
Figure 21.9.5: High-resolution output spectrum around the carrier Figure 21.9.6: Plot of rms phase error due to VCO noise versus loop
including 20dB external attenuation. bandwidth fL.