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I. Inroduction
A Viterbi decoder [1, 2] is an important target for power reduction in many low-power communication devices. It can account for more than one-third of power consumption during baseband processing in current generation cellular telephones [3]. As integrated circuits continue to become smaller and faster, the appeal of higher complexity Viterbi decoders for higher memory order convolutional codes increases. Higher memory order codes can achieve superior coding performance without requiring precious additional channel bandwidth. However, to counteract the exponential dependence of Viterbi decoder complexity on higher memory order in low-power designs, good power reduction methods that exploit variations in the communications system are needed. In order to overcome this problem, the adaptive Viterbi Decoder (AVD) [4] [11] has been developed. This Decoder reduces the average number of computations required per bit of decoded information while achieving comparable bit error rates (BER) versus Viterbi algorithm implementations. As is the case in many designs today, significant untapped power reduction potential lies in dynamically varying a AVD implementation according to real-time changes in system characteristics. Low-power AVD is a well-studied subject. Power reduction in AVDs has been achieved by either reducing the number of states (reduced-state sequence decoder) [3], the size of survivor memory [4], or the number of trellis paths (limited-search trellis) [5] at the expense of increased BER and/or reduced throughput. Other approaches include
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scarce state transition [6] where the most-likely path passes through the zero states most of the time allowing shorter survivor memories and efficient limited-search trellis decoding [7]. In this paper, we present energy-efficient architectures for the fast add-compare-select unit (FACSU), For 128 State rate convolutional code for constraint length k=8, Nmax=8, Threshold=17 and Truncation length =40
In the implemented decoder, the expected symbol value (BMselect) is used to select the appropriate branch metric from the BMG, as shown at the left in Figure 2. This branch metric value is combined with the path metric of its parent present state to form a new path metric, di. At each Trellis stage, the minimum-value surviving path metric among all path metrics for the preceding Trellis stage, dm, is computed. New path metrics are compared to the sum dm + T to identify path metrics with excessive cost. Comparators are then used to determine the life of each path based on the threshold, T.
Figure 2: ACS unit of adaptive Viterbi decoder
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If the threshold condition is not satised by path metric dm + T, the corresponding path is discarded. Once the paths that meet the threshold condition are determined, the lowest-cost Nmax paths are selected. Sorting circuitry is eliminated by allowing feedback adjustments to the parameter T for each received symbol. If the number of paths that survive the threshold is less than Nmax, no iteration is required. As show in Figure 4, for stages when the number of paths surviving the threshold condition is greater than Nmax, T is iteratively reduced by 2 for the current Trellis stage until the number of paths surviving the threshold condition is equal to or less than Nmax. The T value is reset to its original value prior to the Processing of the next Trellis stage. Appropriate values for T and Nmax were determined in previous work [8], so that T reduction is needed infrequently (for less than 5% of symbols). The output of the ACS units includes path valid signals which indicate which of the 2 * Nmax paths have survived pruning. Details regarding other decoder components can be found in [8].
So the 5b input to LSB is generated and the bit wise comparison is done in the similar way as in MSB. While comparing all the bits are equal, the lowest bit value path is selected. The RCS decision is made based on 4bit MSB of path metrics Ai and Aj respectively. The correct decision depends upon 4bit LSBS of updated path metrics Ai(o:3) and Aj(0:3) as the propagated carries will make the 4bit MSB Ai(7:4) and Aj(7:4) equal. The wrong decisions will affect the decoder performance.
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The ACS unit is the most important part and is different from common viterbi decoder, and its structure is shown in detail in Fig4. Adaptive Viterbi decoder consists of three parts as shown in fig 4. When two input bits that represent the outputs of the encoder have been transmitted are received from the channel, the branch metric generator (BMG) calculate the Hamming distance between the received bits and the 2K possible expected values. This path will be sent to next module to calculate , and then select the surviving paths . After accepting the new branch metrics from BMG, the main task of the Add-Compare-Select (ACS)module is to update the path metric. In conventional add compare select unit while comparing the two path cost values, 4bit branch metric is added to eight bit path metric to generate the eight bit output with carry, and discard the paths that dont satisfy the two criterias for path retention.ie 1. Path is retained if path is less than dm+T 2. The total number of survivor path is limited. The operation needed is to find the minimum cost among all surviving paths in the previous trellis stage by updating the threshold value dm. From the information of surviving paths, we can use decoding method such as register-exchange or trace-back, to generate the output sequences. In Fast Add Compare Select unit when two paths are compared, first MSB of both path metrics are compared bitwise. If values of bit wise comparison differs low cost path is selected. If all the values of MSB are equal LSB of branch metric is added to path metric to generate the output with carry. The selection mux is used to select the low cost path. FACSU is better than conventional ACSU computation of low path cost is minimized there by consuming the power.
V. Implementation Analysis
Power consumption values for AVA decoers were implemented in XC3S50 were determined with the following equation: Power = ((0.02xf) + 0.09) x A x V. Where f is the design frequency, A is the percentage of used device flip flop, and the I/O multiplied by their switching activity of 30% was used with a supply voltage of 5v. The implementation is done for both Adaptive viterbi decoder conventional Add Compare Select Unit and
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Fast Add Compare Select Unit. In Table 1 we are comparing the both Conventional ACSU and FACSU. .Comparision report shows the number of CLB slices, LUT,power consumption, number of filpflop and latency utilized for both ACSU and FACSU. Here we have analysed the process in xilinx project navigator XC3S50PQ208 with the speed -5 for high performance industry standard and simulated in Modelsim 6.2 .
Table 1:
S.NO 1. 2. 3. 4.
Conclusion
The power consumption is minimized by implementing Fast Add Compare Select Unit in Adaptive Viterbi Decoder. Our future work is to implement this architecture in digital data communication receivers to reduce the power consumption and to enhance the performance of the system,.
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] Design Analysis of Viterbi and Adaptive Viterbi Decoder. IJERIA ISSN 0974-1518,VOL 3,N0 III (August 2010), pp, 403-412 F. Chan and D. Haccoun, Adaptive Viterbi decoding of convolutional Codes over memory less channels, IEEE Transaction on Communications, vol. 45, no. 11, pp. 13891400, Nov. 1997. S. J. Simmons, Breath-rst Trellis decoding with adaptive effort, IEEE Transactions on Communications, vol. 38, no. 1, pp. 312, Jan. 1990. S. Nanda, K. Balachandran, and S. Kumar, Adaptation techniques in Wireless packet data services, IEEE Communications Magazine, vol. 38, No. 1, pp. 5464, Jan. 2000. D. Matolak and S. Wilson, Variable-complexity Trellis decoding ofbinary convolutional codes, IEEE Transactions on Communications, vol. 44, no. 2, pp. 121126, Feb. 1996. S. Simmons, An error bound for reduced-state Viterbi decoding of TCM Codes,IEEECommunicationsLetters, vol. 3, no. 9, pp. 266268, Sept.1999. A. Michelson and A. Levesque. Error-control Techniques for Digital Communication. John Wiley and Sons, New York, NY, 1985. B. Pandita and S. K. Roy. Design and Implementation of a Viterbi Decoder Using FPGAs. In Proceedings of IEEE International Conference on VLSI Design, pp 611614, Jan. 1999. J. Proakis. Digital Communications. McGraw-Hill, New York, NY, 1995.