Inter-Integrated Circuit (I2C) Design

of Zilogs Z8 Encore! XP
-------------------------

A Thesis
Presented to the
Department of Electronics & Communications Engineering
College of Engineering
De La Salle University
-------------------------

In Partial Fulfillment of
The Requirements for the Degree of
Bachelor of Science in Electronics and Communications Engineering
-------------------------

By

CARIO, Franz Marco R.

MALUBAY, Mary Joyce V.
RAMA, Noel Jazz P.
RAMIREZ, Daisy Zari D.

August 26, 2011

TABLE OF CONTENTS
1 INTRODUCTION

1.1 Background of the Study

1.2 Statement of the Problem

1.3 Significance of the Problem

1.4 Objectives

1.4.1 General Objectives

1.4.2 Specific Objectives

1.5 Scope and Delimitations

1.6 Description of the Project

2 REVIEW OF RELATED LITERATURE

2.1 IC Development in the Philippines: Industry and Academe 9

2.2 The Development of Integrated Circuit

10

2.3 The Inter-Integrated Circuit Design

11

2.4 The Inter-Integrated Circuit Simulation and Implementation

13

2.5 Existing I2C Devices

15

2.5.1. I2C Applications

15

2.5.2. I2C Bus Analyzer based on Personal Digital Assistant

15

2.5.3. Field Programmable Gate Array (FPGA) Interface Model

for I2C Bus

16

3 THEORETICAL CONSIDERATIONS

17

3.1 Serial Communication

17

3.2 Inter-integrated Circuit

17

3.2.1 General Operation

18

3.2.2 Interfacing I2C with Devices

19

3.3 Zilog Z8 Encore! F64XX Series Development Board

20

3.4 I2C in Zilog Z8 Encore! F64XX Series

21

3.4.1 Features

21

3.4.2 Operation

22

3.4.2.1 Write Operation

23

3.4.2.2 Read Operation

26

3.4.2.3 SDA/SCL Timing

29

3.4.3 Registers

29

3.4.3.1 Data Register 30

3.4.3.2 Status Register

30

3.4.3.3 Control Register

32

3.4.3.4 Baud Rate High and Low Byte Registers

33

3.4.3.5 Diagnostic State Register

34

3.4.3.6 Diagnostic Control Register

34

3.4.4 Interrupts

35

3.5 Electrically Erasable Programmable Read-Only Memory (EEPROM)

35

3.6 ATMEL 24C04 (AT24C04)

37

3.7 Shift Register

39

3.8 DeMorgans Theorem

42

4 DESIGN CONSIDERATIONS

43

4.1 I2C System Block

43

4.2 I2C RTL Design

45

4.2.1 Interfacing_Block

45

4.2.2 Signalling_Block

47

4.2.3 Base Block

49

4.2.3.1 ACTION_NO_OP Block 50

4.2.3.2 ACTION_START Block

50

4.2.3.3 ACTION_WRITE Block

51

4.2.3.4 ACTION_READ Block

53

4.1.3.5 ACTION_IDLE Block

54

4.1.3.6 ACTION_NACK Block

55

4.1.3.7 ACTION_STOP Block

56

4.3 I2C RTL Implementation

57

4.3.1 Interfacing_Block

57

4.3.2 Signalling_Block

62

4.3.3 Base_Block

67

4.4 I2C CMOS Design

72

4.4.1 Signalling_Block

72

4.4.2 Base_Block

77

4.4.2.1 ACTION_START Block

77

4.4.2.2 ACTION_WRITE Block

81

4.4.2.3 ACTION_READ Block

83

4.4.2.4 ACTION_IDLE Block

85

4.4.2.5 ACTION_NACK Block

88

4.4.2.6 ACTION_STOP Block

90

4.5 Binary Counter

92

4.6 Registers

94

4.6.1 Shift Register

94

4.6.2 Data Register 97

4.6.3 Control Register

100

4.6.4 Status Register

101

4.7 I2C CMOS Implementation

102

4.8 I2C CMOS Layout

107

5 EXPERIMENTS AND ANALYSIS OF RESULTS

108

5.1 ZILOG Performance Results

108

5.1.1 Write Operation

108

5.1.2 Read Operation

116

5.2 XILINX Simulated Results

124

5.2.1 Write Operation

124

5.2.2 Read Operation

127

5.3 FPGA Performance Results

130

5.3.1 Write Operation

131

5.3.2 Read Operation

137

5.4 Pre-Layout Performance Results

143

5.4.1 Write Operation

144

5.4.2 Read Operation

148

5.5 Data Comparison of Zilog, FPGA and Pre-Layout Simulation

153

5.5.1 Write Operation

153

5.5.2 Read Operation

156

5.6 Post- Layout Simulation

159

5.6.1 Write Operation

160

5.6.2 Read Operation

165

5.8 Data Comparison of Zilog, FPGA and Post-Layout Simulation

170

5.8.1 Write Operation

170

5.8.2 Read Operation

173

6 CONCLUSION, RECOMMENDATIONS, and FUTURE DIRECTIVES

176

Bibliography

179

LIST OF APPENDICES
Appendix A I2C Controller Zilog Z8 Encore! XP F64XX Series Product
Specification
Appendix B Zilog Application Note AN0126 Using the Z8 Encore! XP
MCU as an I2C Bus Master
Appendix C Zilog Applicaion Note AN0126 Program Listings
Appendix D Interfacing Block of Write Operation VHDL Simulation
Program Listings
Appendix E Interfacing Block of Read Operation VHDL Simulation
Program Listings
Appendix F Signalling_Block VHDL Simulation Program Listings
Appendix G Base_Block VHDL Simulation Program Listings
Appendix H SPICE Simulation Program Listings
Appendix I Post-Layout Simulation Program Listings
Appendix J Chapter 5 Data
Appendix K Atmel AT2401A/02/04/08A/16A I2C EEPROM Data Sheet

LIST OF FIGURES

Figure 1.1 Microcontroller without I2C and microcontroller with I2C 3

Figure 1.2 Inter-Integrated Circuit Block Diagram

Figure 2.1 Production process of integrated circuit

11

Figure 3.1 Interfacing Master and Slave

20

Figure 3.2 Z8 Encore XP F644XX Series Block Diagram

20

Figure 3.3 Start and Stop Timing Condition

23

Figure 3.4 7-Bit Addressed Slave Data Transfer Format for Write Operation

24

Figure 3.5 Timing Diagram

24

Figure 3.6 Write Operation 25

Figure 3.7 7-Bit Addressed Slave Data Transfer Format for Read Operation

Figure 3.8 Timing Diagram

27
27

Figure 3.9 Read Operation

28

Figure 3.10 SDA / SCL Timing Diagram

29

Figure 3.11 Data Register

30

Figure 3.12 Status Register 30

Figure 3.13 Control Register 32
Figure 3.14 Baud Rate High Byte Register

33

Figure 3.15 Baud Rate Low Byte Register

33

Figure 3.16 Diagnostic State Register

34

Figure 3.17 Diagnostic Control Register

34

Figure 3.18 ATMEL AT24C04 8-lead TSSOP

37

Figure 3.19 4-bit Serial In to Serial Out Shift Register 40

Figure 3.20 4-bit Serial In to Parallel Out Shift Register

41

Figure 3.21 4-bit Parallel In to Serial Out Shift Register

41

Figure 3.22 4-bit Parallel In to Parallel Out Shift Register 42

Figure 3.23 Implementation of De Morgans Theorem

42

Figure 4.1 I2C System Block Diagram

44

Figure 4.2 Write Cycle

46

Figure 4.3 Read Cycle 47

Figure 4.4 State Diagram of Signalling_Block 49
Figure 4.5 State Diagram ACTION_START

51

Figure 4.6 State Diagram ACTION_WRITE

52

Figure 4.7 State Diagram ACTION_READ

54

Figure 4.8 State Diagram ACTION_IDLE 55

Figure 4.9 State Diagram ACTION_NACK

56

Figure 4.10 State Diagram ACTION_STOP 57

Figure 4.11 RTL block of Interfacing_Block 62
Figure 4.12 RTL block of Signalling_Block 67
Figure 4.13 RTL block of Base_Block 71
Figure 4.14 Signalling Block Circuit Implementation 76
Figure 4.15 ACTION_START Circuit Implementation

80

Figure 4.16 ACTION_WRITE Circuit Implementation

82

Figure 4.17 ACTION_READ Circuit Implementation 85

Figure 4.18 ACTION_IDLE Circuit Implementation 87
Figure 4.19 ACTION_NACK Circuit Implementation

90

Figure 4.20 ACTION_STOP Circuit Implementation 92

Figure 4.21 Design of 3-bit Binary Counter

93

Figure 4.22 Bidirectional Shift Register

96

Figure 4.23 Representation of a bit in Data Register

97

Figure 4.24 Data Register

99

Figure 4.25 Control Register 101

Figure 4.26 Status Register 102

Figure 4.27 I2C Design Layout 107
Figure 5.1 Zilog Experimental Set-Up

108

Figure 5.2 Hyper Terminal Window I2C Write Operation

109

Figure 5.3 Zilogs I2C Write Operation

110

Figure 5.4 Zilogs I2C Write Operation (Part 1 of 3) 111

Figure 5.5 Zilogs I2C Write Operation (Part 2 of 3)

112

Figure 5.6 Zilogs I2C Write Operation (Part 3 of 3)

113

Figure 5.7 Zilogs I2C Page Write Operation

114

Figure 5.8 Hyper Terminal Window I2C Read Operation

117

Figure 5.9 Zilogs I2C Read Operation 118

Figure 5.10 Zilogs I2C Read Operation (Part 1 of 4)

119

Figure 5.11 Zilogs I2C Read Operation (Part 2 of 4)

120

Figure 5.12 Zilogs I2C Read Operation (Part 3 of 4)

121

Figure 5.13 Zilogs I2C Read Operation (Part 4 of 4)

122

Figure 5.14 Write Simulation in ISim

124

Figure 5.15 First state of Write Operation in ISim

125

Figure 5.16 Second state of Wrtie Operation in ISim

125

Figure 5.17 Third state of Write Operation in ISim 126

Figure 5.18 Fourth state of Write Operation in ISim

126

Figure 5.19 Last state of Write Operation in ISim

126

Figure 5.20 Read Operation in ISim

127

Figure 5.21 First State of Read Operation in ISim

128

Figure 5.22 Second State of Read Operation in ISim 128

Figure 5.23 Third State of Read Operation in ISim

128

Figure 5.24 Fourth State of Read Operation in ISim 128

Figure 5.25 Fifth State of Read Operation in ISim

129

Figure 5.26 Last State of Read Operation in ISim 129

Figure 5.27 SPARTAN 3E FPGA Set-up

131

Figure 5.28 SPARTAN 3E FPGA Write Operation

132

Figure 5.29 SPARTAN 3E FPGA Write Operation (Part 1 of 3)

133

Figure 5.30 SPARTAN 3E FPGA Write Operation (Part 2 of 3) 134

Figure 5.31 SPARTAN 3E FPGA Write Operation (Part 3 of 3) 135
Figure 5.32 HyperTerminal Read Operation 136
Figure 5.33 Hyper Terminal Window I2C Write Operation by Zilog 138
Figure 5.34 SPARTAN 3E FPGA Read Operation

139

Figure 5.35 SPARTAN 3E FPGA Read Operation (Part 1 of 3)

140

Figure 5.36 SPARTAN 3E FPGA Read Operation (Part 2 of 3)

141

Figure 5.37 SPARTAN 3E FPGA Read Operation (Part 3 of 3)

142

Figure 5.38 Pre-Layout Simulation of Write Operation (Part 1 of 5) 144

Figure 5.39 Pre-Layout Simulation of Write Operation (Part 2 of 5) 145
Figure 5.40 Pre-Layout Simulation of Write Operation (Part 3 of 5) 145
Figure 5.41 Pre-Layout Simulation of Write Operation (Part 4 of 5) 146
Figure 5.42 Pre-Layout Simulation of Write Operation (Part 5 of 5) 147
Figure 5.43 Pre-Layout Simulation of Read Operation (Part 1 of 6) 149
Figure 5.44 Pre-Layout Simulation of Read Operation (Part 2 of 6) 149
Figure 5.45 Pre-Layout Simulation of Read Operation (Part 3 of 6) 150
Figure 5.46 Pre-Layout Simulation of Read Operation (Part 4 of 6) 150
Figure 5.47 Pre-Layout Simulation of Read Operation (Part 5 of 6) 151
Figure 5.48 Pre-Layout Simulation of Read Operation (Part 6 of 6) 152
Figure 5.49 I2C Layout 159
Figure 5.50 Post- Layout Simulation for Write Operation (Part 1 of 5) 161
Figure 5.51 Post- Layout Simulation for Write Operation (Part 2 of 5) 162
Figure 5.52 Post- Layout Simulation for Write Operation (Part 3 of 5) 162

Figure 5.53 Post- Layout Simulation for Write Operation (Part 4 of 5) 163
Figure 5.54 Post- Layout Simulation for Write Operation (Part 5 of 5) 164
Figure 5.55 Post-Layout Simulation for Read Operation (Part 1 of 6)

166

Figure 5.56 Post- Layout Simulation for Read Operation (Part 2 of 6)

167

Figure 5.57 Post-Layout Simulation for Read Operation (Part 3 of 6)

167

Figure 5.58 Post-Layout Simulation for Read Operation (Part 4 of 6)

168

Figure 5.59 Post- Layout Simulation for Read Operation (Part 5 of 6)

168

Figure 5.60 Post-Layout Simulation for Read Operation (Part 6 of 6)

169

LIST OF TABLES

Table 4.1 Multiplexer inputs 73

Table 4.2 States Binary Equivalent

75

Table 4.3 Equivalent Inputs 75

Table 4.4 Truth Table ACTION_START

77

Table 4.5 Truth Table ACTION_START

77

Table 4.6 Karnaugh Map SDA ACTION_START 79

Table 4.7 Karnaugh Map SCL ACTION_START

79

Table 4.8 Karnaugh Map SCL ACTION_START

79

Table 4.9 Truth Table ACTION_WRITE

81

Table 4.10 Karnaugh Map SCL ACTION_WRITE 82

Table 4.11 Truth Table ACTION_READ

83

Table 4.12 Karnaugh Map SDA ACTION_READ

84

Table 4.13 Karnaugh Map SCL ACTION_READ

84

Table 4.14 Truth Table ACTION_IDLE

86

Table 4.15 Karnaugh Map SDA ACTION_IDLE

87

Table 4.16 Karnaugh Map SCL ACTION_IDLE

87

Table 4.17 Truth Table ACTION_NACK 88

Table 4.18 Karnaugh Map SDA ACTION_NACK

89

Table 4.19 Karnaugh Map SCL ACTION_NACK 89

Table 4.20 Truth Table ACTION_STOP

90

Table 4.21 Karnaugh Map SDA ACTION_STOP

91

Table 4.22 Karnaugh Map SCL ACTION_STOP

91

Table 4.23 Select Line Values of Bidirectional Shift Register

95

Table 5.1 Write Operation Zilog Signal Measurements 115

Table 5.2 Read Operation Zilog Signal Measurements

123

Table 5.3 Write Operation Xilinx Signal Measurements

127

Table 5.4 Write Operation Xilinx Signal Measurements

130

Table 5.5 Write Operation FPGA Signal Measurements

137

Table 5.6 Read Operation FPGA Signal Measurements

143

Table 5.7 Write Operation Pre-Layout Signal Measurements

148

Table 5.8 Read Operation Pre-Layout Signal Measurements 153

Table 5.9 Summary of Waveform Functionalities (Write Operation)

154

Table 5.10 Performance Result Summary (Write Operation) 156

Table 5.11 Summary of Waveform Functionalities (Read Operation)

157

Table 5.12 Performance Result Summary (Read Operation)

158

Table 5.13 Write Operation Post- Layout Signal Measurements

165

Table 5.14 Read Operation Post- Layout Signal Measurements

170

Table 5.15 Summary of Waveform Functionalities (Write Operation) 171

Table 5.16 Performance Result Summary (Write Operation) 173
Table 5.17 Summary of Waveform Functionalities (Read Operation)

174

Table 5.18 Performance Result Summary (Read Operation)

175

ACKNOWLEDGEMENT

Our thesis has been a wonderful journey to us. We were able to face challenges
and conquer obstacles on our way to reach on our destination. And we wouldnt be
able to reach our goal if it werent for those who encouraged us and helped us along
the way.
We want to first thank the Lord, for the wisdom, knowledge and strength that
he has given us. To Him be all the glory and honor. We also want to thank our parents
for their support and for providing our monetary needs to be able to supplement our
bodies with delicious nourishment every day we made our thesis. Furthermore, we
want to thank Sir Yap, our adviser, for his patience with us and for guiding us until we
were able to see our thesis as a success. We thank our friends as well for alleviating
our stress by instilling humor in our sometimes tense and anxious life. Lastly, we want
to thank Zilog, Inc. that despite our careless mistake of asking for the wrong product
still gave us the free development kit that we ask of them.

ABSTRACT
This paper reviews the theoretical operation and describes the design of a
Inter-Integrated Circuit (I2C) using 0.25m CMOS technology. I2C is a
communication tool used to communicate between peripheral devices. It is composed
of 2 bidirectional buses/lines namely the SCL and SDA lines. The different control
signals passes through these lines to establish an operation between the master and the
slave. The I2C configuration could be a MASTER-SLAVE mode, MASTER mode or
SLAVE mode.
The I2C module design aims to mimic the behavior of I2C module of Zilogs
Z8 Encore! XP F64XX Series Development Kit. This design is limited only to 8-bit
data transfer application and tested only using a 4k EEPROM (AT24C04) as a slave.
This design only dealt with the MASTER mode configuration of the I2C.