Embedded System Design

By Dr K A Radhakrishna Rao Prof in E & C Engg

Typical Embedded System

Memory (Embedded
Firmware)

Communication Interface (USB,RS232) I/P Ports (sensors) System Core (MP,MC,DSP,ASIC,PLD, COTS)

O/P Ports(Actuators)

Other supporting Ics, Subsystems

 System core
Microprocessor (Intel 8085) Microcontroller(AT89C51) Field Programmable Gate Array(FPGA) (xilinx Spartan) Digital Signal Processor (DSP) (Blackfin processors) Application Specific Integrated Circuit (ASIC)/ Application Specific Standard Product (ASSP) (ADE7760 Single phase Energy Metering IC)

 Embedded system viewed as REACTIVE system

REACTIVE system is one which responds to an input. Embedded systems are basically designed to regulate a physical variable or to manipulate the state of some devices by sending some control signals to the Actuators or devices connected to the O/p ports of the system, in response to the input signals provided by the end users or the sensors which are connected to the I/p port.

 Common User Interface (I/O ports):

Input devices Key boards, push-button switches Output devices Buzzers, LED, LCD Not all i/p and o/p devices are used with any embedded system, it is only application dependent. eg. eg. Mobile applications requires keyboard & screen Embedded systems could be automatic i.e whole process of control and monitoring could be automated.

 Communication Interface:
Serial and parallel devices such as USB, DB9, parallel port and RS 232.

Communication interface devices provides connectivity with other devices or systems. Memory:
Responsible for holding control algorithm and other configuration details Typical memory types are OTP, PROM, UVPROM, EEPROM and FLASH

Core of the Embedded System

1. General purpose and Domain Specific Processors
Microprocessors Microcontrollers Digital Signal Processors

2. Application Specific Integrated Circuits (ASIC) 3. Programmable Logic Devices (PLDs) 4. Commercial off-the- shelf Components(COTS)

 General purpose and Domain Specific Processors

Microprocessors typically consists of CPU which internally contains ALU, control unit and working registers. It requires supporting chips to be fully functional Intel 4004 (4-bit processor) , Intel 4040 (advanced features in comparison to 4004),Intel 8008(similar to 4040 but with 14 bit PC), Intel 8080, motorola 6800(8-bit processor), Intel 8085(upgraded version additional instructions, interrupts, power supply of +5V) ,Z80 (concept of register banking by doubling register set) 16, 32 and 64 bit processors, clock speed drastically raised, more competitors in the market, low cost and low power issues addressed) Intel, AMD, Freescale, IBM, TI, Cyrix, Hitachi, NEC, LSI logic are key players Harvard and Von-Neumann are the two common architectures for processor design

 General Purpose Processor (GPP) vs Application Specific Instruction Set Processor (ASIP)
GPP meant for general computational tasks (Pentium 4/AMD Athlon, etc) Produced in large quantity ASIP are processors with architecture and instruction set optimized to specific-domain/application requirements like network processing, automotive, telecom, media applications, DSP, control applications ASIP fill the architectural spectrum between general purpose processors and ASICs. Most of the Embedded systems are built around ASIPs

 Microcontrollers:
Highly integrated containing CPU, scratch pad RAM, special and general purpose register arrays,on chip ROM/FLASH memory for program storage, timer and interrupt control units and dedicated I/O ports. Super set of microprocessors More suitable for Embedded systems Cheap, cost effective and readily available TI 1000 (first microcontroller), Intel MCS-48 family (8038HL,8039HL,8040HL,8048HL,8049AH) 8051 most popular MC. PIC form Microchip Technologies is equally popular. It is a high performance RISC microcontroller complementing CISC features of 8051. ARM 11 series provides solution to applications requiring hardware acceleration and high processing capability. Freescale, NEC, Zilog, Hitachi, Mitsubishi, Infineon, ST Electronics, National, TI, Toshibha, Philips, Microchip. Analog Devices, Daewoo, Intel, Maxim, Sharp, Silicon Laboratories, TDK, Triscend, Winbond, Atmel are the key players in Microcontroller market.

 Digital Signal Processors:

Dedicated hardware to address signal processing tasks Speed not just dependent on clock used but on the specific hardware Multiply Accumulation in one clock cycle Harvard architecture (separate Data and Program memory) Audio video signal processing, telecommunication and multimedia applications are typical examples where DP is involved. Blackfin from Analog Devices and TMS series from TI are typical DSPs.

RISC or CISC
RISC (Reduced Instruction Set Computer) CISC (Complex Instruction Set Computer) Example of RISC: Atmel AVR microcontroller having only 32 instructions Example of CISC: AT89C51 having 255 instuctions Note: It is not just number of instructions which determine the processor to be RISC or CISC, there are many other criteria.

RISC Lesser no. of instructions Instruction pipelining and execution speed Orthogonal instruction set Operations are performed on registers only, memory operations restricted to load and store A large number of registers are available Longer code length to execute a task Single, fixed length instructions Less silicon usage and pin count Harvard architecture

CISC Greater no. of instructions Generally no instruction pipelining feature Non-orthogonal instruction set Operations are performed on registers and memory depending on instruction Limited no. of general purpose registers Shorter code length to execute a task Variable length instructions More silicon usage Can be Harvard or Von-Neumann

Harvard vs Von-Neumann
I/O CPU Memory

Single shared bus

Program Memory

CPU

Data Memory

Harvard Architecture Separate buses for instructions and data fetching Easier to pipeline thus high performance Comparatively high cost No memory alignment problems No chances for accidental corruption of PM as it is separate from DM

Von-Neumann Architecture Single shared bus for instructions and data fetching Low performance Cheaper Allows self modifying codes
Self-modifying code is a code/instruction which modifies itself while execution

Chances of corruption of PM

 Big Endian vs Little-Endian Processors/Controllers Endianness specifies the order in which the data is stored in the memory by processor operations in a multi byte system, Two ways of doing this are
Little Endian: Lower-order byte of the data is stored in memory at the lowest address, and the higher order byte at the highest address (The little end comes first)
Base Address +0 Base Address +1 Base Address + 2 Base Address +3 Byte 0 Byte 1 Byte 2 Byte 3 Byte 0 Byte 1 Byte 2 Byte 3 0x20000(Base Addr) 0x20001(Base Addr+1) 0x20002(Base Addr + 2) 0x20003(Base Addr + 3)

 Big Endian: Higher order byte of the data is stored in memory at the lowest address, and the lowerorder byte at the highest address (The big end comes first)

Base Address +0 Base Address +1 Base Address + 2 Base Address +3

Byte 3 Byte 2 Byte 1 Byte 0

Byte 3 Byte 2 Byte 1 Byte 0

0x20000(Base Addr) 0x20001(Base Addr+1) 0x20002(Base Addr + 2) 0x20003(Base Addr + 3)

 Load Store Operation and Instruction Pipelining Load Store Architecture

R1 R2 R3

x y z

ALU

 Load R1, x Load R2,y Load R3, R1, R2 Store R3, z Conventional Instruction Execution by Processor is fetch-decode-execute While decode-execute stage, next fetch can be overlapped as memory address bus is free. Fetch will go waste in case of present execute instruction is branch or jump Multiple levels of pipelining is possible.

 Application-Specific Integrated Circuits (ASICs)

A microchip designed to perform a specific or unique application Integrates several functions into a single chip and there bt=y reduces the system development cost Most of them are Proprietary products As a single chip, ASIC consumes a very small area in the total system and therby helps design of smaller systems with high capabilities/functionalities Pre-fabricated or custom fabricated using re-usable building block library of components for a particular customer application. Profitable only in case of large volume commercial productions. Non-refundable initial investment required Non Recurring Engineering Charge (NRE) If NRE is borne by third party then ASIC is made openly available in the market, the ASIC is then referred to as Application Specific Standard Product (ASSP). The ADE 7760 Energy meter is one example. Generally internal details of the chip are not revealed.

Programmable Logic Devices Logic devices performs specific logical functions Logic devices are broadly classified as fixed and Programmble PLDs offer customers a wide range of logic capacity, features, speed and volatage-characteristics These devices can be re-configured to perform any number of functions at any time. PLD designers make use of inexpensive software tools to quickly develop, simulate, and test their designs. (eg., network router, a DSL modem, a DVD player, or an automotive navigation system) There is no NRE costs and the final design is completed much faster than that of a custom, fixed logic device Customers can change the circuitry as often during the design phase until it operates to their satisfaction. This mainly due to its programmable nature on re-writable memory.

 Twp major types of PLDs are CPLDs and FPGAs. FPGAs offers highest amount of logic density, the most features and the highest performance. (ex. Xilinx Virtex line of devices, provides eight million system gates) These devices also offers features such as built-in hardwired processors, substantial amounts of memory, clock management systems and suport for many latest, very fast device-to-device signaling technologies. FPGA are used in data processing and storage, instrumentation, telecommunication and signal processing applications.

 CPLDs offer much smaller amounts of logic-up about 10,000 gates. They offer very predictable timing characteristics and are therefore ideal for critical control applications. Ex., Xilinx CoolRunner series Low amounts of power, inexpensive.

 Advantages of PLD
More flexibility during design cycle Do not require long-lead times for prototypes or production parts No large NRE charges on customers Customer can order just the number of parts they need, when they need them, allowing them to control inventory PLDs can be reprogrammed even after a piece of equipment is shipped to a customer.

 Commercial Off-the-Shelf Components(COTS) COTS product is one which is used as-is These are designed in a such a way to provide easy integration and interoperability with existing system components. COTS component itself can be developed around a general purpose or domain specific processor or an ASIC or a PLD. Ex. Remote controlled toy car control units, high bandwidth ADCs, TCp/IP plug-in module (WIZnet, Freescale, Dynolog) Major advantage is that they are available in the market, cheap and developer can cut his cost Identifying proper COTS is the task and provide the plug-in option on the board. There is no operational and manufacturing standards among the vendors Major disadvantage is that manufacturer withdraws the COTS component any time.

 MEMORY On-Chip , Off-chip and working Memory Program Storage memory (ROM)
Different types of ROM used in storing program codes are Flash, NVRAM,PROM(OTP), Masked ROM (MROM), EPROM, EEROM Program storage memory is non-volatile

 Masked ROM (MROM):

It is a one-time programmable device Makes use of hardwired technology for storing the data. Device is factory programmed by masking and metallisation process at the time of production itself. It is low cost for high volume production Mechanisms used with masking process
Creation of an enhancement or depletion mode transistor through channel implant By creating the memory cell either using a standard transistor or a high threshold transistor. In the high threshold mode, the supply voltage required to turn ON the transistor is above the normal ROM IC operating voltage. This ensures that the transistor is always off and the memory cell stores always logic 0.

Major disadvantage is that there is no flexibility in modifying the firmware once programmed.

 PROM:
Can be programmed by end user. This memory has nichrome or polysilicon wirees arranged in a matrix. These wires act as fuse. Programming the PROM is by selective burning/blowing the fuses Fuse not blown/burnt represent logic 1.Default logic is 1 OTP can be programmed only once.

 EPROM:
Flexible as it can be erased and reprogrammed EPROM stores the bit information by charging the floating gate of an FET. EPROM programmer are used to store bit-information High voltage is used to charge the floating gate. Erasing is done by exposing quartz crystal window to UV rays. Entire memory is erased when exposed to UV rays for fixed duration Erasing is a tedious and time-consuming process as it requires chip to be taken out and exposed to UV rays for 20-30 mins. EEPROM uses electrical signals at the register/Byte level to alter They can be erased and reprogrammed in-circuit Very flexible in terms of erasing and reprogramming Disadvantage is that it has limited capacity compared to standard ROM

 FLASH
Latest and most popular ROM technology Variation of EEPROM technology It combines the re-programmability of EEPROM and the high capacity of standard ROMs FLASH memory is organised as sectors (blocks) or pages and stores information in an array of floating gate MOSFET transistors. Erasing of memory can be done at sector or page level and should be done before re-programming The typical erasable capacity of FLASH is 1000 cycles W27C512 from WINBOND is an example of 64KB FLASH memory

NVRAM
Non Volatile RAM is random access memory with battery back-up. Contains static RAM and a minute battery for providing supply to the memory in the absence of external power supply. Both are packed together in a single package. Life span is typically 10years.DS1644 from Maxim/Dallas is 32KB NVRAM

 Read-Write Memory/Random Access Memory(RAM)

RAM is used as data or working memory. Both read and write are possible. Volatile in nature and accessing is random. Static RAM (SRAM), Dynamic RAM (DRAM) and Non-Volatile RAM (NVRAM) are major types.

 SRAM
This stores data in the form of voltage and they are made up of flip-flops. This is fastest among the types of RAM. In a typical implementation, a SRAM cell (storing one bit information) is realised using six transistors (or 6 MOSFETs). Four of the transistors are used for building the latch part of the memory and two for controlling the access. SRAM is fast in operation due to its resistive networking and switching capabilities. Major disadvantage of SRAM are low-capacity and high cost.

 DRAM
Stores data in the form of charge. It is made up of MOS transistor gates. Low cost and high density are the advantages Since it is stored in the form of charge, it faces leakage problem and calls for periodic refreshing. Special DRAM controllers are used for periodic refreshing (in milliseconds interval).

 Memory according to the Type of Interface

Parallel Interface(parallel data lines of processor connected to data lines of memory) Serial interface like I2C which is 2-line interface Serial peripheral interface(SPI) [ 2+n line interface where n stands for the total number of SPI bus devices in the system] Single wire interconnection(ex Dallas 1-Wire interface)

 Memory Shadowing
Execution of program or configuration reading from ROM is generally slower compared with that of RAM due to difference in memory accessing timings. Memory shadowing is used to enhance program executing or configuration setting. Basic Input Output configuration ROM or simply BIOS is used to hold important hardware configuration setting of a system. Data in the BIOS is usually read in the beginning and system is configured accordingly, it is time consuming process. RAM is included behind the logical layer of BIOS at its same address as a shadow to the BIOS. First step that happens during the boot up is copying the BIOS to the shadowed RAM and write protecting the RAM then disabling BIOS reading. Non-volatile nature of RAM requires data to be in ROM and high accessing speed of RAM helps one to speed up the process.

 Memory Selection for Embedded Systems

No general rule Application and situation dependent Many factors influence while deciding on size and type of memory (Cost, mobility, power conservation) Real time applications need separate consideration (RTOS selection, RAM and ROM share, keeping image of Program in ROM while running the codes from RAM) Normally the binary code for RTOS kernel containing all the services is stored in a non-volatile memory (like FLASH) as either compressed or noncompressed data. During boot- up of the device the RTOS files are copied from the program storage memory and then loaded to the RAM for execution. Always have buffer (extra) memory Memory comes in definite sizes and near closest on higher end is chosen. Choose total amount of memory based on address bus size. NAND and NOR flash

 Sensors and Actuators

Sensors are means of collecting physical status of the system and they are the input to Embedded system Actuators are the means of driving the control mechanism which itself is controlled by output of the embedded system . Sensors and Actuators are not mandatory, it depends on the application If the system is only designed for monitoring then there is no necessity of actuators. Sensor is a transducer that converts energy from one form to another for any measurement or control purpose. Actuator is a form of transducer (mechanical or electrical) which converts signals to corresponding physical action (motion). Both sensors and actuators constitute part of I/O subsytem. Both sensors and actuators are not directly connected to embedded system , it is generally done through I/O interface which takes care of signal matching etc..

 Light Emitting Diode(LED)

It is a p-n junction diode LED can be driven by Logic 0 or 1 level of the processor (source /sink option)

7-segment LED Display

Contains 8 light emitting diode arranged in a special form 7 LEDs are used for displaying alpha numeric characters and 1 used for decimal point display. Common anode and common cathode LED display

 Optocoupler
It is a solid state device to isolate two parts of a circuit. It combines LED and photo-transistor in a single housing. It is used in electronic circuits for suppressing interference in data communication, circuit isolation, high voltage separation, simulataneous separation and signal intensification An example for a optocoupler is MCT2M from Fairchild semiconductors.

 Stepper Motor
It is an Electro-mechanical device which generates discrete displacement (motion) in response to dc electrical signals. Different in operation in comparison to normal dc motor It is continuous rotation in case of normal dc motor where as it discrete rotation for the applied dc input in case of stepper motor. Widely used in industrial embedded applications, robotics control systems, consumer electronic products.

 Based on the coil winding arrangements , a two-phase stepper motor is classified into:
Unipolar Bipolar

Unipolar
has two windings per phase The direction of rotation (clockwise or anticlockwise) is controlled by changing the direction of current flow Current in one direction flows through one coil and opposite in other coil Direction is changed by switching the terminals to which the coils are connected

 A,B,C and D represent coils Coils A and C carry current in opposite directions for phase 1 (only one of them will be carrying current at a time), similarly, B and D carry current in opposite directions for phase 2.

 Bipolar
It has single winding per pahse For reversing the motor rotation the current flow through the windings is reversed dynamically Complex circuitry is required for current flow reversal.

 The stepping of stepper motor can be implemented in different ways by changing the sequence of activation of the stator windings. Full step: Out of the two windings, only one winding of a phase in energised at a time
Step 1 2 3 4 Coil A H L L H Coil B H H L L Coil C L H H L Coil D L L H H

 Wave Step: Only one phase is energised at a time and each coils of the phase is energised alternatively
Step 1 2 3 4 Coil A H L L L Coil B L H L L Coil C L L H L Coil D L L L H

 Half Step: It sues combination of wave and full step. It has the highest torque and stability.
Step 1 2 3 4 5 6 7 8 Coil A H H L L L L L H Coil B L H H H L L L L Coil C L L L H H H L L Coil D L L L L L H H H

 Two-phase unipolar stepper motors are popular choise Port pins of Microprocessor/microcontroller may not be able to drive the motors Voltage requirement is in the range of 5 to 24 volts Drivers are needed, ULN2803 is a octal peripheral driver array available from ON semiconductors and ST microelectronics

 Relays:
It is a Electro-mechanical device Dynamic path selector for signals and power Magnetic field generated due to current flow attracts armature core and moves the contact point Most of the industrial relays are bulky and requires high voltage to operate. Reed relays use low voltage DC which is used with ES

 A free-wheeling diode is used for free-wheeling the voltage produced in the opposite direction when the relay coil is deenergised. The free wheeling diode is essential for protecting the relay and the transistor .

 Piezo Buffer
It is a piezoelectric device for generating audio indications in embedded application. It contains piezoelectric diaphragm which produces audible sound in response to the voltage applied to it. Self driving and External driving are the two types. Self driving has all the necessary components to generate predefined tone External driving supports generation of different tones. Tone can be varied by applying a variable pulse train to the piezoelectric buffer. This can be directly interfaced to the port pin o fthe processor Transistor drive circuit can be used in case of higher drive requirement.

 Push Button Switch

Input device, Push to Make and Push to break are two types Configured to used with LOW or HIGH

Key Board
Array of keys arranged in matrix form Greatly reduces number of interface connections (ex to connect 16 keys, we need 16 port pins where as if it is arranged as 4x4 then only 8 pins are needed) Scanning technique is used to identify key pressing. Rows are o/p ports and columns are i/p port. Sequentially each row is pulled down and columns are scanned. De-bouncing is a standard problem. Hardware and Software solutions are possible.

 Programmable Peripheral Interface (PPI)

Supports 24 I/O pins (I/O, Handshake, BSR modes) Either used as three 8-bit I/O ports or two 8 bit parallel ports (A & B) with port C in
8 individual I/O pins Two 4-bit ports

Control word defines roles of ports/pins

 Communication Interface
Communication interface is essential for communicating with various subsystems of the embedded system and with the external world Two perspectives of communication interface with embedded systems
Onboard communication interface (connecting onboard components) External communication interface(connecting outside embedded system)

 Examples of Onboard communication interface are I2C, SPI, UART 1Wire External communication interface is responsible for data transfer between the embedded system and other devices or modules. This can be either wired or wireless media and it can be serial or parallel. (ex Mobile communication equipment) Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi), Radio Frequency waves (RF), GPRS are exaples of wireless communication interface. RS-232C/RS-422/RS-485, USB, Ethernet IEEE 1394 port, Parallel port, CF-II interface, SDIO, PCMCIA are examples for wired interfaces. It is not mandatory that embedded system should contain an external communication initerface.

 Onboard Communication Interfaces

Inter Integrated Circuit (I2C) Bus: Synchronous bi directional half duplex two wire serial interface bus. Developed by Philips Semiconductors in the early 1980s to be used with connecting Microprocessor and peripheral chips in television sets Has two bus lines; Serial Clock-SCL and Serial Data SDA. SCL line is responsible for generating synchronisation clock pulses and SDA is responsible to carry serial data. I2C is a shared bus to which many devices can be connected. Devices can be Master or Slave. Master take responsibility of sending synchronizing clocks and serial data. Master and Slave devices can act as either transmitter or receiver. Master either as transmitter or receiver is responsible for sending synchronizing clock pulses. I2C supports multi masters on the same bus.

 I2C bus interface is built around an input buffer and an open drain/collector transistor. When the bus is in the idle state, the open drain /collector transistor will be in the floating state and the output lines (SDA and SCL) switch to the High Impedance state. For proper operation of the bus, both the bus lines should be pulled to the voltage using pull-up resistors. With pull-up resistors, the output lines of the bus in the idle state will be HIGH

Sequence of operations for communicating with an I2Cslave device:

1. 2. 3. The master device pulls the clock line (SCL) of the bus to HIGH The master device pulls the data line (SDA) LOW when the SCL line is at logic HIGH (this is the start condition for data transfer) The master device sends the address of the slave device over the SDA line. Clock pulses are generated at the SCL line for synchronizing the bit reception by the slave device. The MSB of the data is always transmitted first. The data in the bus is valid during the HIGH period of the clock signal. The master device sends the Read or Write bit according to the requirement (1 Read, 0 write) Master waits for the acknowledgement from slave while slave dcode the address sent on the SDA line Slave device sends an acknowledgement over SDA line Master transmits 8-bit data over SDA line if it is write operation or slave sends the data if it is Read operation Acknowledgement for data transfer is done (either master or slave will send depending on read or write operation) The master device terminates the transfer by pulling the SDA line HIGH when the clock line SCL is at logic HIGH (indicating the STOP condition)

4. 5. 6. 7. 8. 9.

 Three different rates supported by I2C are;

Standard mode (100kbps) Fast mode (400kbps) High speed mode(3.4mbps)

Serial Peripheral Interface (SPI) Bus

It is synchronous, bi-directional full-duplex four wire serial interface bus Introduced by Motorola It is a single master multi-slave system More than one master is allowed but only one will be active at a time. Signals used with SPI are:
Master Out Slave In (MOSI): Signal carrying data from master to slave device. It is also known as Slave Input/Slave Data In (SI/SDI) Master In Slave Out (MISO): Signal line carrying data from slave to master device. It is also known as Slave Output (SO/SDO) Serial Clock (SCLK): Signal line carrying clock signals Slave Select (SS): Signal line for slave device select. It is active low signal.

Master is responsible for generating clock signal. It selects the required slave device. The data outline (MISO) of all the slave devices when not selected floats at high impedance state. Serial data transmission through SPI bus is fully configurable. Certain set of registers are used for this. The serial peripheral control register holds the configuration parameters such as slave select address, baud rate, clock signal control etc. The status register holds the status of various conditions for TX and RX. Shift register principle is used with data communication. Both master and slave device have special shift registers. Size of the shift register is normally device dependent and it is generally multiple of 8. Shift registers of master and slave forms a circular buffer. Data transfer happens from master shift register to slave shift register through MOSI pin. Whereas otherwise communication is through MISO pin. Comparison to I2C bus, SPI bus is most suitable for applications requiring transfer data in Streams. Limitation is that it does not support acknowledgement mechanism.

 Universal Asynchronous Receiver Transmitter (UART)

Asynchronous serial data transmission, no clock signal required. Pre defined rules and agreements control the data transfer. The serial communication settings (baud rate, number of bits per byte, parity, number of start and stop bits and flow control ) for both Tx and Rx should be set as identical. Polling of data at Rx is done at the rate 1/x seconds where x is the baud rate. The receiver unit polls the receiver line exactly half of the time slot available for the bit. Parity adding and checking is done at Tx and Rx respectively. In addition to the serial data transmission function, UART provides hardware handshaking signal support for controlling the serial data flow. National semiconductors 8250 is an example for UART chip. Present day processors/controllers comes with integrated UART functionality.

 1-Wire Interface
It is an asynchronous half-duplex communication protocol developed by Maxim Dallas. It is also referred to as Dallas 1-wire protocol. Single line called DQ is used for communication. MasterSlave communication model is followed. Power can be sent along the signal-wire Supports single master and one or more slave devices. Every 1-wire device contains a globally unique 64 bit identification number stored within it. The identifier as three parts: an 8-bit family code, a 48-bit serial number and an 8-bit CRC computed from the first 56 bits.

 The communication protocol is:

1. 2. 3. 4. 5. The master device sends a Reset pulse on the 1-wire bus The slave device present on the bus respond with a Presence pulse The master device sends a ROM command (Net address command follwoed by the 64 bit address of the device). This addresses the slave devices to which it wants to initiate a communcation. The master device sends a read/write function command to read /write the internal memory or register of the slave device. The master initiates a Read data/Write data from the device or to the device.

All communication over 1-wire bus is mater initiated. Communication is divided into timeslots of 60 microseconds. Each operation of data communication is expressed interms of above time slots. Ex In the step -1 Reset pulse occupies 8 time slots.

 Parallel Interface
Generally used with memory mapped devices onboard The host processor/controller of the embedded system contains a parallel bus and the device which supports parallel bus can directly connect to this bus system Communication on this bus is controlled through control signal interface. Control signal includes Read and write and device select. Direction of data transfer is controlled by Read and Write signal. Strict timing characteristics are followed for parallel comunication. Parallel communication is always host initiated If the device wants initiate a data transfer then interrupt mechanism is used.

 External Communication Interfaces

RS-232 C & RS-485
RS-232 C (Recommended Standard number 232,revision C from the Electron Industry Association(EIA)) is a legacy, full duplex, weird, asynchronous serial communication interface Developed in 1960s. RS-232 extends the UART communication signals for external data communication RS-232 follows EIA standard for bit transmission (logic 0 is represented by voltage +3 to +25 V and logic 1 is represented with voltage between -3 to -25 V. Logic 0 referred to as Space and logic 1 known as Mark RS-232 has various handshaking signals for data communication apart from standard transmit and receive Two connectors are supported DB-9 and DB-25

1 4 9

1 1 4 2 5

1 3

Pin name TXD RXD RTS CTS DSR GND DCD DTR RI FG SDCD SCTS STXD

DB-9 3 2 7 8 6 5 1 4 9

DB-25 2 3 4 5 6 7 8 20 22 1 12 14 15

Description Transmit pins for transmitting serial data Receive pin for Receiving serial data Request to send Clear to send Data set ready Signal Ground Data Carrier detect Data terminal Ready Ring Indicator Frame Ground Secondary DCD Secondary CTS Secondary TXD

Pin name TC SRXD RC SRTS SQ NC NC NC NC NC NC NC

DB-9

DB-25 15 16 17 19 21 9 10 11 18 23 24 25

Description Transmission Signal Element Timing Secondary RXD Receiver Signal Element Timing Secondary RTS Signal Quality detector No connection No connection No connection No connection No connection No connection No connection

Data Terminal Equipment (DTE) and Data Communication Equipment (DCE) are involved in

point-to-point communication using

RS-232 If no data flow control is required then it is only TXD and RXD are required in cross connection mode. Control signals are used for modem communication . RTS and CTS signals coordinate the communication between DTE and DCE. DTR and DSR are acknowledgement kind of signals from DTE and DCE respectively. DCD is used by the DCE to indicate the DTE that a god signal is being received. RI is a modem specific signal line for indicating an incoming call on the telephone line. The 25 pin DB connector contains two sets of signal lines for transmit, receive and control lines. Now a days DB-25 connector is obsolete. Baud rate supported are 300bps,1200bps,9600bps,11.52kbps and 19.2kbps. 9600 bps is the most widely used one. Maximum operating distance of RS-232 is 50 feet UART is used as onboard communication interface in most of the embedded systems conversion from onboard to RS-232 is done through converters both at TX and RX. (eg MAX 232)

 Disadvantages of RS-232
Bluetooth, USB, Firewire technologies have pushed RS-232 technology. RS-232 supports only point-to-point communication not suited for multi-drop communication Since it uses single ended data transfer technique for signal transmission and threby more susceptible to noise and this greatly reduces the operating distance.

RS-422 is another standard from EIA supporting 100kbps baud rate over 400 feet. It is compatible with RS-232, converters are needed. Multi-drop communication with one TX device and Rx devices upto 10. RS-485 is the enhanced version of RS-422. It can go up to 32 receivers. The communication between devices in the bus uses the addressing mechanism to identify slave sections.

 Universal Serial Bus (USB)

Wired high speed bus Intel, Microsoft, IBM, Compaq, Digital and Northern Telecom together proposed this standard. USB communication system follows a star topology with a USB host at the centre and one or more USB peripheral devices connected to it. A USB host can support connection upto 127 inclusive of slave and other USB hosts. USB transmits data in packet format. Comunnication is host initiated one. USB host contains a host controller which is responsible for controlling the data communication, including establishing connectivity with USB slave devices, packetizing and formatting the data. Two important standards Open Host Control Interface (OHCI) and Universal Host Control Interface (UHCI)

 USB cable is used to establish physical connection between host and other devices. USB cable supports communication upto 5 meters. USB standard uses two different types of connector at the ends of the USB cable for connections. Type A connector is used for upstream connection (connection with host) and Type B is used for downstream connection (connection with slave) Type A connector is used with PCs and Laptops. Both Type A and Type B contain 4-pins for communication.

Pin no 1 2 3 4

Pin Name V Bus DD+ GND

Description Carries power (5V) Differential data carrier line Differential data carrier line Ground signal line

USB uses differential signals for data transmission. It improves the noise immunity. USB interface has the ability to supply power to the connecting devices. It can supply power upto 500mA at 5 V. Mini and Micro USB connectors are available for small form factor devices like portable media players. Each USB device contains a product ID (PID) and Vendor ID (VID) which embedded into the USB chip by the USB device manufacturer. VID is supplied by the USB standards forum. PID and VID are essential for loading the drivers corresponding to a USB device for communication. USB supports four modes of data transfer:

Control: Used by USB system software to query, configure and issue commands to the USB device Bulk: Is used for sending block of data to a device. This supports error checking and correction. Transferring data to a printer. Isochronous mode: Used for real data communication. Data transmitted as stream in realtime. No error-checking allowed. Audio devices and medical equipments use this. Interrupt transfer: Used for small amount of data transfer . Uses polling technique to see whether the USB device has any data to send. Mouse and keypad uses this technique .

Four different data rates : Low speed (1.5 Mbps), Full speed (12 Mbps), High speed (480Mbps) and super speed (4.8 Gps) USB1.0 defines Low and Full speed USB 2.0 and above defines high and super speed.

 IEEE 1394 (Firewire)

Wired, isochronous high speed serial communication bus, also known as High Performance Serial Bus (HPSB) Apple carried out this research and standard proposed by IEEE. Available from various vendors (Firewire from Apple, i.Link from Sony, Lynx from TI) Supports peer-to-peer connection and point-to-multipoint communication allowing 63 devices to be connected on the bus in a tree topology. Can support cable length of 15 feet. Evolution from initial version (1394-1995) to recent version (1394-2008) Supports data rate from 400 to 3200 Mbits/sec Uses differential data transfer Interface cable supports 3 types of connectors, namely; 4-pin connector, 6-pin connector(alpha connector) and 9 pin connector (beta connector) 6 & 9 pin connectors carry power also to power peripheral devices. It can supply unregulated power in the range of 24 to 30 V.

Pin Name Power Signal Ground TPBTPB+ TPATPA+ TPA (S) TPB(S) NC

4pin

6pin 1 2

9pin 8 6 1 2 3 4 5 9 7

Description Unregualted DC supply, 24 30V Ground connection Diff signal line for signal line B Diff signal line for signal line B Diff signal line for signal line A Diff signal line for signal line A Shield for Diff signal line A. Normally Gnded Shield for Diff signal line B. Normally Gnded No connection

1 2 3 4

3 4 5 6

 There are two differential data transfer lines A & B per connector. In a 1394 cable, normally the differential lines of A are connected to B 1394 is a popular communication interface for connecting embedded devices like Digital camera, Camcorder, Scanners to desktop computers for data transfer and storage. Unlike USB interface ,IEEE 1394 does not require a host for communicating between devices. Eg., scanner can be connected to printer directly. Data rate supported by 1394 is far higher than the one supported by USB 2.0 interface.

 Infrared (IrDA)
Serial, half duplex, line of sight based wireless technology (used with TV, VCD etc) Uses infrared waves of electromagnetic spectrum for transmitting the data. Supports point-to-point and point-to-multipoint communication provided all devices connected are within line of sight. Typical range 10 cm to I mt. Range can be increased further by increasing TX power. Speed of transmission is from 9600 bps to 16 Mbps Based on speed five classifications.
Serial IR (SIR) 9600bps to 115.2 kbps Medium IR (MIR)-0.576 Mbps to 1.152 Mbps Fast IR (FIR)- 4Mbps very fast IR (VFIR) -16Mbps Ultra Fast IR (UFIR)-targeted for 100Mbps

 Tx and Rx are involved in Ir DA communication. LED is the IR source for transmission and photodiode at RX used for reception. Both Tx and Rx will be present in the device known as Transceiver to have two-way communication. Infra-red Data Assocaition is the regulatory body. IrDA communication has two essential parts; a physical link part and protocol past. Physical link is responsible for the physical transmission of data between devices and protocol part is responsible for defining the rules of communication. IrDA specification include the standard for both physical link and protocol layer. The IrDA control protocol contains implementations for physical layer (PHY), Media Access Control (MAC) and Logical Link Control (LLC) IrDA is a popular interface for file exchange and data transfer in low cost devices.

Bluetooth (BT)

Low cost, low power, short range wireless technology for data and voice data communication. Proposed first by Ericsson in 1994 Operates at 2.4 GHz of the Radio Freq spectrum and uses Frequency Hopping Spread Spectrum (FHSS) technique Supports data rate of 1 Mbps and 30 feet Has physical link part and protocol part. Bluetooth enabled devices essentially contain a Bluetooth wireless radio for the transmission and reception of data. Rules governing the Bluetooth communication is implemented in the Bluetooth protocol stack. Bluetooth communication IC holds the stack. Each Blue tooth device has a 48 bit ID number. Communication follows packet based transfer. Supports point-to-point and point-to-multipoint communication. Master slave communication model is followed. When network is formed with one bluetooth device as master and more than one device as slaves, it is called Piconet. Piconet supports max of seven slave devices. Most widely used with Mobile devices The Generic Access Profile (GAP) defines the requirements for detecting a Bluetooth device and establishing a connection with it. All other specific usage profiels are based on GAP. Serial Port Profile (SPP) for serial communication, File transfer Profile (FTP ) for file transfer between devices, Human Interface Device (HID) for supporting human interface devices like keyboard and mouse. Blue tooth Special interest group (SIG) defines the standards.

Wi-Fi or Wireless Fidelity

Popular communication technique for networked communication of devices and it supports Internet Protocol(IP) It follows IEEE 802.11 standard As it is requirement of networking devices to have identification, in wi-fi it is done through IP address. In Wi-Fi routers/access points to manage communication are needed. Routers/access points are responsible for restricting the access to a network, assigning IP address to devices in the network, routing data packets to the intended devices on the network Wi-Fi enables devices contain a wireless adaptor for transmitting and receiving data in the form of Radio signals through an antenna. Wi-Fi operates at 2.4 GHz or 5GHz of radio spectrum Service Set Identifier (SSID) are used in identifying available networks. In case of secured networks password is needed. Wi-Fi employs different security mechanisms like Wired Equivalency Privacy (WEP), Wireless Protected Access (WPA) etc.. for securing the data communication Supports data rates from 1 Mbps to 150 Mbps depending on the standards and access/modulation method. Depending on the type of antenna and usage location , Wi-Fi offers a range of 100-300 feet.

ZigBee
Low power, low cost, woreless network communication protocol based on the IEEE 802.15.4.2006 standard Targeted for Wireless Personal Area Networking (WPAN). ZigBee specifications support a robust mesh network containing multiple nodes. This networking strategy makes the network reliable by permitting messages to travel through a number of different paths to get from one node to another. Operates worldwide at the unlicenced badns of Radio spectrum. Supports operating distance up to 100 mts and a data rate of 20 to 250kbps. ZigBee Coordinator(ZC)/Network Coordinator: This acts as root of the ZigBee network. It is responsible for initiating the network and it has the capability to store information about the network. ZigBee Router(ZR)/Full function Device (FFD): Responsible forpassing information fromm device to another device or ZR ZigBee End Device (ZED)/Reduced Function Device (RFD): End device containing ZigBee functionality for data communication . It can talk with a ZR or ZC and doesnt have the capability to act a mediator for transferring data from one device to another.

 ZigBee has wide application areas such as Home & Industrial automation, energy management, home control/security, medical/patient tracking, logistics & asset tracking and sensor networks & active RFID ZigBee alliance manages defining standards

 General Packet Radio Service (GPRS)

GPRS is a communication technique for transferring data over a mobile communication network like GSM. Packet communication is used GPRS supports a theoretical maximum transfer rate of 171.2 Kbps. Shared communication is used, i.e., instead of radio channel is dedicated to single cell user it shared among many users. Time division multiplexing is used, i.e., channel is divided into 8 timeslots and transmits data over the available channel. GPRS supports IP, Point to Point Protocol (PPP) and X.25 protocols for communication. GPRS is mainly used by mobile enabled embedded devices for data communication. The device should support the necessary GPRS hardware like GPRS modem and GPRS radio. To accomplish GPRS based communication, the carrier network also should have support for GPRS communication EDGE, High Speed Downlink Packet Access (HSDPA) are now replacing GPRS.

 Embedded Firmware
This refers to the control algorithm (Program Instructions) and or the configuration settings than an embedded system developer dumps into the code (Program) memory of the embedded system. This is an unavoidable part of Embedded system. Different ways of developing Embedded Firmware are
1. Write program in high level languages like Embedded C/C++ using an Integrated Development Environment (IDE). IDE will contain an editor, compiler,l inker, debugger, simulator etc. IDE is different for different family of processors. Eg., Keil with 8051 microcontrollers 2. Writing an Assembly level program

 Process of converting the program written in either a high level language or processor specific Assembly code to machine readable binary code is called HEX File Creation. The methods used for HEX File Creation is different depending on the programming techniques used. For a beginner it is always better to use High level language method, since it is easily portable. Also programs written in high level languages are not developer dependent. Any skilled programmer can trace out the functionalities and do suitable modification if sufficient comments and documentation is done. Debugging time will be very short. Assembly language approach is very time consuming and tedious. Each has their own style of writing. Knowing every instruction of the processor is not easy. Two types of control algorithm development are used in practice.
Infinite or loop or super loop approach, where control flow runs from top to bottom an then jumps back to the top of the program. It is similar to while (1) { } based technique in C. Second method deals with splitting the function to be executed into tasks and running these tasks using a scheduler which is part of General Purpose or Real Time Embedded Operation System (GPOS/RTOS)

 Other System Components

Reset Circuit Brown-out Protection circuit Oscillator unit Real-Time Clock (RTC) Watchdog Timer

 Reset Circuit
It is essential to ensure that the device is not operating at a voltage level where the device is not guaranteed to operate, during system power ON. The reset signal brings the internal regsiters and the different hardware systems of the processor/controller to a known state and starts the firmware execution from the reset vector. Reset signal can be active High or Low Since the processor operation is synchronised to a clock signal, the reset pulse should be wide enough to give time for the clock oscillator to stabilize before the internal reset state starts.

 Brown-out Protection Circuit

This circuit prevents the processor/controller from unexpected program execution behaviour when the supply voltage to the processor/controller falls below a specified voltage. It is essential for battery powered devices. Processor may not behave predictably if voltage falls below recommended voltage. It may lead to data corruption. A brown-out protection circuit holds the processor /controller in reset state, when the operating volatge falls below the threshold, until it rises above the threshold volatge.

The Zener diode Dz and transistor Q forms the heart of the circuit. The transistor conducts always when the supply voltage Vcc is greater than that of the sum of VBE and VZ. Moment Vcc drops below this threshold Q stops conducting. When Q is ON pulse is in High mode when Q in OFF reset pulse is Low.

 Oscillator Unit
Commonly clock circuit are built on the board. However, certain processors/controllers integrate a built-in-oscillator unit and simply require an external ceramic resonator/quartz crystal for producing the necessary clock signals. Quartz crystal and ceramic resonators are equivalent in operation , however they possess physical difference. Speed of the processor depends on the clock freq, but this freq cannot be blindly increased. The internal gates decides the threshold. The total system power consumption is directly proportional to the clock frequency. The accuracy of program execution depends on the accuracy of the clock signal. The accuracy of the crystal oscillator or ceramic resonator is normally expressed in terms of +/- ppm(parts per million)

 Real-Time Clock (RTC)

RTC is a system component responsible for keeping track of time. This supplies timing reference to the system. RTC is intended to perform in the absence of power. The RTC chip contains a microchip for holding the time and date related information and backup battery cell for functioning in the absence of power, in a single IC package. The RTC chip is interfaced to the processor or controller of the embedded system. For OS based embedded devices, a timing reference is essential for synchronizing the operations of the OS kernel. The RTC can interrupt the OS kernel by asserting the interrupt line of the processor/controller to which the RTC interrupt line is connected. One IRQ can be assigned to the RTC interrupt and the kernel can perform necessary operations like system date time updation, managing software timers etc when an RTC timer tick interrupt occurs. The RTC can be configured to interrupt the processor at predefined intervals or to interpret the processor when the RTC register reaches a specified value.

 Watchdog Timer
Watchdog timer is responsible to reset the embedded system when the execution of program hangs up. This is a Hardware timer for monitoiring the firmware execution Depending on internal implementation , the watchdog timer increments or decrements a free running counter with each clock pulse Generates a reset signal to reset the processor if the count reaches zero incase of decrement counter or highest value in case of up-counter. Firmware can initialize the watchdog counter before the start of execution

 If the firmware execution doesnt complete due to malfunctioning, within the time required by the watchdog to reach the maximum count, the counter will generate a reset pulse and this will reset the processor. If the program completes the execution then watchdog counter can be loaded with 0 (up counter) Most of the processors implements this as built-in component and provides status register to control the watchdog timer and watchdog timer register for writing the count value. Some processors have this as external circuitry also. The hardware /logic takes care of generating necessary enabling, disabling, count increment/decrement and reset generation The Microprocessor supervisor IC DS1232 integrates a hardware watchdog timer in it. Interrupt can also be generated instead of reset and interrupt handler can be programmed to handle the situation.

 PCB and Passive Components

PCB is the backbone of every Embedded System Along with ICs responsible for executing required logic etc. there are passive components like resistors, capacitors supporting the whole system. There are many subsystems like circuit responsible for supplying regulated (ripple free) power supply, spike suppressors etc which are of equal importance in defining performance of the system.

Characteristics and Quality Attributes of Embedded System

Characteristics of an Embedded System
1. 2. 3. 4. Application and domain specific-designed for one application can not be used for other Reactive and Real Time- responding to input and that to too quickly Operates in harsh environments-dusty, high temperature and vibration full atmosphere Distributed-Card reading, transactions, money counter and transaction printer in ATM are independent embedded systems. Coffee vending machine has card reader and vending unit which are separate ES. Supervisory Control and Data Acquisition (SCADA) Small size and weight-Small is comfortable, compact and easy to maintain Power concerns-devices consuming less power, devices with low power technology

5. 6.

 Application and Domain Specific

Intended to perform specific function not useful for generic functions

Reactive and Real Time

Changes in the real world need to be captured and ES must respond to it Event may be periodic or unpredictable one In case of unpredictable ,interrupts can be used. Response should be real time.

Operates in Harsh Environment

The areas of operation could be High temperature or dusty or vibration/ shock-full area

 Quality Attributes of Embedded System

These are the non-functional requirements that need to be documented properly in any system design. More concrete and measurable has better impact on system development process. 1. Operational Quality Attributes 2. Non-Operational Quality Attributes

 Operational Quality Attributes

Represents the relevant quality attributes related to the embedded system when it is in the operational mode or online mode
1. 2. 3. Response-Measure of quickness Throughput- No. of products, no. of transactions over a fixed time, Measured in terms of Benchmark Reliability- percentage of reliance of proper functioning or what is the susceptibility of the system for failure, Mean Time Between Failures (MTBF) and Mean Time Between Repair (MTTR) are used in expressing above.

4.

5.

6.

Maintainability- Reliability and Maintainability are complementary. Maintainability is closely related to system availability. Two categories Scheduled or Periodic Maintenance, Maintenance to unexpected failures Eg: Printer Security Confidentiality Integrity and Availability. Confidentiality deals with protection of data and application from unauthorized disclosure. Integrity deals with protection of data and application from unauthorized modification. Availability deals with protection of data and application from unauthorized users. Ex. Personal Digital Assistant (PDA). In case of shared one PDA is operated and available to individual through password, this is Availability. Not all data is accessible to everyone. Administrator defined security is used. This Confidentiality. Data available to users can only be seen but not alterable this is Integrity Safety This is possible damage to the operators, public and environment due to the breakdown or emission of dangerous radioactive or hazardous materials. Breakdown may due to failure of hardware or software. Safety analysis should be done during the design.

 Non Operational Quality Attributes

1. 2. 3. 4. 5. Testability & Debug-ability Evolvability Portability Time to prototype and market Per unit and total cost

 Testability and Debug ability

Ease of testing (both hardware & software) Debug-ability is a means of debugging the product as such for figuring out the probable sources that create unexpected behaviour in the total system. Both hardware and software debugging option need to be provided.

Evolvability
This is referred to as non-heritable variation. It is the ease with which embedded product can be modified to take the advantage of new firmware or hardware technologies.

 Portability
It is a measure of system independence The ease with which an embedded product can be ported on to a new platform is a direct measure of the re-work required. Standard embedded product should always be flexible and portable. In embedded products, the termporting represents the migration of the embedded firmware written for one target processor to a different target processor. Using high-level language in writing fimrware improves portability. If the firmware is platform independent it is still better.

 Time-to-Prototype and Market

This is the time elapsed between the conceptualisation of a product and the time at which the product is ready for selling or use. This time has to be as small as possible to beat the competition Delay in making may lead to outdate of the technology. Prototyping is an informal kind of rapid product development in which important features of the product under consideration are developed. If Prototype is developed fast time for final product can be speeded up.

 Per Unit Cost and Revenue

Product life cycle (PLC) has different stages:
Product development- idea discussion, prototyping, design and development. This stage has only investment no returns Product introduction product introduced to market. Generally low revenue in this stage Growth This stage product gains high market and revenue increases Product Maturity Revenue peaks up in this stage Product retirement revenue starts declining due to competition from similar products or change in technology