International Journal of Advances in Science and Technology, Vol. 3, No.

4, 2011

High-Performance Memory Cell Design at 32nm Technology based on CNTFET for Low-Power Embedded Systems
Rajendra Prasad S1, B K Madhavi2 and K Lal Kishore3
1

Department of ECE, ACE Engineering College, Hyderabad, AP, India srprasad447@gmail.com

Department of ECE, Geethanjali College of Engineering and Technology, Hyderabad, AP, India bkmadhavi2009@gmail.com
3

Department of ECE, JNT University, Hyderabad, AP, India lallishorek@yahoo.com

Abstract
In this paper a new design of a low-power and High-performance Memory cell based on carbon nanotube Field Effect Transistors (CNTFETs) is proposed. This Circuit utilizes different threshold voltages for best performance. In a Carbon Nano Tube (CNT), the threshold voltage can be adjusted by controlling the diameter of the tube, called chirality vector. In the proposed Memory cell design, all CNTFETs of the same type have the same chirality but N-type and P-type transistors have different chiralities. As figures of merit stability and write time are considered when selecting the chirality for the best overall performance. Extensive simulations have been performed in HSPICE using 32nm Stanford CNTFET model, to evaluate the power and stability of the CNTFET-based Memory cell, and compared this with standard CMOS basic Memory cell design. The CNTFETbased Memory cell demonstrates that it is significantly better than its CMOS counterpart.

Keywords: Carbon Nanotube Field Effect Transistor; Memory Cell Design; SRAM design; LowPower; High performance 1. Introduction
Embedded systems particularly targeted towards low-duty cycles and portable applications, such as mobile phones or PDAs, must have low energy consumption, as these systems are battery operated. In such systems, considerable amount of power is consumed during memory access, which has significant impacts on battery life. Hence, efficient power saving Memory cell designs needs to be explored for longer operation of battery powered applications. As Static Random Access Memory (SRAM) is the fastest random Access memory, so in this paper SRAM is taken as a Memory cell for highperformance. At Nano feature sizes, scaling has resulted in increased short-channel effects, reduced gate control, exponentially rising leakage currents, severe process variations, and high power density. As todays VLSI systems mostly rely on silicon MOS technology, the Industry Technology Roadmap for Semiconductors (ITRS) has predicted that in the nano regimes, the expected high density will encounter substantial difficulties in terms of physical phenomena and technology limitations, possibly preventing the continued improvements in figures of merit such as low power and high performance. Nanoscaled alternatives to bulk silicon transistors are therefore being pursued. New materials and devices have been investigated to replace silicon in nanoscaled transistors from the year 2015 and beyond, as per ITRS prediction. CNTFETs are promising due to their unique one-dimensional bandstructure that suppresses backscattering and makes near-ballistic operation a realistic possibility [1] [4]. Therefore, it is essential to develop a low power SRAM design technique for the new device technology such as CNTFET.

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International Journal of Advances in Science and Technology, Vol. 3, No.4, 2011 Design of fast and power efficient memory structures continues to be of the highest priority and ballistic transport operation and low off current make the CNTFET a suitable device for high performance and increased integration density of SRAM design. Moreover, the MOSFET-like model of the CNTFET is likely to be scalable down to 10nm channel length, thus providing a substantial performance and power improvement compared to the MOSFET model with minimum channel length of 32nm [5]. Therefore, a SRAM design implemented using CNTFETs requires a significantly smaller area than its CMOS counterpart. A resistive-load CNTFET-based SRAM cell has been proposed in [6]. However, large off-chip resistors i.e. 100M are needed in the configuration due to the current requirements of the CNTFETs. This resistive-load CNTFET-based SRAM cell design is modified with P-type transistors as active load to address this problem as proposed in this paper. The use of transistors with multiple threshold voltages is widely utilized in todays CMOS circuits to improve performance. The threshold voltage can be changed by applying different bias voltages to the bulk terminal of the CMOS transistors. The threshold voltage of CNTFET is determined by the CNT diameter. Therefore, CNTFETs with different threshold voltages can be accomplished by growing CNTs with different diameters i.e. chiralities. In this paper, a CNTFET-based SRAM cell design with optimized threshold voltages is proposed, assessed, and compared to the CMOS implementation of the same cell. Different diameters and therefore chirality, are utilized for the two types of CNTFETs (i.e. N or P). The optimum chirality is selected to achieve the best-combined performance in terms of stability, power consumption of the CNT-based SRAM cell.

2. CNTFET
To build a CNTFET, single walled carbon nanotubes (SWCNTs) are used due to their semiconducting and metallic properties and its ability to carry high current. It has already proven that carbon nanotubes can carry current density of the order 10A/nm. This is much higher as compared to standard metal wires which could carry 10nA/nm [7]. CNTFETs can have almost a near-ballistic transport characteristic because the mean free path for electrons in SWCNTs exceed close to 1 m. This will results in a much higher speed device as compared to silicon MOSFETs. These mention research concludes that carbon nanotubes have a promising for the future of nanoelectronics due to their superior electrical characteristic. In structural look, the CNTFET looks like a MOSFET. The only change in that he silicon channel is being replaced by carbon nanotubes. An SWCNT can act as either a conductor or a semiconductor depending on the angle of the atom arrangement along the tube. This is referred to as the chirality vector and is represented by the integer pair (n, m) [5]. A simple method to determine if a carbon nanotube is metallic or semiconducting is based on considering the indices (n, m), i.e. the nanotube is metallic if n=m or n-m=3i where i is an integer. Otherwise, the tube is semiconducting. The diameter of the CNT can be calculated from [5] as a function of m and n. Figure 1 shows the schematic diagram of the CNTFET [5]. Similar to the silicon device the CNTFET has four terminals, a dielectric film is wrapped around a portion of the undoped semiconducting nanotube, and a metal gate surrounds the dielectric. Figure 2 shows the equivalent circuit model implemented in HSPICE as proposed in [5]. Heavily doped CNT segments are placed between the gate and the source/drain to allow for a low series resistance during the on-state [8]. As the gate potential increases, the device is electrostatically turned on or off via the gate.

Figure 1. CNFET structure

Figure 2. Equivalent circuit model for the intrinsic channel region of a CNTFET [6]

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International Journal of Advances in Science and Technology, Vol. 3, No.4, 2011 The current-voltage (I-V) characteristics of the CNTFET are shown in Figure 3, and they are similar to those of MOSFET. The CNTFET device current is saturated at higher Vds (drain to source voltage) as channel length increases as shown in Figure.3, and the on-current decreases due to energy quantization in the axial direction at 32-nm (or less) gate length [5]. The threshold voltage is defined as the voltage required to turn on the transistor, and the threshold voltage of the intrinsic CNT channel can be approximated to the first order as the half bandgap which is an inverse function of the diameter [5]:

Vth

Eg 3 aV 2e 3 eDCNT

(1)

where a = 2.49 is the carbon to carbon atom distance, V = 3.033 eV is the carbon - bond energy in the tight bonding model, e is the unit electron charge, and DCNT is the CNT diameter. Then, the threshold voltage of the CNTFETs using (19, 0) CNTs as channels is 0.289 V because the DCNT of a (19, 0) CNT is 1.49 nm. Simulation results have confirmed the correctness of this threshold voltage. As the chirality vector changes, the threshold voltage of the CNTFET will also change. The threshold voltage of the CNTFET is inversely proportional to the chirality vector of the CNT. Figure 4 shows the threshold voltage of P-type CNTFET (PCNTFET) with CNTs of different chirality vectors. For N-type CNTFET (NCNTFET), the threshold voltage is determined similarly to the P-type CNTFET, but having an opposite sign [5]. The threshold voltage of the CNTFET only depends on the chirality vector of the CNT. Therefore, CNFFETs provide a unique opportunity for threshold voltage control by changing the diameter of the CNT [9]. Extensive research has been pursued for manufacturing wellcontrolled CNTs [10] [11]. In this paper, a CNTFET-based SRAM design is proposed and designed for best performance.

Figure 3. Current-voltage (I-V) characteristics of a ballistic CNTFET

Figure 4. Threshold voltage of P-type CNTFET with different Chirality vectors

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International Journal of Advances in Science and Technology, Vol. 3, No.4, 2011

3. Proposed SRAM Memory Cell Design

Figure 5 shows the conventional six-transistor (6T) SRAM Memory cell configuration used as the core storage element of most register file and cache designs in CMOS for low-power embedded applications and Microprocessors. With todays aggressive scaling, substantial problems such as power consumption and stability have already been encountered when the 6T SRAM cell configuration is utilized in CMOS at nanoscale ranges. In this paper, the 6T SRAM cell of Figure. 5 is designed using CNTFETs as shown in Figure. 6 and its performance is assessed to compare power dissipation and stability with standard CMOS SRAM cell design.

3.1 . Read Operation

Prior to the read operation, BL and BL_bar of Figure. 6 are precharged to high level. When the wordline signal WL is high, the access transistors M5 and M6 are turned on, and the data stored in the SRAM is read. However, a read-upset problem is present during the read operation, and this may change the data stored in the SRAM cell. The read-upset problem can be described as follows. Assume that the cell is currently storing 1 so that Q is 1 and Q_bar is 0. When WL is high, M5 and M6 are on and the voltage at node Q_bar will rise. An appropriate sizing ratio between M3 and M6 is required to limit the voltage at node Q_bar to be lower than Vth such that the stored logic value does not change during the read operation. In the traditional CMOS design, the M3/M6 ratio should be greater than 1.28 for this requirement [12]. For the CNTFET SRAM design, simulations have been performed to establish the sizing ratio of M3 and M6. The gate and source of M6 are connected to Vdd, and the gate of M3 is also connected to Vdd as the voltage at Q needs to be set to 1. The transistor size ratio of the two CNTFETs is measured as the number of tubes in the two CNTFETs unlike MOSFET. As mentioned in Section 2, the threshold voltage of the (19, 0) CNTFET is 0.289V. Therefore, the M3/M6 ratio should be kept greater than 0.5 to keep the voltage of Q-bar below threshold voltage. However, for fair comparisons, the M3/M6 ratio used in this paper for the CNTFET SRAM design needs to be greater than 1.4 to control the low state voltage below the threshold voltage of the 32nm MOSFET which is 0.18V [16].

Figure 5. CMOS 6T SRAM Cell

Figure 6. CNTFET 6T SRAM Cell

3.2. Write Operation

During the write operation, the wordline WL is high to allow the data on bitlines BL and BL_bar to be written into the SRAM cell. For a successful write to a SRAM cell, the pull up transistor should not be too strong. Assume that the SRAM cell is storing 1 and it is required to write a new data 0 into the SRAM cell. The node Q in Figure. 6 is going to be low, so the pass gate M5 must be significantly more conductive than the PMOS M2. In the traditional CMOS design, the M2/M5 ratio should not be

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International Journal of Advances in Science and Technology, Vol. 3, No.4, 2011 greater than 1.6 [12]. For CNTFET SRAM design, simulations have been performed to establish the size ratio between M2 and M5. The bias voltage on the gate of M2 is kept below Vth, and the bias voltage on the gate of M5 is Vdd. Any M2/M5 ratio of less than 1.6 can pull node Q below 0.289 V, which is the threshold voltage of a CNTFET with (19, 0) nanotubes. Similarly to the read operation, the M2/M5 ratio used in this paper for the CNTFET SRAM design needs to be less than 1 to ensure that the write voltage at node Q is not higher than the threshold voltage of the 32nm MOSFET i.e. 0.18V. Therefore, for the proposed CNTFET-based 6T SRAM cell design, the transistor size ratios among the pull up FET, the pull down FET, and the access transistors are M2/M5 = 0.5 and M3/M6 = 1.5. Ptype CNTFETs with one tube are used for M2 and M4, while n-type CNTFETs with three tubes are used for M1 and M3. The number of tubes used for M5 and M6 is two. As the channel length of the CNTFET decreases to 32nm or below, the drain current of the CNTFET decreases due to energy quantization in the axial direction. Phonon scattering in shortchannel devices further reduces the on-current [16]. As shown in Figure 3, the drain current of CNTFET decreases dramatically when the channel length is less than 20nm. Therefore, by considering area and performance, a 32nm gate length is chosen in this paper for the design of the CNTFET-based SRAM cell.

4. Simulation Results
Since the threshold voltage of CNTFET can be controlled by adjusting tubes diameter, the design of CNTFET-based circuits with different threshold voltages is possible because CNTs can be grown with different diameters [9] [11]. In this paper, N-type and P-type CNTFETs use CNTs that have different chirality vectors for the best performance. However, all N-type CNTFETs use CNTs with the same chirality vector and all P-type CNTFETs use the same chirality vector as well. The difference in chirality between N-type and P-type CNTFETs must also take into account the performance of the SRAM memory cell. As for CMOS SRAM, the threshold voltages of the pull-up Ptype FETs (M2 and M4 shown in Figure. 6) have a close relationship with the Static Noise Margin (SNM) of the SRAM cell. The SNM is defined as the maximum value of DC noise voltage that can be tolerated by the SRAM cell without changing the stored bit [13]. The SNM is commonly used as a metric for static stability of a SRAM cell [14]. To investigate the SNM of the proposed CNTFET SRAM, extensive simulations have been performed on CNTFET SRAM cells. HSPICE simulations are performed using 32nm Stanford CNTFET model for CNTFET 6T SRAM and Berkely Predictive Technology 32nm model for CMOS 6T SRAM. For the 6T SRAM cell configuration in Figure. 5, the worst-case stability condition occurs when the cell is accessed for read operation, i.e. the read SNM is lower than the hold SNM. The chirality vector of the PCNTFETs changes from (10, 0) to (22, 0), then the SNM of the CNTFET SRAM is increased [15]. The values of the read SNM of the CNTFET SRAM change little as the chirality vectors of the N-type CNTFETs change [15]. Therefore, for best stability, the chirality vector of the PCNTFETs must be adjusted. In this paper chirality vector of P-type CNTFET is varied from (10, 0) to (22, 0) by keeping chirality vector of NCNTFET is kept constant at (19, 0). The stability of the SRAM cell can be increased by decreasing the absolute value of the threshold voltage of the pull-up transistor by controlling its chirality vector. However, there is a conflicting constraint between performance and stability. At a better ability to hold data, it is also harder to write new data into the SRAM cell, i.e. it takes more time to write new data. To find the optimum chirality for both PCNTFETs and NCNTFETs, both the SNM and the write time must be considered. Table 1 shows the SNM and the write time of the CNTFET SRAM cell with different threshold voltages of the PCNTFET at 0.9V power supply and room temperature. Both the SNM and the write time increase with decrease of the absolute value of the threshold voltage of the pull-up transistor. For a highly stable and low delay design, a high SNM and a fast write time are desired. Therefore, the SNM is divided by the write time to find the best threshold voltage of the PCNTFET for both high SNM and fast write time. As shown in Table I, when the threshold voltage of the PCNTFET is |0.332V| for a (16, 0) SRAM cell, the ratio between the SNM and the write time is the highest among those CNTFET SRAM cells listed in Table 1. Therefore, the (16, 0) SRAM cell is selected for best overall performance. It is also shown in Table 1 that the ratio between the SNM and the write time for the CNTFET SRAM cell is significantly higher than for the CMOS SRAM cell, i.e. high stability is attained at a low write time.

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International Journal of Advances in Science and Technology, Vol. 3, No.4, 2011 Table 2 shows the comparison of CNTFET 6T SRAM Memory cell with CMOS 6T SRAM Memory cell in terms of Power and SNM. Table 1. SNM and Write Time of the SRAM Cells at 0.9V VDD at room temperature at (19, 0) NCNTFET chirality vector Chirality of SRAM Cell (10,0) PCNTFET (13, 0) PCNTFET
(16, 0) CNTFET (19, 0) CNTFET (22, 0) CNTFET 32nm CMOS SRAM cell

SNM (mV) 124 174

205 243 261 80

Write time (ps) 20.41 23.38

24.85 29.67 32.14 24.57

SNM/Write Time (mV/ps) 6.07 7.44

8.24 8.19 8.12 3.25

Table 2. Power and SNM Comparison of CNTFET and CMOS SRAM 6T Memory Cells Sl. No.
1 2

Parameter
Power (nW) SNM (mV)

CNTFET 6T SRAM
1.684 243

CMOS 6T SRAM
78.73 79

5. Conclusion
This paper has investigated the use of CNTFETs in 6T SRAM design. As the threshold voltage of the CNTFET can be easily controlled by changing the chirality vector of the CNTs, a CNTFET SRAM cell configuration with different threshold voltages is designed, which is made possible by using different diameters for the P-type by keeping N-type CNTs diameter constant, in the cell. The best chirality for the PCNTFETs was selected to achieve high stability and low power consumption. The proposed design shows significant improvements compared to the basic CMOS SRAM design in terms of power consumption and stability.

6. References
[1] [2]

[3] [4]

[5] [6] [7] [8] [9]

A. Rahman, J. Guo, S. Datta, M.S. Lundstrom, Theory of ballistic nanotransistors, IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 1853 - 1864, Sept. 2003 A. Akturk, G. Pennington, N. Goldsman, A. Wickenden, Electron Transport and Velocity Oscillations in a Carbon Nanotube, IEEE Trans. Nanotechnol., Volume 6, Issue 4, pp 469 474, July 2007. H. Hashempour, F. Lombardi, Device Model for Ballistic CNFETs Using the First Conducting Band, IEEE Des. Test. Comput., Vol. 25, Issue 2, pp 178-186, March-April 2008. Y. Lin, J. Appenzeller, J. Knoch, P. Avouris, High-performance carbon nanotube field-effect transistor with tunable polarities, IEEE Trans. Nanotechnol., Vol 4, Issue 5, pp 481 - 489, Sept. 2005. Stanford University CNFET Model website [Online]. Available: http://nano.stanford.edu/model.php?id=23. A. Bachtold, P. Hadley, T. Nakanishi, C. Dekker, Logic Circuits with Carbon Nanotube Transistors, Science, Volume 294, no. 5545, pp. 1317 - 1320, Nov. 2001. Rasmita Sahoo, R.R. Mishra 2009, Simulations Of Carbon Nanotube Field Effect Transistors, Birla Institue Of Technology and Science, India. J. Appenzeller, Carbon Nanotubes for High-Performance ElectronicsProgress and Prospect, Proc. IEEE, Volume 96, Issue 2, pp. 201 - 211, Feb. 2008. A. Raychowdhury,; K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design, IEEE Trans. Nanotechnol., Volume 4, Issue 2, pp. 168 179, March 2005.

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[10]

[11]

[12] [13] [14]

[15] [16]

International Journal of Advances in Science and Technology, Vol. 3, No.4, 2011 Y. Li, W. Kim, Y, Zhang, M, Rolandi, D. Wang, Growth of Single-Walled Carbon Nanotubes from Discrete Catalytic Nanoparticles of Various Sizes, J. Phys. Chem., Vol. 105, pp. 11 424, 2001. Y. Ohno, S. Kishimoto, T. Mizutani, T. Okazaki, H. Shinohara, Chirality assignment of individual single-walled carbon nanotubes in carbon nanotube field-effect transistors by microphotocurrent spectroscopy, Applied Physics Letters, Vol. 84, no. 8, Feb. 2004. A. Chandrakasan, W.J. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2000, pp. 290 - 296. E. Seevinck, F.J. List, J. Lohstroh, Static-noise margin analysis of MOS SRAM cells, IEEE J. Solid-State Circuits, Volume 22, Issue 5, pp. 748 - 754, Oct 1987. E. Grossar, M. Stucchi, K. Maex, W. Dehaene, Read stability and write-ability analysis of SRAM cells for nanometer technologies, IEEE J. Solid-State Circuits, Volume 41, Issue 11, pp. 2577 2588, Nov. 2006. S. Lin, Y.B. Kim, F. Lombardi, Design of a CNTFET-based SRAM cell by dual-chirality selection, IEEE Transactions on Nanotechnology 9 (1) (2010) 30-37. Berkeley Predictive Technology Model website [Online]. Available: http://www.eas.asu.edu/~ptm/.

Authors Profile
Rajendra Prasad S received his BTech (ECE) from SK University and MTech from SV University, Tirupati. He is pursuing Ph.D from JNTU, Hyderabad. He published 3 papers in National/International Journals/Conferences. His areas of interest include Low-Power SRAM Design, Low-Power High-performance Digital Circuit Design, VLSI, CNTFETs and Embedded Systems.

Dr. B K Madhavi received Ph.D from JNTU, Hyderabad. She completed ME from BITS-PILANI in the specialization of Microelectronics. She published 23 research papers in various National and International Journals and Conferences. Presently she is guiding 10 PhD Students and guided several BTech and MTech Projects. She is also reviewed research papers for IETE. She participated in several workshops, summer and winter schools, National, International conferences and also organized several National level workshops, student paper contests, and seminars etc. Her research interest include Microelectronics (VLSI Design, Low Power VLSI, Mixed Signal Processing), Wireless communications.

Dr. K Lal Kishore is a Senior Professor in Electronics and Communications Engg. Department of JNTUH University, Hyderabad. He has more than 127 Research Publications to his credit so far. He has produced 10 Ph.Ds and many more Research Scholars are working under his Guidance. He has won First Bapu Seetharam Memorial Award and S.V. Aiya Memorial Award from IETE for Research Contribution, Best Teacher Award from Govt. of A.P and many more National Level Awards. He has over 33 years of Experience in Teaching and Research. He has implemented number of Research Projects and developed many Laboratories in the Department. He has Post-Graduate and Ph.D Degrees from Indian Institute of Science (I.I.Sc) Bangalore. He wrote Six Text Books, on Electronic Devices, Circuit Analysis, Linear I.C. Applications, Electronic Measurements and Instrumentation and VLSI Design. He had held number of administrative positions in the JNT University, Hyderabd including that of Rector, Registrar, Director, Academic and Planning, Director School of Information Technology, Principal etc.

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