Fabiication of PN0S Tiansistois

Microfabrication Lab
Dr. Savage
California Polytechnic State University

By:
Nash Anderson
Michael Ray
ntroduction

Objectives
O To learn how to effectively use the microfabrication lab and its various equipment
O To make a Positive Metal Oxide Semiconductor with working transistors

Cross-section View of the FinaI Device





This is a view of what we would like our wafer's cross-section to look like after our final steps. There is no
way that our device would have channels as square and crisp as they are depicted above but a cross
section of our device should look similar.













Figure 1: Final cross-section of wafer


!rocess 8equence

Diffusion Mask

The first major modification of the device wafers was the application of an oxide layer to serve as a
diffusion mask. The target thickness of this mask was 8,000 Angstroms and our goal was to make it as
uniform and contain as little impurities as possible. The thickness and purity of this layer could have been
affected by many things. The furnace is a long tube in which the quartz boat sat inside with all of the
wafers. For an ideal environment there should have been water vapor flowing evenly across the surface
of each wafer the entire time and the temperature of the wafers should have consistently been 1050C.
This is probably unrealistic to think that both of these conditions were met. The furnace temperature
probably varied in different regions of the quartz boat. For instance, the wafers in the front portion of the
quartz boat were probably not the same temperature as the wafers in the back. The water flow also
probably was not consistently flowing across the surface of the wafers because of their compact
orientation in the quartz boat. The resulting thickness of the oxide layer came out thicker than 8,000
angstroms and this diffusion mask was a success for the purpose of our wafers.
Doping Active Regions
We doped our device wafers with boron (B155) and recoded the thickness of both wafers which can be
seen in the table 1 below. When we applied the dopant to the wafers there was a decent amount of
human error because we all put on various amount of dopant on our wafers and on wafer B-1 it was
streaky around the edges. n industry this process is all done with machines to get much closer
consistency in the dopant thickness. Our thickness also turned out to be thinner than it should have. This
is also human error from estimation of dopant applied. This could result in not having enough dopant to
diffuse far enough into the n-type wafer. Once the B155 was spin coated on all the wafers we placed
them in to the furnace at approximately 1050C for 90 minutes to diffuse the dopant into the wafer. A
representation of this can be seen in figure 2 below. Whenever we use the furnace there is always a
chance for impurities to enter the device but our wafers were able to make good active doped regions.

Thickness of Dopant on B-1 Thickness of Dopant on B-2
965.73 (nm) 968.96 (nm)
956.30 (nm) 981.71 (nm)
953.63 (nm) 972.26 (nm)
960.18 (nm) 963.42 (nm)
967.61 (nm)
Average: 958.96 (nm) Average: 970.79 (nm)


Table 1: Thickness of Boron (B155)




Add in junction depth information when get process report
FieId Oxide and Gate Oxide
We created the field oxide first through wet oxidation in the furnace. Our target field oxide thickness was
5,000 angstroms and we were able to get very close to this target. Table 2 below shows the thickness
that we achieved with an average of 5,375.4 angstroms.







After the field oxide was in place we administered the gate oxide. Our target for the gate oxide was 500
angstroms. We also used wet oxidation here and the gate oxide that resulted was much thicker than our
target of 500 angstroms. We did not measure the actual thickness of this oxide on the account of time. A
cross-section of the field and gate oxide layers can be seen below in figure 3.







MetaI Contacts

To create metal contacts we spun on positive photoresist and exposed it to lithography mask #3 then
sputtered on aluminum and put on lithography mask #4. Aligning the lithography mask #3 was probably
the most difficult process of this entire project. We used the layers from the process traveler to help us
Avg.
Thickness
(Angstroms)
5439 5440 5330 5349 5319 5375.4
SiIicon Wafer (N-Type)
Oxide Layer
P-Type Layer P-Type Layer
Figure 2. Cross-section representation post furnace treatment where
p-type source and drain have been formed through diffusion of boron
into the substrate.
Boron Dopant
Table 2: Thickness of Field Oxide
Si N-Type
P-type P-type
Field
Oxide
Gate
Oxide
Figure 3: Field and Gate Oxide Cross-sections
see the map of the chip. We basically had to look through three small holes from layer 3 and match those
holes to same spot on the wafer. Looking for the little numbers on layer two is what ultimately allowed us
to find the right location. The alignment of wafer two was only off by approximately one micron, but wafer
one was off by a whole die. When we were aligning wafer one believe we thought we were at the correct
orientation but in reality we were shifted down approximately 18 to 20 microns. This miss-alignment can
be seen in figure 5 below. f we would have realized how far off we were when we developed wafer 1 we
would have stripped the resist and repeated that process. Once mask #3 was exposed and developed we
etched the remaining oxide and began sputtering aluminum. The target thickness for the aluminum
sputter was 3000 angstroms but the machine we used was old and is not the best device for sputtering.
Although, we got enough aluminum on our devices for the purpose that we need don't believe we got
quite to 3000 angstroms. We also had a little moister get into our sputter and the surface of our devices
was slightly milky white.





















Figure 4: Wafer 2, and the exposed
metal contacts. Good alignment
























EIectricaI Testing
For the resistance tests wafer two had 40 ohms for the metal resistance and 6980 ohms for the diffusion
area. Wafer one had a metal resistance of 52 ohms and we could not get a measurement for the diffusion
area. The die that we tested just would not yield a resistance for the diffusion area and could be the result
Figure 5: Wafer 1 appears to be off by approximately 18 microns.
after mask#3
Figure 6: Wafer #2 after development of mask #4. This wafer was aligned much
better and is very close to where it should be in its alignment.
of a multitude of errors. The first error that would guess would be because layer 3 was not aligned
correctly and the metal contacts could have been too far out of place not allowing any current to go
through. t could also be due to the imperfections in the oxide layer that can be seen below as bluish dots.






































On the last day of lab we tested our device's transistors to see how much current and voltage would pass
through. Tables 3 5 below show all of the values we were able to get for wafer two at an applied gate
voltage of 1, 2, and 3 Volts. Wafer one would not allow any current through for a number of possible
reasons. The best explaination is that mask #3 was developed way out of alignment meaning that the
metal contacts were too far out of place to allow current to flow.



Figure 7: Above is a picture of a test structure in cell 9 that we tested for resistance. Boron
diffusion and aluminum serpentine test cell area to measure resistance. On the left is the
diffusion test area and the right is the aluminum test area. Scratches can be seen on
squares 7, 9, 10, & 12 from the resistance testing probes.
VoItage (VoIts) Current (mA)
1.0 0.08
2.1 0.34
3.1 0.69
3.9 1.3
5.2 2.2
6.1 2.7
7.1 3.2
8.0 3.9
9.9 4.9




























VoItage (VoIts) Current (mA)
1.2 0.4
3.1 1.7
4.4 2.2
5.4 2.7
7.1 3.5
8.8 4.3
10.1 5.1
VoItage (VoIts) Current (mA)
1.0 0.26
2.4 1.3
3.5 1.9
4.7 2.5
5.8 3.0
7.0 3.6
8.2 4.2
9.1 4.7
10.5 5.5
Table 3: Wafer 2 with Voltage
at the gate at 1 Volt
Table 4: Wafer 2 with Voltage
at the gate at 2 Volts
Table 5: Wafer 2 with Voltage
at the gate at 3 Volts
Table 6. Calculated resistance for
diffusion and aluminum serpentine test
cell.
ield Analysis

Estimate % of functional chips for each device wafer
Pics of wafers
Summarize in a table the yield
EIectricaI Testing
Electrical testing on device wafer 1 almost completely failed due to alignment as shown in Table 3.
Device wafer 2 was functional as seen in Table 4.









The calculated resistances of the serpentine channels are
shown in Table 6.
The values seen for the resistance of device wafer 2 as
compared to the expected calculated values are similar.
Device wafer 1 was so dramatically misaligned the 52C
resistance measured for the aluminum area will not even
be considered. The two devices on wafer 2 vary in resistance measurements and this is probably due to
differences in amount of aluminum sputtered and boron diffusion. The geometry of the serpentine strip is
no where near as perfect as our calculation was made to be. There will be a varying geometry throughout
the entire conductive volume of the test cell (Refer to Figure 7). The diffusion area resistance
measurements reflect this defect in that they vary by 300C.
Wafer 1

Diffusion
Area AI Area
Device
1
not
measurable 52 C
Device
2
not
measurable
not
measurable
Wafer 2
Diffusion Area AI Area
Device 1 7018 C 40 C
Device 2 6741 C 47 C

Diffusion
Area AI Area
Resistance 71.67D
Table 4. Resistance of diffusion serpentine
test cell.
Table 5. Resistance of aluminum serpentine
test cell.
Figure 8. The green diffusion layer
has connected by the inversion layer
as a voltage is applied on the gate.
n Figure 6, little changes in geometry can be seen and depth is not able to be distinguished. The
measured aluminum resistance is lower than the calculated resistance. This is most likely because when
we sputtered, we made sure more than enough aluminum was deposited onto the surface to make sure
we did not have to do the step over again. This would result in a larger cross sectional area which would
decrease resistance.
Device Characteristic Curves
Characteristic curves were created as shown in Figure 7 with each set of data varying the gate voltage
from 1-3V. These curves do not look like normal characteristic curves of a properly functioning PMOS
transistor. They should be more log-shaped.










The graph in Figure 7 is not supposed to take a linear shape
like it did. t should hold a more logarithmic shape and level off
at a certain current. This means that something in our device is
probably shorting the transistor or it is flowing through the
device without having to hardly apply any voltage on the gate
meaning the diffusion areas were much too large connecting
the source to the drain. The inversion layer should form when
a voltage is applied as shown in Figure 8. For some reason
however, our devices are not functioning in this manner.

Device Wafer 2 Characteristic Curves
-1
0
1
2
3
4
5
6
0 2 4 6 8 10 12
V(ds)
I
(
d
s
)
VG = 1
VG = 2
VG = 3
Linear (VG = 3)
Linear (VG = 1)
Linear (VG = 2)
Figure 7. PMOS transistor characteristic curves for varying gate voltage (1-3V). As the
voltage applied across the drain and source rose the current did as well creating a linear
plot when fitted to a trendline.
Waste of Processes
With the techniques available in the MatE microfab lab here on campus, we use many processes that
involve chemical etching which produces many liters of waste to process one batch of wafers. The
breakdown for volume of chemicals disposed is shown in Table 7.

ChemicaI Piranha BOE
Resist
Stripper DeveIoper Resist HDMS
AI
Etching
DI
Water
# of Uses 8 5 4 4 8 8 1 18
TotaI
Liters
of aII
Waste
Amount
(L) / Use 2.5 2.5 2.5 1.4 0.003 0.003 2.5 2.5
TotaI
Waste 20 12.5 10 5.6 0.024 0.024 2.5 45 95.648

The waste must be picked up by a chemical specialist which will safely breakdown or dispose (incinerate)
the chemicals. None of the waste that we produce is reusable and the chemicals we use have health
hazard ratings varying from 1- 4.
To minimize toxic waste we would have to change our processing methods. nstead of chemical
etching we would have to go to plasma or a reactive ion etching. Physical vapor deposition uses ions that
bombard the surface and "physically remove material. This would also solve problems of under etching
that exists in wet etching. This machinery would be very expensive and beyond budget to buy for our
microfab. lab, but it would eliminate liquid waste. These processes would also take much longer and we
would not be able to process multiple wafers at a time like we do with wet chemical etching.

ConcIusion
With the processing steps taken to complete our device wafers, our yield was 1 functional wafer with
estimated 81% device yield. The malfunctioning device wafer 1 was due to the third photolithography
alignment error that left our wafer dramatically misaligned which would not allow any connections. Further
investigation should include research as to why our characteristic curves of device wafer 2 had the linear
shape instead of a logarithmic.

Table 7. Representing the volume of disposed chemicals throughout the quarter during wafer
processing. n total, an estimate of 95.6 liters of waste was produced.