UNIVERSITY OF NOTRE DAME DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CSE-221L Laboratory MG6 /HD6 March 30, 2004

Design of a Binary Multiplier

Combinational and Sequential Circuit Realizations Introduction
The previous experiments have demonstrated the use of combinational and sequential logic in the design of digital circuits, and have employed both Mentor Graphics simulation on Sun workstations and physical experimentation with actual hardware in the laboratory. This last experiment is a more elaborate design experience using most of the concepts and techniques that you have studied in the class and laboratory throughout the semester. The objective of the experiment is to design a circuit which accepts two 4-bit unsigned binary numbers as input, and produces the corresponding 8-bit product as the output. There are many ways of accomplishing this task. We will investigate two methods in this project: a combinational logic solution using a Read-Only Memory (ROM), and a sequential circuit using a counting procedure. This is a three-week project with parts MG6 and HD6 denoting Mentor Graphics design software, and laboratory Hardware, respectively. Part MG6, the schematic creation and simulation using Mentor Graphics Design Architect and QuickSim, should be completed first. Part HD6 will utilize the IDL-800 Logic Lab units during the final week of class. Each laboratory team of two students will submit a single formal report for this project. Specifications for this report are given on Page 13 of this document. You will meet in Room 177 Fitzpatrick Hall during the week of April 5-9 for a discussion of the project, and execution of the ROM design in Part MG6A. There will be no formal laboratory sessions during the week of April 12, while you are working on your project. The laboratory will be open during scheduled lab times so that you may experiment with your designs as you build them. Each team will be loaned an IDL-800 breadboard for construction of the hardware counting multiplier. Your written report will be turned in at your regular lab session in Room 208 Cushing during the period from Monday April 19 through Friday, May 23, at which time each team will demonstrate the operation of its hardware multiplier, and the laboratory instructors will administer individual oral examinations which will constitute 10 percent of the laboratory grade.

References
The following references are in the textbook, Introduction to Digital Logic Design, by John Hayes, Addison-Wesley, 1993. The relevant pages will be photocopied and distributed to each lab team by the TA during the week of April 1. 1. For discussions and examples of a ROM-based realization of a binary multiplier, see pages 7374 and pages 259-260. This method will be used in part MG6A of the project. 2. The design of a 2 2 binary multiplier is presented on pages 340-342 as an example of multiple-output combinational logic design using basic gates for the hardware. 3. A counter-based design for a general n n binary multiplier is shown as Example 8.8 on pages 660-664. It is a sequential machine composed of three counters and five-state one-hot

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controller, using SSI and MSI components. An alternative approach to the design of this counter-based multiplier, using algorithmic state machine (ASM) charts, is presented on pages 684-691. We will use a variation of this approach for parts MG6B and HD6 of this project. 4. The design of an 8 8 bit shift-and-add multiplier from an ASM chart is presented as Example 8.10 on pages 691-698. We may use this design as an example in class, with the hardware simplification discussed in Problem 8.69 on page 712.

Part MG6A. ROM Realization of a Binary Multiplier

We may think of a multiplier as a combinational logic circuit which takes two N-bit values as the input and produces a corresponding 2N-bit output. This is a reasonable approach for values of N less than 10. A ROM is a good solution because it requires only one chip, but it does require that the appropriate codes be placed into the ROM. Since there are 2N inputs, there are (2N)2 corresponding minterms or address locations in the ROM, and each address must have a 2N-bit value corresponding to the product. For this experiment, with N = 4, we require a ROM with 256 8-bit words. We will use the 82LS135 PROM that is available in the MGC Board Process Library. Your Design Architect schematic will consist only of this chip, two input ports and one output port. For QuickSim simulation you must set up a file that contains the contents of the ROM in a specified format. Follow the procedure given here.

a) Schematic Creation with Design Architect

1. In your Logic directory, invoke Design Architect, and open a new sheet with Component Name MG6A. Obtain an ND border of size a with full-size symbols, and enter appropriate values for the project name, your name, course number and the date. 2. Obtain these circuit components from pull-down Library > MGC Generic Libraries: ground, portin, portout, ripper 4x1 and ripper 8x1. 3. Obtain the ROM from palette [ADD/ROUTE] LIBRARY > Memory. In the Select Memory window choose Type: PROM, and select List by Memory Organization. Scan the list to see the variety of available ROM sizes, and then select the 256x8 82LS135, and click OK. 4. Use the COPY and MOVE commands to place two input ports on the left side, and one output port on the right side of your schematic. Assign the following names to your ports: A(3:0), B(3:0), P(7:0). The first two names are associated with the 4-bit input ports on the left side of the schematic, and the third name is associated with the 8-bit product at the output port on the right. 5. Make a copy of the ripper 4x1 element, and then "wire" the elements together. ROM inputs 0 through 3 correspond to input port A(0) through A(3), ROM inputs 4 through 7 correspond to input port B(0) through B(3), ROM outputs 0 through 7 correspond to output port P(0) through P(7). Connect the two ROM EN terminals to ground in order to enable the ROM output. Use [TEXT] SEQUENCE TEXT to assign appropriate numbers to the ripper R values. 6. Unselect All, and invoke [TEXT] CHANGE VALUE to change the path name at the bottom of the ROM symbol to the full path name of a file which you will create later, for example, /afs/nd.edu/.../MG6A/ROM_file. Use function key F1 to select the text, and use the popup menu to Change Height > 0.5 x Pin Spacing. 7. Check, save, and obtain a printed copy of the completed schematic sheet.

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b) Simulation with QuickSim II

1. Since the manual computation and preparation of the 256 values to be stored in the ROM would be a lengthy and error-prone procedure, you should write a computer program (about ten lines of C code, including comments, as demonstrated in lab) to generate the ROM_file in the following format: # ROM_file for 82LS135 4-bit multiplier 00/00; 01/00; ... FE/D2; FF/E1; This file contains a comment line, followed by 256 rows, each with one entry. Each entry specifies one of the 256 ROM addresses and the corresponding output for that address, all in hexadecimal. The slash separating the address and its contents, and the terminating semicolon are required syntax. Note that we are essentially storing a hexadecimal multiplication table in the ROM, where the entry AB/PP represents the multiplier and multiplicand as single hex digits A and B, and the corresponding product PP as two hex digits. Obtain a printed copy of your program for inclusion in your report. Use Unix commands or Design Manager to store the ROM_file as .../MG6A/ROM_file. Invoke QuickSim from the Design Manager by selecting the MG6A component, and using the right mouse button to select QuickSim from the pop-up menu. Click on OPEN SHEET in the QuickSim Palette to obtain a schematic window. Create a trace window for the three ports in the schematic. Configure the traces to be in the following order, from top to bottom: A(3:0), B(3:0), P(7:0). To obtain a force file, invoke either pop-up (QuickSim) > Force > From File... or pull-down Setup > Force > From File... In the resulting Load Forcefile dialog window, type exactly $MGC_HOME/user/logic/MG6A_forces_800 Run the simulation with the typical chip delay, rather than the default unit delay. To accomplish this, click Palette [SETUP] TIMING MODE. In the Change Timing Mode dialog window which appears, select Change > Full Delays Typ. Run the simulation for 800 ns. To obtain an attractive plot which fills the page, invoke the pop-up menu Setup > Window and then enter the following values in the resulting Setup Trace Window dialog box: Domain label interval 100 Curve height 50 Domain pixels/interval 100 Curve spacing 40 Domain area height 40 Margin 10 Name area width 80 Display Radix Decimal Select File > Print > Active Window Enter the values for the start and end times of the plot as follows: Begin Domain 0 End Domain 820 Check that the results are correct. If not, you may modify your schematic in design architect, save it, return to QuickSim and use [DESIGN CHG] RELOAD MODEL > All to try again. This procedure will not work for the invocation of a schematic having a different name. 3

2. 3. 4. 5.

6. 7.

8.

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9. Use palette [DBG GATES] DELTAS to determine the delay time of the ROM. 10. Close QuickSim without saving. Study the simulated output waveforms and write a discussion of the results in your report, including the value of typical delay time found in Part 9.

Part MG6B. A Sequential Circuit Multiplier Realization

The ROM multiplier realization becomes impractical for larger values of N. For example, a ROM for multiplication of two 16-bit integers would require over 4 trillion 32-bit words, or 16 thousand Megabytes of memory. In References 3 and 4, Hayes gives several sequential circuit approaches to multiplier design, which require less memory, but take more execution time. The counter-based design (Reference 3) employs three counters: a 2N-bit up-counter for the product, and two N-bit down-counters: one each for the multiplier and the multiplicand. It is based on the principles that multiplication is repeated addition and that addition is repeated incrementing. We will implement and simulate a variation of this counting multiplier with Mentor Graphics tools, and then construct the multiplier in hardware with the IDL-800 Logic Lab units. A system block diagram of the counting multiplier is shown on the next page. The product is generated in Counter 3, which consists of the 74LS390 dual BCD counter used in Experiment HD5, followed by a 2-bit ripple counter implemented with a 74LS76A dual JK flip flop. This composite counter will have a range from 0 to 399 (a Modulo 400 counter), which is more than sufficient to accommodate the largest product of 15 x 15 = 225. Two 74LS169B 4-bit binary up/down counters are configured as down-counters 1 and 2, associated with the multiplicand and the multiplier, respectively. We will assume that the values of the multiplicand N1(3:0) and multiplier N2(3:0) remain constant for the duration of the multiplication operation, so that no additional data registers are required. The operational behavior of the 74LS169B counter can be inferred directly from its ANSI symbol, which you should use in your Design Architect schematic. The control unit is a finite state machine which implements the multiplication algorithm in accordance with the Algorithmic State Machine (ASM) Chart shown in Figure 2 on Page 6. Note that this ASM Chart uses only two states, as contrasted to the ASM Chart on Page 684 of the Hayes text, which uses five states. The Hayes controller on Page 690 of the text uses five flip-flops in a one-hot design, whereas our design requires only one flip-flop. The Mentor Graphics Design Architect implementation for simulation of this design will consist of three schematic diagrams in a two-level hierarchical configuration. The top-level schematic will correspond directly to the block diagram in Figure 1 on Page 5, containing the 74LS169B down-counters 1 and 2, a symbol for the composite up-counter 3, and a symbol for the controller. You will create separate level-2 schematics for the up-counter and the controller and invoke automatic generation of corresponding symbols which may then be inserted into the toplevel schematic. All ICs used in this design must be selected from the Hardware Lab kit because you will implement the design on the IDL-800 Logic Lab after you obtain a satisfactory Mentor simulation.

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Product Count 10-Bit Up Counter 3 10 P 2-Bit Binary MSD 8-Bit BCD LSDs Multiplicand 4 N1 4-Bit Down Counter 1 Count Enable Load Clock Zero Clear Clear

Control _INC3 _CLR3 CLR3 ST _DCR1 FG _LD1 CLK _ZER1 RDY Count Enable _DCR2 _LD2 CLK _ZER2 Ready _RST Reset Start

Clock

4 CT1

Multiplier 4 N2 4-Bit Down Counter 2

Load Clock Zero

4 CT2

Figure 1. Counting Multiplier Block Diagram

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RST State S0 RDY

START ? Y

Clear the Product in Up-Counter 3 Load Multiplicand N1 into Down-Counter 1 Load Multiplier N2 into Down-Counter 2 State S1

Counter 2 = 0 ? N

Counter1 = 0 ?

Decrement Counter 1 Increment Counter 3

Decrement Counter 2 Load N1 into Counter 1

Figure 2. ASM Chart for Counting Multiplier

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Read the cited text references to fully understand the logical behavior of this multiplier. The table below shows the IC components (in your hardware lab kit) that are available to implement this circuit. You should be familiar with these devices from experience in the previous experiments. Nine of these IC chips are dedicated to specific uses as indicated in the Description column. Although the four chips specified for use in HD6 will not appear in the MG6B simulation, they cannot be used for other purposes in MG6B. Since the IDL-800 breadboard will accommodate a maximum of 12 IC chips, your design is constrained to using not more than three additional chips from the items having no pre-assigned application in the table. IC 74LS00 74LS00 74LS02 74LS04 74LS08 74LS10 74LS20 74LS32 74LS74A 74LS76A 74LS76A 74LS86 74LS138 74LS153 74LS157 Description Quad 2-input NAND Quad 2-input NAND Quad 2-input NOR Hex Inverter Quad 2-input AND Triple 3-input NAND Dual 4-input NAND Quad 2-input OR Dual D Flip-Flop Dual JK Flip-Flop Dual JK Flip-Flop Quad 2-input XOR 1 of 8 Decoder Dual 4-input MUX Quad 2-input MUX 7-Segment Display controller in HD6 Multiplicand, down-counter 1 Multiplier, down-counter 2 1 for control states, 2 for Start signal processing, 1 spare Lower 8 bits (two BCD digits) of up-counter 3 Clock generator for 7-segment display controller in HD6 Most significant 2 bits of composite up-counter 3 7-Segment Display controller in HD6 Application 2 to 1 MUX for Decimal Points in HD6 (one spare gate)

74LS169B 4-bit Up/Dn Counter 74LS169B 4-bit Up/Dn Counter 74LS175 74LS194 74LS390 MC14584 Quad D Flip-Flop 4-bit Shift Register Dual Decade Counter Hex CMOS Schmitt

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a) Multiplier Controller Design

The controller is a sequential machine whose ASM chart is given in Figure 2 on Page 6. Since the chart has only two states, we require only one flip-flop, with output QA. We may then assign state values for S0 and S1 as QA=0 and QA=1, respectively. Since the controller output CLR3 is simply the complement of _CLR3, we will eliminate CLR3 from the following procedure, keeping in mind that it has to be implemented in the final design. 1. Refer to the ANSI symbols of the counter ICs to determine the actions and priorities of the associated control signals. Note for instance that an active _LD1 signal (equal to 0) will override the count-enable input _DCR1, giving rise to a don't care (hyphen) in the table below. 2. Using the specified state assignments and the counter mode characteristics, trace all paths through the ASM chart and complete the corresponding transition/output table below. Output DA is the next-state variable QA+ . Complete this table to account for all 16 combinations of the four input variables. Note that each hyphen in the input columns accounts for two combinations, and corresponds to a missing variable in a product term. QA START _ZER1 _ZER2 DA 0 0 1 1 1 3. The completed table from Part 2 expresses each of the seven outputs as a sum of product terms in the four input variables. This is a PLA format, but it can be used for gate-level logic as well. Now simplify the logic using the espresso logic minimization program. Create a file called MG6B.espin containing your table from Part 2, in the following format: .i 4 .o 7 .ilb QA START _ZER1 _ZER2 .ob DA _LD1 _DCR1 _LD2 _DCR2 _CLR3 _INC3 00-- 0111111 01-- 10-0-01 1 1 .e 0 1 0 1 _LD1 1 0 _DCR1 1 _LD2 1 0 _DCR2 1 _CLR3 _INC3 1 0 1 -

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The first two lines specify the number of input and output variables, respectively, and the next two lines give the labels for the variables in the order in which their values are written in the tabular data. The data lines are an exact reproduction of the entries from the table of Part 2. Invoke man espresso and man -s 5 espresso for details. Save your file and then invoke the minimizer as follows: espresso MG6B.espin The espresso program will return the simplified output in the same format as the input, but it will usually contain fewer product terms and more hyphens, corresponding to fewer gates and fewer gate inputs. Further simplification may sometimes be obtained if the polarity of one or more outputs is changed. If your invoke espresso with the switch -Dopo, the program will try various combinations of output polarities and give an "optimal" configuration in the same format as the input, with an additional comment line containing a bit string corresponding to the output variables in the following format: #.polarity 0111010 A zero in this string indicates that the polarity of the corresponding output must be changed, and a one indicates that the polarity of the corresponding output remains unchanged. Thus you would realize the network as if the polarity comment were not present, and then attach logical inverters to all outputs which have corresponding zeros in the polarity comment. Try the polarity option with the invocation espresso -Dopo MG6B.espin Obtain printed copies of your espresso input and output files for inclusion in your report. From inspection of the espresso outputs create a corresponding circuit realization using a minimum number of gates of any type listed without a pre-assigned application in the table on Page 7. Keep in mind that you can use only three IC packages for the control unit. 4. Practical considerations for hardware implementation on the IDL-800 Logic Lab units require that the additional circuitry shown in Figure 3 on Page 10 be included in the controller, and should also be included in the Mentor Graphics schematic. The input ST is an asynchronous Start input from push-button Switch B on the IDL-800. The switch is debounced internally with an RS flip-flop, and the output remains high as long as the button is depressed. In order for a depression of the switch to initiate a single multiply operation, the two flip-flops with AND Gate 1 produce a single synchronized pulse with a duration of one clock period at the output START, regardless of how long the switch is depressed. This behavior is illustrated by the waveforms beneath the schematic in Figure 3. The system clock for the multiplier will be derived from the IDL-800 Function Generator OUT shown as the signal FG in Figure 3. An LS gate, shown here as AND Gate 2 must be used to obtain a suitable TTL clock signal, CLK, which is connected directly to the clock inputs of the state flip-flop and the down-counters 1 and 2. The controller _DCR1 and _DCR2 outputs are connected to the G6 count enable inputs on the respective down-counters. Up-counter 3 counts on a negative clock transition, and has no count-enable input. Therefore NOR Gate 3 must be used to provide a gated clock with negative phase at _INC3. The gate signal X is the _INC3 signal derived in Part 3 with the tacit assumption that the counter had separate clock and count-enable inputs. The waveforms in Figure 3 show that the output signal _INC3 from the NOR gate (negative logic symbol) will trigger up-counter 3 on a negative clock edge which is synchronous with the positive edge of the system clock which triggers down-counter 1. 5. Use your design of Part 3 with the augmentations of Part 4 to create a schematic for the controller using components listed in the table on Page 7, with the three IC package limit.. 9

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April 6, 2000 Synchronized Unit Pulse 1 START X

ST

D1 C

Q1 Q1

D2 C

Q2 Q2

_INC3 CLK

FG FG CLK ST

Q1

Q2

START

FG CLK X _Enable INC3 _INC3

Figure 3. CSE-221L HD6 Clock and Start Control

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b) Schematic Creation with Design Architect

1. Invoke the Design Architect, and open a new sheet with MG6B_control for the Component Name. Obtain an ND border of size b with full-size symbols for your schematic, and enter appropriate values for the project name, your name, the date and the course number. 2. Obtain circuit components from the MGC BPL Library, as required for your design from Part a)5. The input and output ports should have the names shown inside the controller block in Figure 1 on Page 5: Input ports _ZER1, _ZER2, _RST, FG and ST, and output ports CLR3, _CLR3, _INC3, _LD1, _DCR1, _LD2, _DCR2, RDY and CLK. 3. Use COPY and MOVE to place components. If two ports with different names are associated with the same net, then connect them together with the following selected element: [ADD/ROUTE] LIBRARY > Connectivity Symbols > Net Connector 4. "Wire" the elements together in accordance with your design, check, and save the schematic. 5. Create a symbol for controller by invoking pull-down Miscellaneous > Generate Symbol. You may edit the symbol to change its shape and/or port locations. Check and save the symbol. You will get some messages about ports not being on the interface when checking the first time, but these messages should disappear if you check again after saving. 6. Close the controller symbol and the controller schematic. 7. Open a new schematic with the name MG6B_upctr, and obtain an ND border of size a with full-size symbols. Obtain MGC BPL Library components 74LS390, 74LS76A, portin, portout, Vcc, and MGC Genlib component ripper 4x1. The input and output ports should have the names shown inside of the Up-Counter 3 block in Figure 1 on Page 5: Inputs _INC3, _CLR3 and CLR3, and output P(9:0). 8. Create a 10-bit modulo 400 counter with the lower 8 bits corresponding to two BCD digits as shown on the schematic in Experiment HD5, and the upper 2 bits as a modulo 4 ripple counter using JK flip-flops connected as T flip-flops. 9. Repeat Steps 4 through 6 above to check, and save the schematic, and create a symbol. 10. Open a new schematic with the name MG6B_top and obtain an ND border of size b with fullsize symbols. Obtain MGC BPL Library components 74LS169B, portin, portout, Gnd, and MGC Genlib component ripper 4x1. The input and output ports should have the names of the external signals in the top-level block diagram in Figure 1 on Page 5: Inputs _RST, CLK, ST, N1(3:0), N2(3:0), and outputs P(9:0), RDY, CT1(3:0), CT2(3:0). 11. Select CHOOSE SYMBOL in the schematic_add_route palette to obtain your MG6B_control and MG6B_upctr elements. Wire the elements together in accordance with your design, check, and save the completed schematic sheet.

c) Simulation with QuickSim II

1. Invoke QuickSimII on your top-level schematic: quicksim MG6B_top & 2. Click on OPEN SHEET in the QuickSim Palette to obtain a schematic window. 3. Create a waveform window for all ports in the schematic, and configure the traces to be in the following order, from top to bottom: RST, ST, N1(3:0), N2(3:0), CLK, CT1(3:0), CT2(3:0), P(9:0), RDY 4. To simulate multiplications 2x3 followed by 3x2, invoke pop-up menu Force > From File... In the resulting Load Forcefile dialog window, type exactly $MGC_HOME/user/logic/MG6B_forces_5000 11

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5. Run the simulation in the default unit delay mode for 5000 nanoseconds and obtain a printer plot of the waveforms for a domain of 0 to 5000 ns. 6. Use palette DEBUG GATES > DELTAS to determine the multiplication time in nanoseconds for both 2x3 and 3x2 by measuring the time from the falling edge of RDY to the next rising edge of RDY. Include these values in your report, and explain why they are different. 7. Reset the state of the simulator. Delete the forces using pull-down Report > Waveforms... Forces OK Select all of the forces in the forces window, and use pop-up Delete twice. Load the force file to multiply 15x15 from $MGC_HOME/user/logic/MG6B_forces_50000 Run the simulation for 50000 ns. Study the simulated output waveforms and discuss the results. You may wish to expand areas of the waveform display to see the details of the state transitions. You may also wish to test for other values of the multiplier and multiplicand to see if the correct product is obtained. 8. Use popup Setup > Window... to set up Domain label interval = 600, Curve height = 30 and Curve spacing = 20. Obtain a printer plot for a domain of 45000 to 49000 ns.

Part HD6. Hardware Implementation of the Counting Multiplier

The objective of this hardware laboratory is to experimentally verify the operation of the counting multiplier on the IDL-800 Logic Lab. Be sure that you have a circuit that simulates correctly before you begin this part. In this experiment we use the CMOS Schmitt Trigger clock for the display multiplexer, and the Function Generator for the multiplier system clock. Although the three schematics of Part MG6B contain all of the components required to simulate correct behavior with Quicksim, they do not contain the circuitry required to display the product on the 7-segments LEDs of the IDL-800 Logic Lab. Also, the gates do not display the pin numbers that are required for the hardware setup. A fourth schematic showing the interface with the IDL-800 is given on Page 14. 1. Be sure that your total design on four schematics uses not more than twelve IC packages. To annotate the components in your MG6B schematics with IC package identifiers and pin numbers for use in the hardware lab, we will use the Design Manager to invoke the Design Viewpoint Editor (DVE) to create a Printed Circuit Board (PCB) viewpoint, and then invoke Board Architect (brd_arch) to automatically perform the packaging and pin numbering, as follows: 2. Type dmgr & to invoke the Design Manager, and select your MG6B_top component in the navigator window. 3. Use the Right Mouse Button to invoke pop-up menu item Open > DVE 4. In the DVE window, use the LMB to invoke pull-down menu item Setup > PCB, and then when the setup is finished, invoke pull-down MGC > Exit to terminate DVE. Also close the auxiliary DVE window. 5. In Design Manager, select your MG6B_top icon, and use the RMB to invoke pop-up menu item Open > brd_arch Note that Board Architect displays the schematic with package identifiers U1, U2, ..., and all pin numbers in red. To retain these in the schematic, use pulldown Miscellaneous > Merge Annotations > All. Obtain a printed copy of your annotated schematic with pull-down File > Print Sheet.

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Open down on the control block and note that Board Architect has attached package identifiers and pin numbers for the entire design. To save these notations, again invoke pull-down Miscellaneous > Merge Annotations > All. Obtain a printed copy of your annotated schematic with pull-down File > Print Sheet. 7. Repeat Part 6 for the up-counter block. 8. Finally, MGC > Exit with Yes for saving the schematic and PCB design data base. 9. Determine a layout of chips on the breadboard with a view toward minimizing the wiring complexity. Refer to the chip pin layouts in the class web notes or previous experiments. 10. Wire your circuit on the breadboard in accordance with the four schematics, and use the 8-inch reinforced leads for connections between the board and the IDL-800 connectors. Adjust the Function generator frequency to observe your multiplier behavior at different speeds. You will have continuous access to the Hardware Laboratory in Room 208 Cushing to test your design before the final presentations that will be held in your assigned laboratory between April 19 and April 23.

Formal Report
Write a two or three-page narrative discussing your results, the difficulties which you encountered, and what you learned from this experiment. Include all of the tables, schematics, waveform charts and espresso files, as requested in the experiment procedure, and make appropriate references to them in your narrative. Your report should be prepared with a word processing program, and it should include a cover sheet. The supporting documentation must include: 1. MG6A a) 7. Page 2: Schematic for the ROM realization. 2. MG6A b) 1. Page 3: C program source code for ROM contents generation. 3. MG6A b) 7. Page 3: Delay timing simulation of the ROM realization. 4. MG6A b) 9. Page 4: Measured delay time of the ROM. 5. MG6B a) 3. Page 9: Final copies of espresso input and output files. 6. MG6B c) 5. Page 12: Unit timing simulation of MG6B_top from 0 to 5000 ns. 7. MG6B c) 6. Page 12: Measured multiplication times for 2x3 and 3x2. 8. MG6B c) 8. Page 12: Unit timing simulation of MG6B_top from 45000 to 49000 ns. 9. HD6 5. Page 12: Annotated Schematic for MG6B_top. 10. HD6 6. Page 13: Annotated Schematic for MG6B_control. 11. HD6 7. Page 13: Annotated Schematic for MG6B_upctr. 12. A copy of this Laboratory MG6/HD6 document, printed duplex (two-sided). All of the annotated schematics for the counting multiplier should show pin numbers and package reference codes corresponding to the actual hardware configuration. Due Date: This report is due in your assigned laboratory period between April 19 and April 23.

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