BCN1043

COMPUTER ARCHITECTURE and ORGANIZATION

Chapter 4 Computer Interconnection

Overview
COMPUTER COMPONENTS

COMPUTER FUNCTIONS

INTERRUPTS

INTERCONNECTION STRUCTURES OLDER BUS TYPES

ISA MCA

BUS INTERCONNECTION

EISA VLB

PC BUSES

PCI

AGP

COMPUTER COMPONENTS

A computer system consists of two major component: Hardware and software.

Hardware(CPU, memory, system bus and I/O.) Software (system software-OS, application software)

Central Processing Unit (CPU) or microprocessor controls the operation of the computer and performs its data processing functions.

Memory is the part of computer where program and data are stored.

A bus is a communication pathway connecting two or more devices. System bus is a bus that connects major computer components (processor, memory, I/O).

 The computer systems I/O is the computer interface to the outside world. Example of I/O are keyboard, monitor, disk drives and floppy drives.

All contemporary computer design are based on concept developed by John Von Neumann
Three key concept : Data and instructions are stored in a single readwrite memory. The contents of this memory are addressable by location, without regard to the type of data contained there. Execution occurs in a sequential fashion from one instruction to the next.

Computer Components : Top-Level View

CPU PC
IR Memory
Instruction Instruction Instruction

MAR
MBR I/O AR I/O BR
Data Data Data Data

I/O Module

PC = Program Counter IR = Instruction Register MAR = Memory Address Register MBR = Memory buffer register I/O AR = I/O address register

Buffers

I/O BR = I/O buffer register

Cont
Register = small number of high speed memory in CPU MAR = specifies the address in memory for the next read or write

MBR = Contains the data to be written into memory or receives the data from memory
I/O AR = specifies a particular I/O device I/O BR = used for the exchange of data between an I/O module and the CPU.

IR = Part of CPU control unit that stores an instruction

PC (instruction address register ISR) = contain address of the next instruction to be execute

COMPUTER FUNCTION

INSTRUCTION EXECUTION
Instruction cycle = The processing required for a single instruction

Instruction Fetch and Execute

The processor fetches (reads) an instruction from memory

The processor increases the PC after each instruction fetch so that it will fetch the next instruction in sequence The fetched instruction is loaded into a register in the processor known as the instruction register (IR)

Instructions execution - The processor interprets the

instruction and performs the required action. An instructions execution may involve a combination of these action categories: Processor-memory: Data may be transferred from processor to memory or from memory to processor. Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module. Data processing: The processor may perform some arithmetic or logic operation on data. Control: An instruction may specify that the sequence of execution be altered.

Halts Program execution halts only if the machine is turn off, some sort of unrecoverable error occurs or a program instruction that halts the computer is encountered.
Only if machine is turned off, unrecoverable error occur or instruction halts is encountered

Start

Fetch Next Instruction

Execute Instruction

Halt

Basic Instruction Cycle

Increase the PC

Example of Program Execution

Using three instruction cycle
AC (accumulator) register in which intermediate results are stored tempororarly
1

First instruction cycle

Second instruction cycle

Third instruction cycle

Example of Program Execution

1.

2.

The PC contains the no. 300, the address of the first instruction. This instruction (the value 1940 in hex) is loaded into the instruction register, IR and the PC is increased. Note that this process would involve the use of a memory address register (MAR) and a memory buffer register (MBR). For simplicity, these intermediate registers are ignored. The first 4 bits (first hex digit 1) in the IR indicate that the AC is to be loaded. The remaining 12 bits (three hex digit) specify the address (940) from which data are to be loaded.

Example of Program Execution (Cont.)

3. The next instruction (5941) is fetched from location 301 and the PC is incremented 4. The old contents of the AC and the contents of location 941 are added and the result is stored in the AC. 5. The next instruction (2941) is fetched from location 302 and the PC is incremented. 6. The contents of the AC are stored in location 941.

Interrupts

Interrupts
The mechanism by which other system modules (I/O, memory) may interrupt the normal processing of the CPU. A signal that gets the attention of the CPU and is usually generated when I/O is required. A hardware interrupt causes the CPU to save its state of execution and begin execution of an interrupt handler. Interrupts are prioritized; the higher the priority, the faster the interrupt will be serviced.

Cont

Most external devices (e.g. printer) are slower than the CPU. CPU can waste vast amounts of processing cycles waiting for these slow devices to perform their tasks. Interrupts let the CPU execute its normal instruction sequence and pause to serve the external devices only when they send a signal (the interrupts) that they are ready for the CPUs attention. The processor and the O/S are responsible for recognizing an interrupt, suspending the user program, servicing the interrupt, and then resuming the user program.

Types of Interrupts
Program Something that occurs as a result of program execution such as illegal instructions, arithmetic overflow, divide by zero, or reference outside the allowed space of memory Timer Generated by a timer within the processor, so that the processor can perform some time-scheduled task
I/O Generated by an I/O controller to request service from the processor such as keyboard, mouse, disk drive (e.g. when a key is pressed or when the mouse is moved)

Hardware failure signifies some error condition with the hardware, such as power failure

Interrupts are processed in an interrupt cycle within the overall instruction cycle At the end of an instruction cycle, processor check to see if any interrupts are pending If there arent any, proceed with the next instruction

If there are
Suspend execution of the program and save its state

Jump to the interrupt service routine (ISR) and execute the instruction cycle
When the ISR is completed, restore the state of the program and resume its operation

Interrupts
How interrupt for write instruction to printer is handled. The user program performs a series of WRITE calls within processing. The I/O program is a program that will perform the actual I/O operation. The WRITE calls in the user program are to the I/O program, which consists of three sections.
A sequence of instructions to prepare for the I/O operation (copying data into a special buffer) (4 in the fig). The actual I/O command that enables the device to perform the requested function. A sequence of instruction (5- in the fig) to test the success or failure of the operation.

Transfer of control with multiple interrupts

Cont

When the preparation and I/O command is executed, the control returns to the user program. When the output device become ready to accept more data from the processor to print it, the I/O module of the device sends an interrupt request signal to the processor. The processor responds by suspending operation of the current program branching off to another program called interrupt handler. After servicing the request of the output device, the processor resumes the original execution.

Interrupt Cycle added to the instruction cycle

1. Processor suspends execution of the current program and save the address of the next instruction to be executed (current content of PC). 2. Sets the PC to the starting address of an interrupt handler routine.

Transfer of control via interrupts

Interrupt handler

Interrupt handler is a program which is part of the operating system. Typically , this program determines the nature of the interrupt and perform any action needed. When this program is completed, the processor can resume execution of user program at the point of interruption.

Multiple interrupts
A typical system can support several dozens of interrupts How should the system respond if more than 1 interrupt occurs at the same time? Systems prioritize the various interrupts At the start of the interrupt cycle, the highest priority pending interrupt will be serviced Remaining interrupt requests will be serviced in turn What if an interrupt occurs while an ISR is being executed (a result of a previous interrupt) Ignore the second interrupt (by disabling interrupts) until the ISR completes Recognize and service the interrupt only if it has a higher priority than the one currently being serviced

Transfer of control with multiple interrupts

End of Part1?