SESSION XVI: A/D and D/A Techniques

FAM 16.1:
A SimpleThree-Terminal IC Bandgap Reference
A. Paul Brokaw Analog Devices, Inc. Wilrnington, Mass.

Chairman:

William G. Howard, Jr.

Motorola Inc., Mesa, Ariz.

A CIRCUIT, illustrated in Figure 2, using collector current sensing to reduce errors and provide more flexibility than the conventional bandgap circuit will be described. Collector current of sensing is used to fix the ratio current density in twotransistors. This ratio generates a temperature-proportional voltage which is added to VBE to produce a temperature-stable sum voltage. Conventional bandgap circuits use parallel current paths with voltage sensing connections between the paths.Thesecircuits are typified by Figure 1, discussed earlier to illustrate the operation of more complex, but fundamentally similar circuits. In this well-known circuit parasitic currents exchanged between the parallel paths are not accounted for in the theory and give rise to beta-dependent voltage errors and temperature drift. To generatehigher voltages with theconventional circuit, it is necessary to stack junctions t o produce a multiple of the or use a amplifier second to multiply the bandgap separately stabilized bandgap voltage. these limitations. The The circuit of Figure 2 overcomes operating principle involves the followingcharacteristics. The emitter area of Q1 is larger than that of Q2. Thus when VOUT is low, making the voltage drop across R 1 and R 2 small, the baseemitter voltage of Q1 nearly equals that of 4 2 . This results ina net collector current exceeds the current in 4 2 . This results in a net positive signal applied to the amplifier which causes the amplifier to raise the output voltage. Alternately, if V ~ U T large, R 2 is limits the current through Q1 to less than the current in 4 2 . The net negative input to the amplifier causes it to reduce the output voltage. As a consequence of these conditions at the extremes, the amplifier drives the circuit output to a voltage resulting in equal collector current in Q1 and Q2. When thecollectorcurrents are equal, the areadifference results in unequal current densities. The current density difference generates a temperature-dependent voltage which appears across R 2 The current in 4 2 equals that in Q1, making the current in R1 twice that in R2. Accordingly, the voltage developed across R, is also temperature dependent as shown by the expression in Figure 2.
Widlar, R. J., IEEE Journal of SolidSlateCircuits, Feb., 1971.
Kuiik, K. E., IEEE Journal of Solid State Circuits, June. 1973.
p. 2; p. 222;

The resistance of R1 is selected so that the total of the two k voltages, VOUT, is equal to the bandgap voltage plus (m-1) To/q. This is the optimum voltage to give zero TC at temperature To. This circuit depends upon alpha match rather than high beta so that the base current is supplied by the amplifier and does not contribute to output error. A usefulfeature of the configuration is illustrated inFigure 3. The control loop stabilizes the base of 42 just above the bandgap voltage. The voltage divider between the circuit output and the base causes the output to be stabilized at a voltage greater than the bandgap voltage. Adding R3 compensates any error due to the base current which flows through R4. Theprincipleillustrated by Figure 3 has been used as the basis for an integratedcircuit voltage-reference design shown schematically in Figure 4. The similarly numberedcomponentsinFigure 4 approximately correspond to those in Figure 3. In the complete circuit, Qlo and 9 1 1 are however, the current mirror transistors bootstrappcd to the stabilized output voltage to improve input voltage rejection ratio. Transistors Q, and 44 act as the output

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3Brokaw, A. P . and Maidique, M. A., A Fast. High-Precision, Laser-Trimmed FET Input Operational Amplifier, issue; this p. 142-1 43.

FIGURE 1-Conventional band-gap circuit.

driver and bootstrap followers with level translation and current gain provided by 43, R6, Q12 and Qg. The level translater Q12 is used to provideequal bias for Q8 and Q g Theratioand impedance of R l o and R11 are selected to force the current in 45 to be equal to the currents in Q 1 and Q2. This current is

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reflected by Q13 andQ14to drive both Q4 the and level translation circuit so that the voltage across R6 is made equal to that across R7 and R8. The epitaxiallayerFET, which is integral with Q5, insures starting. Current-limit protection is provided by Rg and Qs. The chip provides a 2.5 V reference output over a 4.5 V to 40-V input range. Itoperatea at 1-mAstandbycurrent and is fully current limited at the output. Breadboard tests and monolithic realization of a simplified design based on the same circuit concept3 indicate that yield to 30 ppm/OC should be substantial.

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Ehminate error due to base current In R 4 by settlng :

FIGURE 2-Idealized circuit illustrating basic configuration.

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FIGURE 3-Simplified circuit for developing higher output

voltages.

FIGURE 4-Complete circuit of monolithic referencechip.

FIGURE 5-Photograph of 37 mil x 6 2 mil monolithic die showing thin-film resistors and balanced thermal layout.

1 TC1
FIGURE 6-Transconductance and frequency compensationmodel.