Challenges in

Testing

Applying E78 to

Semiconductor Wafer Chambers

by Roger Peirce and Brad Williford, Simco

Aurelko | Dreamstime.com

3 Conformity november 2008

ncontrolled electrostatic charge is a significant and growing problem in semiconductor manufacturing. When a static charge builds up on sensitive products, work surfaces, equipment or personnel, the result can be destructive. Products may be damaged, processes may become degraded, and a long list of other problems may ensue. Product damage from static charge can cost manufacturers millions of dollars in scrapped materials, as well as the loss of potential revenue. In the semiconductor manufacturing industry, damage and yield losses attributed to the effects of static charges are well documented, along with the determination of many of the specific causes1-22. Particle contamination is a major issue, as charged wafers attract more particles to their surfaces than their non-charged counterparts (electrostatic attraction) 2,3,6-10,13,22 . Direct electrical damage caused by electrostatic discharge (ESD) to wafers can occur with a variety of ESD failure modes1, 12,15,16. In addition, ESD events produce electromagnetic interference (EMI) that can cause equipment malfunctions, lockups, and direct damage to products via radiated and conducted forms11, 17-19. Problems Caused Specifically by ESA When a wafer or front-opening universal pod (FOUP) becomes charged, the resulting electric field attracts airborne particulate and airborne molecular contaminants (AMCs) through electrostatic attraction (ESA) in much the same way that a television screen attracts dust. Once bonded to a charged surface, it is very difficult to remove the contamination. As line widths get smaller, the killer particle size needed to create a defect has decreased proportionally, and high-tech manufacturers must concern themselves with controlling increasingly smaller particles. Importantly, the ESA of particles also increases as particle sizes decrease (65, 45, 32 nm geometries), magnifying the problem. AMCs are a type of contaminant that is becoming more of a concern in semiconductor fabs. AMCs come from both organic and inorganic sources, and cannot be removed by HEPA or ULPA filters. Problems with AMCs include poisoning Deep UV photoresist processes, roughening the silicon at the pre-gate clean, and the breakdown of HEPA filter media, which can lead to the release of dopant AMCs, such as Boron. There are indications that electrostatic charge increases the attraction of AMCs to product surfaces. Recent published data in 2006 details the increased particle counts on wafers in highcharge generating containers (due to ESA) versus non-charged counterparts, leading to increased yields when ionization techniques are employed to remove the charging mechanisms. Why E78 Was Developed In 1995, SEMI (Semiconductor Equipment and Materials International) established a standards task force made up of professionals in the semiconductor industry. Their

mission was to create a guide to minimize the impact on capital productivity due to the presence of static charge in semiconductor manufacturing environments. The result of that groups efforts was document E78-0998, Electrostatic Compatibility: Guide to Assess and Control Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment. Revisions were produced as needed, the latest of which is E78-0706, published in 2006. E78 identifies static charge as a factor that can be detrimental to semiconductor manufacturing processes. To combat it, the document promotes implementing preventative measures to limit the amount of static charge generated during the handling and processing of wafers and reticles, and the handling of their FOUP carriers. It sets a limit on charge levels, so that they are not great enough to cause product or reticle damage, attract significantly more particles to surfaces, or cause equipment malfunctions to ESD-induced EMI. It also provides a matrix of recommended charge values (measured in nanocoulombs) and electric field values (measured in volts/cm), depending on the sensitivities of the products and equipment involved. The latest version of E78 expands upon ESD and presents both theory and practical voltage values that should be maintained to eliminate the effect of ESA (increased particles) on wafer surfaces.

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With the publication of E78, tool manufacturers and end users have a common document from which to work when developing their electrostatic management programs. E78 promotes a partnership between tool manufacturers and end users to create products, processes, and cleanroom environments that moderate the effects of static charge. In this partnership, equipment manufacturers design in static control to meet the specified sensitivity levels. Awareness of the problem on both sides is the best way to determine an acceptable level of static charge that will not affect yield or throughput. However, each tool platform is unique in its processes, materials used, and automation employed, and a thorough ESD/ESA characterization should be done to comply with E78 guidelines. SEMI E78-0706 In summary, E78 was developed to minimize the negative impact on productivity caused by static charge in the semiconductor manufacturing environment. It provides methods of measurement and recommendations for maximum levels of allowable charge on wafers, wafer containers, parts of the input/output ports in mini-environments, internal walls and surfaces, etc., in order to eliminate ESD electrical damage to product as well as particle attraction issues. It also provides methods of measurement to ensure immunity to ESD-related equipment failures (ESD stress testing). However, E78 does not address the various inner processes that take place in automated wafer processing equipment. For example, chamber operation evaluations are not required as part of an E78 static risk evaluation of the semiconductor tool. Wafer charging and discharging mechanisms often exist inside these semiconductor tool wafer-processing chambers. The remainder of this article reviews a typical chamber design, along with some of the charging and discharging mechanisms that were detected, documented, analyzed and subsequently eliminated as part of a thorough ESD/ESA chamber evaluation. We feel that such evaluations are important to accomplish along with standard E78 evaluations

and static control implementations in the equipment front-end modules (EFEM) areas that are commonly addressed. Chamber Evaluation In our wafer chamber evaluations, we have frequently observed and determined that any process involving a wet chemical or DI water application has a strong propensity to result in a significant charging event. Therefore, it is essential to remove the charge during and immediately after such a fluid dispensing operations in order to eliminate potential damage to devices on the wafer. In this case study, the chamber was completely enclosed during normal operations similar in structure to a basic chamber design shown in Figure 1. The charging characteristics of the wafer could be measured by both direct contact and non-contact techniques. Real-time voltage monitoring was performed with an oscilloscope. Once the monitoring equipment was in place, the operation was started and the chamber baseline measurement was recorded (see Figure 2). The voltage on the wafer inside the chamber was monitored continuously in real-time in order to determine all potential risks with the operations. As can be followed on the scope trace in Figure 2, the points of interest corresponding to major transitions during the process recipe are reviewed below: 1. Fixture movement charges wafer: The voltage on the wafer spikes to +2Kv due to the up/down movement of the wafer. Fluid discharges wafer: A rapid discharge of the wafer occurs when the first fluid application begins. Such a rapid discharge is often responsible for charged device model (CMD) ESD damage to the devices on the wafer. Static sparks can be visually witnessed on occasion with such a discharge if the voltage levels are high enough. Some have even caused pit mark type damage to the wafer surface. However, even without an ESD pitting event, severe damage can occur to the device. Spinning fixture recharges wafer: As the chuck begins spinning at a relatively low RPM, the wafer begins to charge negatively (to 1Kv approximately). Fluid discharges wafer: The (negatively) charged wafer now dangerously discharges at the beginning of the second fluid application. CDM ESD damage is likely at this point in the process recipe. Spinning fluid recharges wafer: The wafer again significantly charges when the high-speed spin process begins and fluid is radially slung from the wafer. The voltage on the wafer at this point reaches +6Kv, which is typical in many high-speed wafer-drying operations.

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Figure 1: Typical wafer chamber design

38 Conformity november 2008

6.

Robot arm discharges wafer: The wafer remains highly charged through the rest of the operations until discharged (a third time) by contact with the grounded robot arm assembly that retrieves the wafer from the chamber and returns it to a FOUP.

When viewing the wafer charging profile above, it is important to note that CDM ESD damage is likely at the three points where the wafer discharges rapidly (points #2, #4, and #6 above). The goal is to avoid damage of this kind by removing the charge from the wafer (safely via ionization, typically) before the discharge mechanism takes place. An air-assisted ionizing device was installed in the chamber to eliminate this discharge event. A number of ionizer solutions were evaluated with varying results, but the most effective ionizer solution produced the wafer charging profile shown in Figure 3. The red scope trace shown in Figure 3 is the wafer-charging profile with the ionizer activated in the chamber. (The black trace is superimposed from the earlier baseline plot.) 1. Fixture movement charges wafer: The voltage on the wafer spikes to +2Kv, but the ionization immediately begins safely discharging the wafer. The entire charge has been eliminated before the upcoming fluid application (#2). Fluid does not discharge wafer: As there is no charge on the wafer, the dangerous baseline discharge has been eliminated. Spinning fixture recharges wafer: As the chuck begins spinning at a relatively low RPM, the ionizer can keep up somewhat with the more gradual charging mechanism. The 1Kv level is never reached. Ultimately, the wafer has been discharged completely before the next fluid application (#4). Fluid does not discharge wafer: As there is no charge on the wafer, the dangerous baseline discharge has been eliminated. Spinning fluid recharges wafer: The wafer again charges dramatically when the highspeed spin process begins (ionization cant keep up initially) as the fluid is radially slung from the wafer. The voltage on the wafer at this point reaches +6Kv, which is typical in many such spin-off operations.
Figure 2: Baselineno ionization

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Figure 3: Constant ionization throughout processing

november 2008 Conformity 39

However, the ionization safely removes the charge well before the upcoming baseline robot arm discharge (#6). 6. Robot arm does not discharge wafer: The wafer is not charged by the time the robot arm makes contact.

However, the solution was not yet perfected. When the ionization was in constant operation in step #5 above, the airflow from it caused a potential contamination problem in the process itself. Specifically, the normal fluid spin-off was disrupted by the airflow from the ionizer, and insufficient wafer cleanliness (water spots, essentially) was observed as a result. To correct this phenomenon, the ionizer airflow was shut off just before the step #5 charging mechanism, and turned back on after a few seconds delay. This was necessary to complete the fluid spin-off step, but still allow for complete discharge during the remainder of the process. Floating Metal and FOUP Issues The single wafer chamber (evaluated above) processes wafers with active metal structures on them. Even with the wafer potentially grounded in the chamber fixture, it is noted that simply grounding the wafer in the chamber does not ensure that all electrical damage possibilities to wafers are eliminated.

As an example (even if most of its metal structures are grounded), there are many wafers that may have additional floating metal structures internally insulated electrically from the grounded structures. It is still possible for CDM discharges to occur when the wafer is grounded. Floating structures can become charged inductively and then discharge internally to the grounded structures. Many case studies exist where floating metal structures have been an integral part of CDM damage. Implementation of ionization inside (chamber) mini-environments is often necessary to guard against ESD and ESA. There is another example of why simply grounding the wafer in the tool chamber is not reliable enough to eliminate all ESD and ESA issues. Charging mechanisms can occur to wafers in a FOUP, even though the wafer is connected to ground internally in the FOUP itself. FOUP designs incorporate an inner (skeletal) fixture that is designed to keep the wafers at ground potential during normal operations. However, recent studies22 have conclusively proven that native oxides on wafer surfaces can prevent good grounding contact of the wafer by this fixture, and that the wafer can be essentially a floating conductor. As the rest of the FOUP container is constructed from plastics that can charge greatly during normal handling and which is in close proximity to the wafers, the resulting large fields couple into the floating wafer and cause it to charge inductively. Charged wafers consequently attract more particles, and run the risk of electrical ESD damage when contacted by subsequent conductors, such as robot arm assemblies. Recent studies are available that document substantially increased particle counts on wafers transferred in and out of FOUPs when ionization equipment is not implemented22. Summary Wafer charging hazards can exist in semiconductor tool chamber minienvironments, even when ionization resides in other areas of the tool (equipment front-end, or EFEM, and process modules). It is important to evaluate the process steps involved in real time to properly characterize and eliminate potential ESD, ESA, and EMI failure modes. Real time monitoring of the wafer is a prerequisite to characterize the risks in the chamber thoroughly. Eliminating potential ESD, ESA, and EMI failure modes in the chamber mini-environment and inside the semiconductor tool is an important part of an overall yield improvement program, and should be considered an important addition to standard E78 evaluations.

Figure 4: Selective ionization throughout process

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Roger J. Peirce is Director of Technical Services for Simco Ionization for Electronics Manufacture, and can be reached at rpeirce@esimco.com. Brad Williford is Global Semiconductor OEM Accounts Manager for Simcos semiconductor ionization products, and can be reached at bwilliford@esimco.com.
References 1. 2. 3. 4. R.J. Peirce, CDM ESD Failure Modes in the Semiconductor Industry, Solid State Technology, May 2007. M. Inoue et al., Aerosol Deposition on Wafers, IES Proceedings, 34th Annual Technical Meeting, 1988. R.P. Donovan, Particle Control For Semiconductor Manufacturing, New York, Marcel Decker Inc., 1990. Semi E78-0706, Electrostatic Compatibility Guide to Assess and Control Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment, SEMI, San Jose, CA. Semi E129-0706, Guide To Controlling Electrostatic Charge in a Semiconductor Manufacturing Facility, SEMI, San Jose, CA. Frank Curran, MS thesis, The Effects of Static Charge on Silicon Wafers in the Semiconductor Industry, The Engineering Council of England, Nov. 1997. L.B. Levit et al., Contamination Control in Semiconductor Manufacturing, Proceedings of SEMICON Taiwan, Taipei, Taiwan, Sept. 1999. L.B. Levit, T.M. Hanley, F. Curran, Watch Out For Electrostatic Attraction, Solid State Technology, June 2000. C.W. Long, J. Peterman, L.B. Levit, Implementing a Static Control Program to Increase the Efficiency of Wet Cleaning Tools, MICRO, Jan/Feb. 2006.

16. J. Montoya, L.B. Levit, A. English, A Study of the Mechanisms for ESD Damage to Reticles, Proceedings of the 22nd Annual EOS/ESD Society, Rome, NY, ESD Association, 2000, 394-405. 17. A. Steinman, L.B. Levit, Its The Hardware, No, Software, No, Its ESD! Solid State Technology Supplement, May 1999. 18. A.C. Rudack, M. Pendley, and L.B. Levit, Measurement Technique Developed to Evaluate Transient EMI in a Photo Bay With and Without Ionization, Proceedings of EOS/ESD Symposium 2000, Rome, NY, ESD Association, 2000, 379386. 19. J. Rush, et al., Reducing Static-Related Defects and Controller Problems in Semiconductor Production Automation Equipment, Proceedings of the SEMI Ultraclean Manufacturing Symposium, Oct. 1994. 20. G. Baumgartner, The Misconceptions of Air Flow as a Tribocharging Source, Proceedings of the 1992 EOS/ESD Symposium. 21. Niels Jonassen, Induction: What It Means to ESD, Compliance Engineering Mr. Static Series. 22. A. Steinman, L.B. Levit, C. Avery Improving Particle Contamination Control with In-Tool Air Ionization Solid State Technology, March 2007.

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10. M. Harrison, Evaluation of Electrostatic Charges on Aerosol Particle Attractiveness to Silicon Wafers in Class-1 Cleanrooms, Journal of the IEST, Jul/Aug. 1999. 11. L.B. Levit, L.G. Henry, J.A. Montoya, F.A. Marcelli, R.P. Lucero, Investigating FOUPs as a Source of ESD-Induced electromagnetic Interference, MICRO, Apr. 2002. 12. J. Wiley, A. Steinman, Investigating a New Generation of ESD-Induced Reticle Defects, MICRO 17, no. 4, 1999. 13. L.B. Levit, A. Steinman, Investigating Static Charge Issues in Photolithography Areas, MICRO, June 2000. 14. M. Yost et al., Electrostatic Attraction and Particle Control, Microcontamination 4, no. 6, 1986. 15. P.R. Bossard, R.G. Chemelli, B.A. Unger, Charged Device Model ESD, Proceedings EOS/ESD Symposium, San Diego, CA, 1980.

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