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EE141 EECS141
Lecture #5
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EE141 EECS141
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Class Material
Last lecture
Detailed Switch Model CMOS Gates Design Rules
Todays lecture
Overview of semiconductor memory
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Semiconductor Memory
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Why Memory?
Intel 45nm Core 2
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Read-Only Memory
Random Access
Non-Random Access
FLASH
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DYNAMIC (DRAM)
Periodic refresh required Smaller (1-3 transistors/cell) Slower Single Ended
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If D is high, D_b will be driven low Which makes D stay high Positive feedback
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V o1
o V
Vi2
V 5
V o2 = V i 1
2 i
V i1 A
1
V o2
V i 2 = V o1
o V 5 2 i
B V i 1 = V o2
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Writing a 1
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Memory Cell
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SRAM Column
WL0
WL2
WL3
BL
BL_B
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65nm SRAM
ST/Philips/Motorola
Access Transistor
Pull down
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Pull up
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Decoders
M bits S0 S1 S2 S0 A0 A1 M bits Word 0 Word 1 Word 2 Storage cell Word 0 Word 1 Word 2 Storage cell
wo r d s
SN 2 2 SN 2 1
De c o d e r
Word N 2 2 Word N 2 1
Intuitive architecture for N x M memory Too many select signals: N words == N select signals
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K = log2N
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Row Decoders
Collection of 2M complex logic gates Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
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Problem Setup
Goal: Build fastest, lowest possible power decoder with static CMOS logic What we know
Basically need 256 AND gates, each one of them drives one word line
N=8
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Possible AND8
Build 8-input NAND gate using 2-input gates and inverters Is this the best we can do? Is this better than using fewer NAND4 gates?
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Possible Decoder
256 8-input AND gates
Each built out of tree of NAND gates and inverters
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Next Lecture
Buffer delay optimization
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