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Circular Buffers in VHDL


Marc-Julien objois, Catherine Single, Charlena Fong, and Mari a Shterngart

Introduction
I ce ai a ica i , a a da d i ea b ffe i e ai ai i g a a ica i ed i ea b ffe (a i b ffe ). The f c i a i f ch a b ffe e i e he a e e ee e be i e ed a he begi i g f he b he a e be hif ed e b e add e i e ecce a . Thi e a ef ci . ai i i a a d. Ta e f i a ce eeded i ai ai i g a a di i ee e be di ed f a d he ffe . Thi d e i e a ee e b .D i g i i ec i ga d ie hif i g f b c f

ffe ed b a ci c a b ffe , hich e

Theor
T i e e hi f c i a i , a b c f e i ec i ed ff hich acc da e he be f e e e eed e. F be ef a ce, e a i e ha i a e f I he e e a e i age , a i e f 8 e e e i ch e ( i h i de e i a e da a id h). T i e a egi e be ai ai ed. .

Fig. 1: Initial state of the buffer Fig. 1 h he 8 e e e f he b ffe ( abe ed 1 h gh 8) a d he he i e . A e , he "g e ed " f he ce abe ea i e . N e ha he ead i e i a he e d a d he i e i e i ca i ca be e a bi a i g a he ead i e i e e ha (i c di g a i g) he i e i e . ca i e e e ed b he ha e bee a he a . The e e add e e

A ie eai ace he da a be i e i he ca i i ed b he i e i e , c ie he a e f he c e ie i e i he ead i e , he i c e e he i e i e b 1. The a e f he i e af e 3 i e e a i i h i Fig. 2.

Fig. 2: After 3 write operations


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The i e poin e i al a a he ne loca ion he e da a ho ld be i en, and he ead poin e i al a e o he la i en elemen af e a i e ope a ion. In Fig. 2, he da ke label mean elemen 1, 2, and 3 ha e been i en o.

Fig. 3: A read opera ion Fig. 3 ho he e l af e a ingle ead ope a ion af e he a e of Fig. 2. To ead, he da a a he ead poin e i placed on he o p da a b , and he ead poin e i dec emen ed b one. In hi ca e, elemen #3, he la elemen o be i en o he b ffe , i ead.

Fig. 4: Af er ano her read opera ion In Fig. 4, he ne o la elemen o be i en i ead. Thi i he econd ead ope a ion. Read ope a ion con in e in hi manne , apping a o nd f om he lef end o he igh end of he b ffe . When he ead poin e eache he i e poin e , he la elemen ha been ead. Thi ma o ma no be impo an o he VHDL p og amme .

Implemen a ion
A imple implemen a ion can be achie ed in VHDL ing a minim m of inp and o p . Again, make e a po e of o i cho en fo he i e of he b ffe . Thi make managing he poin e ea ie . The en i decla a ion i a follo :
ett crua_ufri ni iclrbfe s gnrc(a_aawdh:itgr: 4 eei rmdt_it nee = ; - wdho dt - it f aa rmadeswdh:itgr: 1 - wdho ades a_drs_it nee = ; - it f drs nmvle :itgr: 2; u_aus nee = ) - nme o vle - ubr f aus pr( ot ra :i sdlgc ed n t_oi; wie:i sdlgc rt n t_oi; rst:i sdlgc ee n t_oi; dti :i sdlgcvco(a_aawdh1dwt 0; aan n t_oi_etrrmdt_it- ono ) dtot:otsdlgcvco(a_aawdh1dwt 0; aau u t_oi_etrrmdt_it- ono ) dt_ed :otsdlgc aara u t_oi; ck:i sdlgc l n t_oi ) ; edcrua_ufr n iclrbfe;

The gene ic a e and da a id h .

ed o con ol l m r m d a p_a_q

ell a managing he ci c la b ffe ' add e

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In an idle a e, he r a and w i eline m be lef lo . The r s tline ho ld be cho en o be ed rt ee ac i e high o lo depending on p efe ence. To i e o he b ffe , a VHDL con c m p he da a on he d t i inp aan ignal, and e he w i eline o high. Thi ini ia e a rt i e c cle. A oon a he d t _ e d line goe high, he aara ope a ion i comple e. The b ffe i hen ead o pe fo m ano he ope a ion. To ead f om he b ffe , impl e r a o high and ai fo he d t _ e d line o go high. On ed aara he i ing edge of d t _ e d , The da a on d t o t ill be alid. The da a ho ld be la ched a aara aau hi poin . On he ne c cle, he b ffe i ead fo ano he ope a ion. The r a and w i eline ed rt ho ld be m all e cl i e.

He e i a p opo ed a e machine fo he ci c la b ffe implemen a ion. No e ha he choice of a b ffe i e ha i a po e of o mean he n he i ed code can be malle , a he e i no need fo bo nd checking. Adding a '1' bi o he bina n mbe '111' ep e en ed ing h ee bi e l in '000.'

Fig. 5: S a e Diagram Thi can be adap ed o ha e e peed i needed fo indi id al p ojec .

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